esigning Sequenial Logic Circuis Adaped from Chaper 7 of igial egraed Circuis A esign Perspecive Jan M. Rabaey e al. Copyrigh 23 Prenice Hall/Pearson Sequenial Logic pus Curren Sae COMBINATIONAL LOGIC Regisers 2 sorage mechanisms posiive feedback charge-based pus Nex sae Naming Convenions Lach versus Regiser our ex: a lach is level sensiive a regiser is edge-riggered There are many differen naming convenions For insance, many books call edgeriggered elemens flip-flops This leads o confusion however Lach sores daa when clock is low Regiser sores daa when clock rises
Laches Lach-Based esign Posiive Lach G Negaive Lach G N lach is ransparen when φ = φ P lach is ransparen when φ = clk clk N Lach Logic P Lach sable follows sable follows Logic Timing efiniions Characerizing Timing 2 su hold Regiser ATA STABLE c 2 q ATA STABLE C 2 C 2 Regiser Lach
o 5 o 2 i 5 o 2 i Maximum Frequency Posiive Feedback: Bi-Sabiliy i o = i2 o2 φ o i2 FF s o2 = i LOGIC p,comb clk- + p,comb + seup = T Also: cdreg + cdlogic > hold cd : conaminaion delay = minimum delay i2 = o i A C B o2 i = o2 Mea-Sabiliy Wriing ino a Saic Lach i2 5 o A C i2 5 o A C Use he clock as a decoupling signal, ha disinguishes beween he ransparen and opaque saes B B d i 5 o2 d i 5 o2 Gain should be larger han in he ransiion region Convering ino a MU Forcing he sae (can implemen as NMOS-only)
Mux-Based Laches Negaive lach (ransparen when = ) Posiive lach (ransparen when = ) Mux-Based Lach = + = + Mux-Based Lach Maser-Slave (Edge-Triggered) Regiser Slave Maser M M M M NMOS only Non-overlapping clocks Two opposie laches rigger on edge Also called maser-slave lach pair
Maser-Slave Regiser - elay Muliplexer-based lach pair I 2 I T 2 T I 3 I 5 T 4 M I 4 T 3 I 6 ols.5.5 c 2 q(lh) c 2 q(hl) 2.5.5.5 2 ime, nsec Seup Reduced Load Maser-Slave Regiser 3. 2. M 3. 2. I 2 2 T 2 ols.5. ols.5. T I T 2 I 3.5. I 2 2 T 2.5. M I 2 I 4 2.5.2.4.6.8 ime (nsec) 2.5.2.4.6.8 ime (nsec) (a) T seup 5.2 nsec (b) T seup 5.2 nsec
Avoiding Overlap A B (a) Schemaic diagram S R Overpowering he Feedback Loop Cross-Coupled Coupled Pairs NOR-based se-rese S R S R Forbidden Sae (b) Overlapping clock pairs Cross-Coupled Coupled NAN Sizing Issues Cross-coupled NANs S R S Added clock M M 4 M 8 M 7 R (ols) 2..5..5. 2. 3. W/L 5 and 6 (a) 3.5 4. ols 3 2 W =.9 µ m W = µ m.2.4.6.8.2.4.6.8 2 ime (ns) (b) S W =.5 µ m W =.6 µ m W =.7 µ m W =.8 µ m This is no used in daapahs any more, bu is a basic building memory cell pu volage dependence on ransisor widh Transien response
Sorage Mechanisms Making a ynamic Lach Pseudo-Saic Saic ynamic (charge-based) More Precise Seup Seup/Hold Illusraions Circui before clock arrival (Seup- case) (a) v TG v2 M - elay T -.5 C 2 C 2 aa T Seup- Su 2 C T Seup- H (b) =
Seup/Hold Illusraions Seup/Hold Illusraions Circui before clock arrival (Seup- case) Circui before clock arrival (Seup- case) TG v2 M - elay TG v2 M - elay v v T - T - aa T Seup- aa T Seup- T Seup- T Seup- = = Seup/Hold Illusraions Seup/Hold Illusraions Circui before clock arrival (Seup- case) Circui before clock arrival (Seup- case) TG v2 M - elay TG v2 M - elay T - v v T - aa T Seup- aa T Seup- T Seup- T Seup- = =
Seup/Hold Illusraions Hold- case Seup/Hold Illusraions Hold- case TG v2 M - elay TG v2 M - elay v v T - T - aa T Hold- aa T Hold- T Hold- T Hold- = = Seup/Hold Illusraions Seup/Hold Illusraions Hold- case Hold- case TG v2 M - elay TG v2 M - elay v v T - T - T Hold- aa T Hold- T Hold- aa T Hold- = =
Seup/Hold Illusraions Oher Laches/Regisers: C 2 MOS Hold- case v TG v2 M T - - elay M 4 M 8 C L M 7 C L2 T Hold- aa T Hold- M Maser Sage Slave Sage = Keepers can be added o make circui pseudo-saic sensiive o -Overlap Oher Laches/Regisers: TSPC M 4 M 8 M 7 M M (a) (-) overlap (b) (-) overlap Posiive lach (ransparen when = ) Negaive lach (ransparen when = )
cluding Logic in TSPC TSPC Regiser PUN 2 Y M 9 M 8 PN 2 M M 4 M 7 Example: logic inside he lach AN lach Pulse-Triggered Laches An Alernaive Approach Pulsed Laches Ways o design an edge-riggered sequenial cell: Maser-Slave Laches aa L L2 L aa Pulse-Triggered Lach G G M (a) regiser M 4 M P M N (b) glich generaion G G (c) glich clock
Pulsed Laches Hybrid Lach-FF Timing Hybrid Lach Flip-flop (HLFF), AM K-6 and K-7 : 3. P x P 2 P 3 ols 2..5. M M 4.5...2.4.6.8. ime (ns) Pipelining Lach-Based Pipeline a a log log b b F G C C 2 C 3 Reference Pipelined Compue F compue G
() () x Non-Bisable Sequenial Circuis Schmi Trigger Noise Suppression using Schmi Trigger ou OH in ou M+ TC wih hyseresis OL M Resores signal slopes + p M M+ in CMOS Schmi Trigger Schmi Trigger Simulaed TC M 4 2. 2. in ou.5 M.5 M..5 M2..5 k= k= 2 k= 3 k= 4 Moves swiching hreshold of he firs inverer...5..5 2. in () olage-ransfer characerisics wih hyseresis....5..5 2. in () The effec of varying he raio of he PMOS device M 4. The widh is k*.5 m m.
CMOS Schmi Trigger (2) Mulivibraor Circuis R M 4 S Bisable Mulivibraor flip-flop, Schmi Trigger T Monosable Mulivibraor one-sho M Asable Mulivibraor oscillaor Transiion-Triggered Triggered Monosable Monosable Trigger (RC-based) A R B ELAY d d C (a) Trigger circui. B M (b) Waveforms. 2
Asable Mulivibraors (Oscillaors) olage Conroller Oscillaor (CO) 2 N- Schmi Trigger resores signal slopes M6 M4 3. 3 5 Ring Oscillaor I ref M2 M I ref ols 2..5. conr M5 M3 Curren sarved inverer.5 6...5..5 ime (ns) simulaed response of 5-sage oscillaor ph L (nsec) 4 2..5.5 conr () propagaion delay as a funcion of conrol volage ifferenial elay Elemen and CO o2 o v 3 in in2 v v 2 v 4 crl delay cell 3. 2 3 4 2..5..5. wo sage CO 2.5.5.5 ime (ns) 3.5 simulaed waveforms of 2-sage CO