Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0

MOS Models & Parameter Extraction Workgroup Arbeitskreis MOS Modelle & Parameterextraktion XFAB, Erfurt, Germany, October 2, 2002 Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 Matthias Bucher, Ph.D. mbucher@tee.gr National Technical University of Athens (NTUA), Athens, Greece Smart Silicon Systems S.A., Lausanne, Switzerland Acknowledgements Dimitris Kazazis David Binkley Daniel Foty François Krummenacher M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 2

Outline Introduction EKV MOSFET model formulation Analysis of transconductances vs. level of inversion and channel length Measurement of 0.25um CMOS Comparison with EKV 3.0 MOSFET model Conclusions M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 3 CMOS Technology Evolution Rapid scaling of CMOS technology Increasing complexity of CMOS technology (mostly driven by digital) Analog/mixed signal, wireless RF, LV-LP battery operated equipment requires novel circuit solutions. Moderate/weak inversion increasingly important. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 4

Design-Gap in Analog Gap in analog design productivity is especially severe Lack of understanding of MOSFET physics. Lack of adequate tools, methods and models for design. A new method is needed for: Rapid evaluation of design trade-offs: gain, bandwidth, linearity, matching, noise, chip area. Hand-calculation and full circuit simulation. Transconductance method based on EKV MOS transistor model: Analysis vs. level of inversion & channel length. Measurement vs. level of inversion & channel length. EKV 3.0 MOSFET model for deep submicron CMOS. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 5 MOS Transistor Basic Definitions B V S V G V D S V S G V G L D V D I D p + n + n + poly t ox n + x L eff p substrate (N sub ) Source-, gate-, drain- and substrate transconductances: y g ms ( ID ) g mg VS V V G, V G D g mb = g ms g mg g md I D I g md D V D V S, V D V G, V S M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 6

Normalization of Drain Current and Voltages ID [A].0E-02.0E-03.0E-04.0E-05.0E-06.0E-07.0E-08.0E-09.0E-0.0E- V S =0V.0E-2 V D =.5V WEAK INV. MOD. INV. STRONG INV. V S =0.8V -0.2 0 0.2 0.4 0.6 0.8.2.4 VG [V] Specific Current: I SPEC 2 W I Spec = 2nU T µc ox ---- L Inversion Coefficient: = I D I Spec 0 0. 0 0. Strong Inversion Moderate Inversion Weak Inversion Inversion Coefficient () is meaningful for operation in saturation... covering all the range from weak to strong inversion Normalization of voltages by U T = kt q: υ G( S, D) V. = G( S, D) U T M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 7 Inversion Charge Linearization Inversion Charge Linearization: Pinch-off Surface Potential: Pinch-off Voltage: dq i ---------- n dψ C ox S Ψ SP Ψ S Qi = 0 V P Ψ SP φ Consider charge and voltage balance in the MOS structure: Q i Ψ ---------- γ U S Ψ C ox T ------ S 2φ F V + exp ------------------------------------ ch Ψ = ------ S Q V G V FB Ψ S γ Ψ i = + + S ---------- C ox U T Q i Ψ S V G is almost linear w.r.t. surface potential at fixed. Linearization is essential to analytic charge-sheet model. U T U T M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 8

Pinch-off Voltage, Slope Factor Slope Factor: dv n G = + ----------------------- γ dv P 2 φ + V P Pinch-off Voltage: V V G V TO P ---------------------- n V TO = V FB + φ+ γ φ γ = 2qε si N ---------------------------- sub C ox ε C ox ox = ------- T ox N sub n i φ 2φ F + m U T = U T 2 ln ---------- + m m 2 3 V P, n account for the substrate effect T ox, N sub, V FB, same parameters as in surface potential model (long-ch.) V P, n also include short-channel effects (DIBL, charge-sharing, RSCE...) M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 9 Charge Sheet Model Consider drift and diffusion current transport, use linearization: I D dx µw[ Q i dψ S + U T dq i ] µw Q i = = ------------- + U nc T dq i ox Integrate from source to drain: 2 I D = 2nU T µc W ox ---- ( i L f i r ) = I Spec ( i f i r ) 2 i fr q fr with current-charge relationships: = + q fr or, q fr = 4 + i fr Consider channel conductance: di D = µ W ---- ( L Q i ) dv ch... in normalized form: di fr d q υ fr SD = = -- + i 4 fr = i fr Integration yields voltage-charge relationship: υ P υ SD = 2q fr + q fr ln Gi fr M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 0

Drain Current in Saturation Drain Current: I D = I Spec ( i f i r ) Drain Current (saturation): I D I Spec i f i f >> i r Symmetric forward/reverse normalized current: i fr = F[ υ P υ SD ] i = -- [ υ fr 4 P υ SD ] 2 SI: υ P υ ln + exp ------------------------ SD WI: i fr = exp( υ P υ SD ) 2 2 Example: asymptotic drain current expressions in saturation: SI: WI: nβ I D = ------ [ V 2 P V S ] 2 2 V I D 2nβU P V = exp S T ------------------ U T where: β = µc W ox ---- L M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 Transconductance-to-Current Ratio WEAK INV. MOD. INV. G = ----------------------------- -- + -- + 2 4 STRONG INV. G(): normalized transconductance-to-current ratio: compared to exact surface potential model compared to measurements (4 different CMOS technologies) G() vs. is universal, over bias conditions (saturation), temperature, technology. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 2

Transconductances Analysis Fundamental relationships: g g ms g md n mg = -------------------- g n mb = ----------- g n mg Transconductance-to-current ratios: g G mx U T x ------------------- I D st -order expressions of transconductance-to-current ratios: G G G --------------- G n S G G n G ----------- G n G D G V P + V D U ------ T n n V D (weak-moderate inversion) st -order expressions are valid mostly in moderate & weak inversion. G D is also directly dependent on G() and short-channel effects in V P, n M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 3 Gate Transconductance -- Bsim3v3 Model 0.8 0.7 0.6 BSIM3v3 gmg * UT / ID 0.5 0.4 0.3 0.2 measured 0. 0 E-06 E-05 0.000 0.00 0.0 0. 0 00 000 g m *U T /I D vs. I D /I spec (log): BSIM3v3 model cannot fit a large range in moderate/weak inversion (parameter extraction dependent; but the problem is structural). measured at V G = 0... V DD, V S =0, V D =V G (saturation). M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 4

Gate Transconductance -- EKV 3.0 0.8 0.7 /n 0.6 EKV 3.0 gmg * UT / ID 0.5 0.4 0.3 G()/n 0.2 L=0.28um 0. 0 E-06 0.0000 0.000 0.00 0.0 0. 0 00 000 EKV 3.0 fit from weak to strong inversion, for long & short channel devices (NMOS) Asymptote in weak inversion: /n Weak inversion slope (S~=ln0.n.U T ) is dependent on n(v G ). M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 5 Source Transconductance -- EKV 3.0 0.9 0.8 ~ EKV 3.0 gms * UT / ID 0.7 0.6 0.5 0.4 0.3 0.2 L=0.28um G() 0. 0 E-06 0.0000 0.000 0.00 0.0 0. 0 00 000 g ms *U T /I D vs. is universal (in saturation, independent of gate voltage, temperature, channel length except very short channel) Asymptote in weak inversion: ~ g mg ~= g ms /n (saturation) M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 6

Substrate Transconductance -- EKV 3.0 gmb * UT / ID 0.4 0.3 0.2 0. L=0.28um (n-)/n EKV 3.0 G()*(n-)/n 0 E-06 0.0000 0.000 0.00 0.0 0. 0 00 000 g mb *U T /I D vs. is dependent on substrate effect Asymptote in weak inversion: (n-)/n g mb ~= g ms *(n-)/n M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 7 Drain Transconductance -- EKV 3.0 0. 0.0 gmd * UT / ID 0.00 EKV 3.0 0.000 L=0.28um 0.0000 E-06 0.0000 0.000 0.00 0.0 0. 0 00 000 g md *U T /I D = U T /V A where V A = I D /g md is Early voltage. G D () = g md *U T /I D shows very strong dependence on L! st-order G D tends to underestimate the measured g md *U T /I D M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 8

Drain Transconductance -- EKV 3.0 0. NMOS 0. PMOS gmd * UT / ID 0.0 0.00 0.000 0.28um 0.36um 0.5um um 3um gmd * UT / ID 0.0 0.00 0.000 0.28um 0.5um um 2um 0.0000 E-06 E-05 E-04 0.00 0.0 0. 0 00 000 0.0000 E-05 0.000 0.00 0.0 0. 0 00 000 g md *U T /I D reveals different scaling for NMOS and PMOS WI: dominated by DIBL, Charge-sharing SI: dominated by Vel. Sat., CLM, self-heating EKV 3.0 shows excellent g md *U T /I D modeling with, L M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 9 DC Self-Gain -- EKV 3.0 gmg / gmd 0000 000 00 3um um 0.5um 0.36um 0.28um NMOS gmg / gmd 0000 000 00 2um um 0.5um 0.28um PMOS 0 E-06 E-05 0.000 0.00 0.0 0. 0 00 000 0 E-05 E-04 0.00 0.0 0. 0 00 000 Intrinsic gain g mg / g md is highest in moderate (!) inversion, long L g mg / g md is low-frequency gain in a common-source amplifier stage analog design can profit from high gain in MI, non-minimum L. EKV 3.0 shows excellent scaling. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 20

Conclusions EKV MOS transistor model is a physics based, design-oriented model for deep submicron CMOS: combines surface-potential model & inversion charge linearization consistent normalization, symmetry provides ideal framework for analysis of MOS transistor characteristics Source, Gate, Substrate and Drain Transconductances have been measured in 0.25um CMOS and analyzed with EKV model: correctly model all transconductances vs. level of inversion () and channel lengths is not trivial transconductance method provides useful information for advanced analog design, model parameter extraction & benchmarking method is applicable over many CMOS generations New EKV 3.0 model shows excellent abilities for transconductance-tocurrent ratios modeling at all levels of inversion and channel lengths. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 2 Contact & Reference Matthias Bucher, Ph.D. Smart Silicon Systems S.A. Graviere 6, 007 Lausanne, Switzerland http://www.smartsilicon.ch/ mb@smartsilicon.ch National Technical University Athens (NTUA) Zographou, 55 73 Athens, Greece http://www.elab.ntua.gr/ mbucher@tee.gr EKV 2.6 website (Wladek Grabinski): http://legwww.epfl.ch/ekv/ Main Reference: M. Bucher, D. Kazazis, F.Krummenacher, D. Binkley, D. Foty, Y.Papananos, Analysis of Transconductances at All Levels of Inversion in Deep Submicron CMOS, Proc. 9th IEEE Conf. on Electronics, Circuits and Systems (ECS 2002), Vol. III, pp. 83-86, Dubrovnik, Croatia, September 2002. M. BUCHER 0/2002 MOS-WORKGROUP MEETING, XFAB, ERFURT, GERMANY, OCTOBER 2, 2002 22