INSTRUMENTATION and control systems are now implemented

2576 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 11, NOVEMBER 2008 Digital Converter for Differential Capacitive Sensors N. Madhu Mohan, Student Member, IEEE,AmolRavikantShet, S. Kedarnath, and V. Jagadeesh Kumar, Member, IEEE Abstract A digital converter that directly translates variations in the capacitances of a differential-type capacitive sensor to a proportional digital value is described in this paper. A conventional dual-slope, analog-to-digital converter is suitably modified to obtain direct capacitance-to-digital conversion CDC). Analysis of the proposed technique indicates that the effects of nonidealities and variations in circuit parameters on the performance of the CDC is either in the form of a gain error and/or an offset, both of which can be easily compensated. Simulation studies and experimental results obtained from a prototype built and tested prove the efficacy of the proposed scheme. Index Terms Capacitance-to-digital converter, differential capacitive sensor, digital converter, dual-slope technique, sensor signal conditioning. I. INTRODUCTION INSTRUMENTATION and control systems are now implemented in the digital domain since digital systems offer better user interface and excellent signal processing power compared to their analog counterparts. However, most of the transducers employed in an instrumentation system for sensing different parameters are analog in nature and provide analog outputs. A typical transducer is made of a sensor connected to an analog-signal-conditioning circuit. The latter circuit operates on the elements of the sensor and provides an analog output. To interface a transducer with an analog output to a digital system, it is necessary to convert the analog output into digital form using an analog-to-digital converter ADC). It would be advantageous if the variations in the sensor elements were directly converted into proportional digital values. Direct sensorto-digital conversion methods invariably possess reduced complexity and provide increased reliability. The capacitanceto-frequency or time period) conversion techniques proposed earlier [1] [3], which are suitable for signal conditioning a differential push pull)-type capacitive sensor, meet this requirement halfway. An ADC is not required to interface a transducer possessing a frequency or time) output to a digital system. However, to interface a transducer with a frequency or time period) output to a digital system, the digital system should be designed to be capable of converting the frequency or time period) into a digital value. Manuscript received October 7, 2007; revised February 27, 2008. First published May 16, 2008; current version published October 10, 2008. N. M. Mohan, S. Kedarnath, and V. J. Kumar are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600 036, India e-mail: vjk@iitm.ac.in). A. R. Shet was with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600 036, India. He is now with Texas Instruments, Bangalore 560 093, India. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2008.922109 Fig. 1. Schematic of the proposed dual-slope capacitance-to-digital converter. We now propose a novel capacitance-to-digital converter that provides a final digital output that can be directly interfaced to a digital system [4]. In the proposed method, the variable capacitors of a differential-type capacitive sensor form part of the integrator in a dual-slope ADC. The operation of the dualslope ADC is suitably modified such that its output after a successful conversion is proportional to the variations in the capacitances of the sensor. Since the proposed method is basically the well-known dual-slope integrating-type digital conversion technique, it possesses all the advantages of a conventional dual-slope ADC, i.e., stability, monotonicity, and immunity to noise and interference [5]. II. DUAL-SLOPE CAPACITANCE-TO-DIGITAL CONVERTER The circuit schematic of the proposed dual-slope capacitance-to-digital converter is shown in Fig. 1. The structure of the proposed scheme is similar to a conventional dualslope ADC, save for a couple of small but significant changes. The fixed capacitance of the opamp integrator OA) in a dual-slope ADC is now replaced with the capacitors C 1 and C 2 of a differential-type capacitive sensor, as shown in Fig. 1. Apart from the single-pole, double-throw switch S 1 to select a suitable reference voltage to the opamp integrator OA as +V R or V R, the proposed scheme uses a second single-pole, single-throw switch S 2. S 2 is positioned across capacitor C 2 and short circuits C 2 when activated. Both switches S 1 and S 2 are controlled by the signal SC coming from the timing, control, and measurement unit TCMU). The TCMU is similar to that of a dual-slope ADC and consists of an N-bit countertimer and control logic. The output of the integrator v oi is the input to a comparator OC), and the output of the comparator 0018-9456/$25.00 2008 IEEE

MOHAN et al.: DIGITAL CONVERTER FOR DIFFERENTIAL CAPACITIVE SENSORS 2577 Rearranging 1) results in T 2 = C 2 C 1 + C 2 ) T 1. 2) For a differential-type capacitive sensor with linear characteristics, C 1 and C 2 are given by C 1 = C o 1 ± Kx) and C 2 = C o 1 Kx) 3) Fig. 2. Outputs v oi and V oc. V oc is an input to the TCMU. If the output of the integrator v oi is positive 0), then the comparator output becomes one V oc =1); else, the comparator output remains at zero. A one-to-zero transition on the comparator output signals the zero crossing of v oi from a positive value. On the other hand, a zero-to-one transition of V oc signals the transition of v oi from a negative to a positive value through zero. A typical conversion starts with an autozero phase, wherein v oi is made zero. In the autozero phase, the TCMU is programmed to set switch S 1 in position 2 if v oi is negative V oc =0). The integrator output will then ramp up in the positive direction, as indicated by the bottom dotted line in Fig. 2. As soon as the integrator reaches zero, V oc toggles 0 to 1), signaling the TCMU that v oi is zero. If, initially, v oi is positive, then V oc =1. In this case, the logic of the TCMU is chosen to set switch S 1 to position 1. The integrator output will then ramp down, and V oc will toggle 1 to 0) when v oi reaches zero. Either a one-to-zero or a zero-to-one transition of V oc signals the end of an autozero phase to the TCMU, indicating that v oi =0. This autozero phase is shown in the form of dotted lines in Fig. 2. After an autozero phase, the TCMU performs two consecutive integrations with time intervals T 1 and T 2 to complete one conversion. Fig. 2 shows the output v oi of the integrator and output V oc of the comparator for this arrangement, wherein T 1 is set and T 2 is measured. As soon as the autozero phase ends, switch S 1 is set to position 2, and S 2 is closed. Switch S 1 connects the integrator to reference voltage V R, and switch S 2 short circuits capacitor C 2 ; hence, the output of the integrator ramps up with a slope of V R /RC 1. This condition is maintained for a fixed period first integration), for example, T 1 s= N 1 clock periods). At the end of T 1, the output of the integrator is V T1 = v oi t=t1 = V R RC 1 T 1. Capacitor C 1 is now charged to V T 1, whereas the voltage across C 2 is zero. At the end of T 1, S 1 is changed to position 1, and S 2 is opened. Reference voltage +V R is now connected to the input of the integrator, and its feedback path consists of the series combination of C 1 and C 2. The output of the integrator decreases with a slope V R C 1 + C 2 )/RC 1 C 2 and reaches zero after a period, for example, T 2 s, when V R T 1 = V RC 1 + C 2 ) T 2. 1) RC 1 RC 1 C 2 respectively, where C o is the nominal value of the capacitances C 1 and C 2 of the sensor, K is the transformation factor of the sensor, and x is the physical quantity being measured. Substituting the values of C 1 and C 2 from 3) into 2) results in ±Kx = C 1 C 2 C 1 + C 2 = T 1 2T 2 T 1. 4) It turns out that, if T 1 N 1 clock cycles) is chosen to be a round number, for example, 1000, and period T 2 is obtained by counting down at twice the clock frequency starting from 1000, the final value of the count will represent Kx. Equation 4) holds even when the sensor possesses an inverse characteristic, where C 1 = C o 1 Kx and C 2 = C o 1 ± Kx. 5) Thus, the scheme works without any modification for sensors with linear or inverse characteristics. As can be seen from 4), the output is independent of the absolute values of the components, which is one of the major advantages of using the dual-slope principle. The details of the simulation studies and experimentation on a prototype unit are dealt with in the succeeding sections, and the errors that may be introduced in the output due to nonideal characteristics of practical devices are quantified next. III. ERROR ANALYSIS Equation 4) has been derived, assuming that all the devices used in the circuit of Fig. 1 are ideal. However, in practice, the components used in the circuit will possess nonideal characteristics. The following nonidealities are considered, and their effects on the performance of the circuit are analyzed: 1) difference in the magnitudes of +V R and V R ; 2) parasitic/stray capacitances; 3) finite ON and OFF resistances of switches S 1 and S 2 ; 4) influence of noise and interference; 5) effect of the slew rate of the opamp and the offset voltages of the opamp and comparator. A. Error Due to Difference in the Magnitudes of +V R and V R In deriving 4), it is assumed that the magnitudes of +V R and V R are equal. However, in practice, they may differ. If

2578 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 11, NOVEMBER 2008 Fig. 3. Part of the circuit indicating all possible parasitic capacitances. the negative and positive reference voltages are V 1 and +V 2, respectively, and β = V 1 /V 2, then 1) becomes βv 2 T 1 = V 2C 1 + C 2 ) T 2 RC 1 RC 1 C 2 where T 2 is the new value of T 2 due to a difference in the magnitudes of the positive and negative reference voltages. Then T 2 = C 2 C 1 + C 2 ) βt 1. 6) The error ε T2 in T 2 obtained from 2) and 6) is ε T2 = T 2 T 2 100% = β 1)100%. T 2 The error ε Kx in the measurement of Kx due to the error in T 2 is ε Kx = 1 2T 2 β 1)100%. 7) Kx T 1 Hence, any mismatch difference) in the magnitudes of the reference voltages introduces an error that is quite significant at low values of Kx. Using precision dc voltages with parts-permillion-level stability and accuracy for the reference voltages, this error can be kept very small. B. Error Due to Stray Parasitic) Capacitances of the Sensor Fig. 3 shows the circuit schematic of the integrator incorporating all possible stray and parasitic capacitances. Capacitors C S1 and C S2 are stray capacitances that are in parallel with sensor capacitors C 1 and C 2, respectively. C G1, C G2, and C G3 are the parasitic capacitances between the sensor leads nodes) and ground. C G1 does not, in any way, influence the operation of the converter as its terminals are at virtual ground and ground potentials. Even in a practical case, the voltage across C G1 is very small few μv); hence, its effect on the output is negligible. C G2 is connected between the output of opamp OA and ground and thus becomes an additional load to opamp OA. Hence, capacitances C G1 and C G2 introduce negligible errors on the output compared to other capacitances. Fig. 4. Circuit after the Y Δ transformation. C S1 and C S2 are in parallel with C 1 and C 2, respectively; therefore, the effective capacitances are now C 1 =C 1 + C S1 ) and C 2 =C 2 + C S2 ). T 1 is a set value; hence, other than the clock frequency, no other parameter can influence T 1.To determine the effect of C G3 on T 2,aY Δ transformation is performed on the Y-configuration formed by C G3, C 1, and C 2. The resultant network is shown in Fig. 4. C B and C C are in parallel with C G1 and C G2, respectively. Hence, these capacitances have negligible effects on the performance of the circuit. The influence of capacitor C A =[C 1C 2/C 1 + C 2 + C G3 )] needs to be considered in analyzing the performance of the circuit in the presence of parasitic capacitances. Due to the presence of parasitic capacitances, 4) gets modified as V R RC 1 T 1 = V R C 1 + C 2 + C G3 ) RC 1 T C 2 8) 2 where T 2 is the new value of T 2 due to the presence of parasitic capacitances. Rearranging 8) and solving for Kx by using the values of C 1 and C 2, as given in 3), results in T1 2T 2 ) T 1 = ±Kx 1 ) 1+ C S1+C S2 +C G3 + C S1 C S2 + C G3 ). 9) 1+ C S1+C S2 +C G3 Comparison of 4) and 9) indicates that parasitic capacitances alter the sensitivity, as well as introduce an offset in the output, if the capacitive sensor possesses linear characteristics. If the sensor possesses an inverse relationship, as given in 5), stray capacitances, aside from altering the sensitivity of the circuit, also introduce nonlinearity in the output as T1 2T 2 ) T 1 = ±Kx 1 ) 1+1 K 2 x 2 ) CS1 +C S2 +C G3 C S1 C S2 + C G3 ). 10) 1+1 K 2 x 2 ) CS1 +C S2 +C G3

MOHAN et al.: DIGITAL CONVERTER FOR DIFFERENTIAL CAPACITIVE SENSORS 2579 However, the maximum value of Kx in a differential capacitive sensor possessing inverse relationship will be small 1); hence, the proposed scheme can still be employed, albeit with increased inaccuracy and nonlinearity at the output. C. Error Due to ON and OFF Resistances of Switches The ON and OFF resistances of switch S 1 r ON1 and r OFF1 simply alter input resistance R to R [R =Rr ON1 r OFF1 /R)+ r ON1 +r OFF1 )/r OFF1 r ON1 )]. Since R appears on both sides of 1), it does not affect the performance of the circuit. The ON resistance r ON2 of switch S 2 a few ohms) can introduce a small additional voltage =V R /R)r ON2 during T 1. Since R is chosen to be high a few megaohms), the effect of r ON2 on the output is minimal. On the other hand, the OFF resistance r OFF2 of S 2 will appear in parallel with C 2 during T 2 and introduce a time constant RC 2 in the discharging of voltage V T 1 acquired at the end of T 1 during T 2. The exponential discharging due to this time constant introduces nonlinearity. Hence, the OFF resistance of switch S 2 must be as high as possible. Any leakage resistances in the capacitive sensors also introduce nonlinearity. Since the values of sensor capacitances are normally small, the time constants are also small, resulting in acceptable levels of nonlinearity in the output. Moreover, as the cable resistances are normally of a few ohms, their effects on the performance of the circuit are negligible. Apart from the errors previously indicated, there would be an inevitable ±1 count error inherent to a digital counter, as well as the timing error introduced by the comparator. The error due to the ±1 count can be made negligible by choosing the number of clock cycles N 1, representing T 1, to be very large. The timing error in a comparator is usually of a few nanoseconds. In the dual-slope technique, T 1 is chosen to be of a few milliseconds; hence, the effect on the output due to the timing error in the comparator is minimal. D. Influence of Noise and Interference It is well known that the process of integration smooths out the effect of interference and noise [5]. If the first integration period T 1 is chosen to be large, any noise that may be present gets averaged out, and the effect of noise is reduced to zero. Similarly, by making the first integration period to be an integral multiple of the period of any interfering signal, the effect of the interfering signal on the output can be minimized [5]. However, a large value for T 1 results in a low conversion speed. Hence, the value of T 1 is so chosen to optimize the conflicting requirements of noise/interference immunity and conversion speed. E. Effect of Slew Rate of Opamp and Offset Voltages of Opamp and Comparator In a dual-slope technique, T 1 is chosen to be of the order of a few milliseconds to ensure immunity to noise and interference. Hence, the slew rate demand on opamp OA is expressed in Fig. 5. Results of simulation for a sensor possessing linear characteristics. voltage per millisecond. Since the slew rate of an opamp, in general, is in the range of voltage per microsecond, the slew rate of opamp OA will have negligible effects on the performance of the circuit. Any offset, if present in opamp OA, will appear on both sides of 1) and, hence, get nulled. Similarly, an offset present in comparator OC simply shifts the baseline in Fig. 2 either up or down, depending on the polarity of the offset voltage, but induces negligible effect on the output. On the other hand, if the comparator possesses hysteresis, an offset will be introduced at the output, which can be easily compensated. IV. SIMULATION STUDIES The proposed dual-slope direct capacitance-to-digital converter was simulated using the simulation software SABER. The devices chosen are OP07 for the opamp, LM311 for the comparator, and CD4053 for the switches with an ON resistance of 80 Ω and an OFF resistance of 40 MΩ). The control and logic were implemented using digital gates. Since the terminals of a capacitive sensor are always connected to a signal-conditioning circuit through shielded cables, the parasitic capacitances were chosen to be equal to that of a standard cable, namely 47 pf. Initially, the capacitances were assumed to vary in a linear fashion, as given in 3). C o was chosen as 400 pf, and C 1 and C 2 were varied in steps of 20 pf to obtain a variation in Kx from 0.5 to +0.5 in steps of 0.05. Fig. 5 illustrates the results of the simulation. As expected, the raw output possessed a gain error and an offset. Fig. 5 also portrays the output after affecting suitable gain and offset compensations on the raw output. The error in the output after effecting gain and offset compensations is also plotted in Fig. 5 and is found to be less than 0.9%. Next, the variations in the capacitances were chosen to represent the inverse characteristics, as given in 5). Here also, input Kx was varied over the range of 0.5 to +0.5 in steps of 0.05. For these values of Kx, the corresponding values of sensor capacitances C 1 and C 2 were computed, as per 5), and set as variable inputs in the simulation. The results of the simulation for this case are shown in Fig. 6. As expected, although the variations in the sensor capacitances were nonlinear, the output obtained was linear. As expected, the errors for this case are higher than the errors obtained for the linear case.

2580 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 11, NOVEMBER 2008 Fig. 6. Results of simulation for a sensor possessing inverse characteristics. Fig. 7. Results of prototype unit for a sensor possessing linear characteristics. V. E XPERIMENTAL RESULT To verify the practicality of the proposed dual-slope direct capacitance-to-digital converter, the circuit portrayed in Fig. 1 was breadboarded using off-the-shelf components. The choice of OP07 for the opamp was decided mainly because of its low offset voltage and low input bias current. CD4053 and LM311 ICs were used for the switches and the comparator, respectively. An LM385Z-1.2 with an opamp OP07) inverter circuit provided the positive and negative reference voltages. The gain of the inverter was trimmed to obtain a β of 1.00002. The control and timing circuit was built around an 89C51 microcontroller with necessary interface and display circuitry [6]. A suitable program was developed 1) to obtain the autozero phase, 2) to set T 1 1000 counts), 3) to measure T 2, and 4) to compute and display the value T 1 2T 2 /T 1 ).TosetT 1 and measure T 2, the internal counter of the 89C51 was utilized. The differential capacitive transducer was emulated using two precision variable standard capacitance boxes with an accuracy of ±0.05% manufactured by F&G Neptun, Germany. The resolution and the range of the variable capacitances were 10 pf and 100 1100 pf, respectively. The nominal value C o was chosen to be 400 pf. The capacitors were varied in the range of 200 600 pf in steps of 20 pf to simulate a variation in Kx in the range of 0.5 to +0.5 in steps of 0.05. The results obtained from the prototype unit are given in Fig. 7. As expected, the raw output from the counter had an offset of ten counts) and a gain error the ratio between Kx and 1 2T 2 /T 1 ) was found to be 0.9 instead of 1). Fig. 7 also indicates the output after affecting the offset and gain corrections on the raw output. The worst error is found to be less than ±0.2%. VI. CONCLUSION A digital converter that is suitable for differential-type capacitive sensors is presented. The method is theoretically analyzed, and possible errors due to nonideal components are quantified.

MOHAN et al.: DIGITAL CONVERTER FOR DIFFERENTIAL CAPACITIVE SENSORS 2581 The analysis indicates that the output is independent of the absolute values of the components employed and that the effect due to nonidealities is minimal. It turns out that possible errors that can affect the operation of the circuit are either in the form of a gain error and/or an offset, both of which can be easily compensated. A notable advantage of the proposed dual-slope direct capacitance-to-digital conversion scheme is that the scheme is suitable for differential capacitive sensors possessing linear as well as inverse characteristics without any modifications. Since the scheme is based on the dual-slope principle, a conversion speed of a few samples per second to a few kilosamples per second is achievable. It is possible to obtain higher conversion speeds, for example, a few hundred thousand samples per second, but at the cost of reduced performance, mainly due to interference and noise. Moreover, at such high conversion speeds, the slew rate, as well as the output impedance of the opamp used in the integrator, will introduce errors, downgrading the performance of the scheme. REFERENCES [1] K. Mochizuki, K. Watanabe, T. Masuda, and M. Katsura, A relaxationoscillator-based interface for high accuracy ratiometric signal processing of differential-capacitance transducer, IEEE Trans. Instrum. Meas., vol. 47, no. 1, pp. 11 15, Feb. 1998. [2] F. N. Toth and G. C. M. Meijer, A low-cost, smart capacitive position sensor, IEEE Trans. Instrum. Meas., vol. 41, no. 6, pp. 1041 1044, Dec. 1992. [3] E. W. Owen, An integrating analog-to-digital converter for differential transducers, IEEE Trans. Instrum. Meas., vol. IM-28, no. 3, pp. 216 220, Sep. 1979. [4] N. M. Mohan, A. R. Shet, and V. J. Kumar, Digital converter for differential capacitive sensors, in Proc. 23rd IEEE IMTC, Sorrento, Italy, Apr. 24 27, 2006, pp. 772 775. [5] E. R. Hnatek, A User s Handbook of A/D and D/A Converters. Melbourne, FL: Krieger, 1988. [6] K. J. Ayala, The 80C51 Micro-Controller: Architecture, Programming and Applications, 2nd ed. Mumbai, India: Penram, 1997. N. Madhu Mohan S 99) was born in Coimbatore, India, on March 21, 1970. He received the B.Tech. degree in electronics and communication engineering from the University of Calicut, Kerala, India, in 1991 and the M.S. By Research) degree from the Indian Institute of Technology Madras IIT Madras), Chennai, India, in 2003. He is currently working toward the Ph.D. degree in biomedical instrumentation with the Department of Electrical Engineering, IIT Madras. His research interests include measurements, biomedical instrumentation, and virtual instrumentation. Amol Ravikant Shet was born in Maharashtra, India, on March 2, 1980. He received the B.E. degree in engineering from Pune University, Pune, India, in 2001 and the M.S. By Research) degree from the Indian Institute of Technology Madras, Chennai, India, in 2005. He is currently with Texas Instruments, Bangalore, India, as a Test Engineer. His research interests include signal conditioning, control systems, highspeed ADC testing, and high-speed digital system design. S. Kedarnath received the B.Tech. degree from the National Institute of Technology, Warangal, India, in 1996. He received the M.S. By Research) degree from the Department of Electrical Engineering, Indian Institute of Technology IIT) Madras, Chennai, India in 2008. He is currently a Project Associate with the Department of Electrical Engineering, IIT Madras. His current research interests include power conversion, renewable energy, instrumentation, embedded systems, and power quality. V. Jagadeesh Kumar M 96) was born in Madras, India, on July 21, 1956. He received the B.E. degree in electronics and telecommunication engineering from the University of Madras, Chennai, India, in 1978 and the M.Tech. and Ph.D. degrees in electrical engineering from Indian Institute of Technology IIT) Madras, Chennai, in 1980 and 1986, respectively. He was a BOYSCAST Fellow at the King s College, London, U.K. during 1987 1988 and a DAAD Fellow at the Technical University of Braunschweig, Braunschweig, Germany, in 1997. In 1999, he was a Visiting Scientist with the Technical University of Aachen, Aachen, Germany. In the summer of 1999, he taught for a term at the Asian Institute of Technology, Bangkok, Thailand. He is currently a Professor with the Department of Electrical Engineering, IIT Madras. He has published more than 30 papers in international journals and presented more than 50 papers at various conferences. He is the holder of four patents. His teaching and research interests include measurements, instrumentation, and signal processing.