Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation

Similar documents
An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET

Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation

Lecture 04 Review of MOSFET

MOSFET: Introduction

Section 12: Intro to Devices

Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor. November 15, 2002

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

Semiconductor Physics fall 2012 problems

Classification of Solids

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS CAPACITOR AND MOSFET

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Semiconductor Physics Problems 2015

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Section 12: Intro to Devices

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

MOS Transistor I-V Characteristics and Parasitics

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices: MOS Transistors

Analytic Model for Photo-Response of p-channel MODFET S

Long Channel MOS Transistors

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

Lecture #27. The Short Channel Effect (SCE)

MOS Transistor Properties Review

EE105 - Fall 2006 Microelectronic Devices and Circuits

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Device Models (PN Diode, MOSFET )

A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model

Extensive reading materials on reserve, including

Device Models (PN Diode, MOSFET )

Appendix 1: List of symbols

EE105 - Fall 2005 Microelectronic Devices and Circuits

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.

6.012 Electronic Devices and Circuits

A Compact Analytical Modelling of the Electrical Characteristics of Submicron Channel MOSFETs

Reduction of Self-heating effect in LDMOS devices

ECEN 3320 Semiconductor Devices Final exam - Sunday December 17, 2000

Microelectronics Part 1: Main CMOS circuits design rules

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Typical example of the FET: MEtal Semiconductor FET (MESFET)

6.012 Electronic Devices and Circuits

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Chapter 4 Field-Effect Transistors

Supporting information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

Digital Electronics Part II - Circuits

Numerical and experimental characterization of 4H-silicon carbide lateral metal-oxide-semiconductor field-effect transistor

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

V t vs. N A at Various T ox

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

Lecture 12: MOSFET Devices

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

6.012 MICROELECTRONIC DEVICES AND CIRCUITS

Integrated Circuits & Systems

AS MOSFETS reach nanometer dimensions, power consumption

Graphene photodetectors with ultra-broadband and high responsivity at room temperature

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C.

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

Introduction and Background

Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007

Lecture 4: CMOS Transistor Theory

Lecture 12: MOS Capacitors, transistors. Context

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 340 Lecture 39 : MOS Capacitor II

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

MOSFET Physics: The Long Channel Approximation

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

ECE315 / ECE515 Lecture-2 Date:

The Devices. Devices

ECE 546 Lecture 10 MOS Transistors

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

EE5311- Digital IC Design

ECE-305: Fall 2017 MOS Capacitors and Transistors

EE 560 MOS TRANSISTOR THEORY

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Lecture 11: MOS Transistor

The Devices. Jan M. Rabaey

Nanoscale CMOS Design Issues

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

M R S Internet Journal of Nitride Semiconductor Research

Supplementary Figure 1. Supplementary Figure 1 Characterization of another locally gated PN junction based on boron

Lecture 5: CMOS Transistor Theory

Semiconductor Physics and Devices

Electrical Characteristics of MOS Devices

CMOS Inverter (static view)

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).

Choice of V t and Gate Doping Type

Practice 3: Semiconductors

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

ESE 372 / Spring 2013 / Lecture 5 Metal Oxide Semiconductor Field Effect Transistor

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

Transcription:

Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004, pp. 1283 1287 Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation I. C. Nam, H. T. Kim, H. S. Park, K. S. Kim, K. H. Kim, J. B. Choi, J. U. Lee, S. W. Kim, G. C. Kang, D. J. Kim, K. S. Min and D. M. Kim School of Electrical Engineering, Kookmin University, Seoul 136-702 (Received 7 July 2004) The substrate current is a good indicator for the hot-carrier and electrostatic discharge reliability of MOSFETs. However, the observation of the substrate current induced by generated holes from hot-carrier or impact ionization in dark condition does not objectively offer information on the interface states. By using a sub-bandgap optical source (E ph = 0.95 ev, P opt = 5 dbm, λ = 1310 nm), electrons on the traps below the Fermi level (E t < E F and E C E ph E t E C) can be excited to the conduction band and contribute to the substrate current. We modeled and characterized the substrate current under photonic characterization. We used the conventional substrate current model for universality of this analysis and found that it agreed well with experimental results obtained under sub-bandgap optical excitation. PACS numbers: 72.40.+w Keywords: Substrate current, Trap, Interface state, Optical, Photonic I. INTRODUCTION Recently, MOS (metal-oxide-semiconductor) device size has been extremely scaled down to deep submicron without a comparable reduction of supply voltage, which leads to higher electric field near the drain region to generate energetic hot carriers. As a result, the oxide trapping and interface state generation cause degradation of long-term performance and reliability of devices and their integrated circuits [1]. It is well known that the substrate current plays an important role in determining the robustness and hot-carrier reliability of MOSFETs (MOS field effect transistors). So, we investigated the substrate current with and without sub-bandgap (E ph < E g ) optical source which confines excess carriers only from traps (trap-to-band generation), excluding the band-to-band carrier generation. We expect that changes in the substrate current under sub-bandgap optical illumination can be used to characterize the density and distribution of the traps in the MOS systems. where I D is the drain current, l d is the characteristic length of the velocity saturation region, α n is the impact ionization rate, A and B are the ionization constants, and E(y) is the electric field in the channel of MOS- FETs under test. Based on the quasi-two-dimensional approximation, the channel electric field, E(y), is expressed as E(y) = E SAT cosh(y/l d ), where E SAT is the channel electric field at which the carriers reach velocity saturation. E SAT is known to be 4 10 4 V/cm for electrons. From Eq. (1), I SUB can be derived as [3] (1) I SUB = I D C(V D ηv Dsat ) ( ) B exp l d, (2) V D ηv Dsat l d = l o + l 1 (V DS V geff ) + l 2 (V DS V geff ) 2, (3) II. SUBSTRATE CURRENT MODEL It is well known that the substrate current (I SUB ) can be obtained from [2] ld ld ( I SUB = I D α n dy = A I D exp B ) dy, 0 E-mail: dmkim@kookmin.ac.kr; Tel: +82-2-910-4719; Fax: +82-2-910-4449 0 E(y) V geff = V gs V T o. (4) Characteristic model parameters including C, B, η, l o, l 1 and l 2 are empirical fitting parameters and can be extracted from the experimentally obtained substrate current I SUB. nmos test transistors were fabricated at ISRC (Interuniversity Semiconductor Research Center) by using a 1.5-µm CMOS process. The gate oxide was grown to a thickness of 25 nm. Boron ( 11 B +, 1.5 times 10 12 cm 2, -1283-

-1284- Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004 Fig. 1. Substrate current (I SUB) versus gate to source voltage (V GS) under dark condition in N-MOSFET 20/2 [µm/µm] ( : experimental substrate current; : calculated substrate current; Table: extracted parameters). Fig. 3. I SUB/I D versus V GS under dark condition ( : experimental I SUB/I D; : generalized I SUB/I D; : calculated I SUB/I D) where a fitting error occurs between calculated I SUB/I D and experimental I SUB/I D. Fig. 2. Substrate current (I SUB) versus gate to source voltage (V GS) under sub-bandgap optical illumination in N- MOSFET 20/2 [µm/µm] ( : experimental substrate current; : generalized substrate current; : calculated substrate current; Table: extracted parameters under dark condition). Fig. 4. I SUB/I D versus V GS under sub-bandgap optical illumination ( : experimental I SUB/I D; : generalized I SUB/I D; : calculated I SUB/I D) where a fitting error occurs between calculated I SUB/I D and experimental I SUB/I D. 40 kev) was implanted for the threshold voltage adjustment, and arsenic ( 75 As +, 5.0 10 15 cm 2, 80 kev) was implanted to form the highly doped n + source and drain. Based on Eq. (2), I SUB is calculated and the parameters are extracted under dark condition as shown in figure 1. The measured substrate current under sub-bandgap optical illumination appears as circles in figure 2. As a result of applying the extracted parameters under dark condition and the measured drain current under subbandgap optical illumination to Eq. (2), the calculated substrate current under sub-bandgap optical illumination appears as triangles in figure 2. Experimental data and calculated data show significant errors, as shown in figure 2. These errors are caused by the exclusion of the average drain-to-substrate leakage current component in the model. Therefore, we should consider the average drain-to-substrate leakage current to adopt a change in the bell-shaped substrate current Fig. 5. I SUB/I D versus V GS with and without subbandgap optical illumination ( : without sub-bandgap optical illumination; : with sub-bandgap optical illumination). under sub-bandgap optical illumination. The modeling result is shown as a solid line in figure 2, and the conventional model including the photonic effect

Modeling of the Substrate Current and Characterization of Traps I. C. Nam et al. -1285- in figure 6. III. DENSITY AND DISTRIBUTION OF THE INTERFACE TRAPS Fig. 6. Substrate current (I SUB) versus gate to source voltage (V GS) under sub-bandgap optical illumination in N- MOSFET 20/2 [µm/µm] ( : experimental substrate current; : calculated substrate current; : generalized substrate current; : ζ-adopted substrate current). can be rewritten as I SUB.gen = I SUB.conv + I AV G.leak, (5) where the average leakage current (I AV G.leak ) is the substrate current before V DS is increased up to the saturation voltage V Dsat. Based on Eq. (5), I SUB /I D is shown in figure 3 (without sub-bandgap optical illumination) and figure 4 (with sub-bandgap optical illumination). However, we note that the correct quantity is not fully considered in the substrate current with sub-bandgap optical illumination, as shown in figure 2. Therefore, we propose a model parameter ζ that is a physics-based empirical fitting parameter. The subbandgap optical energy contributes to an increase of the substrate current and this can be implemented as ηv Dsat under dark condition and ζηv Dsat when the optical effect is included. Based on the physical point of view in the definition of ζ, we may understand that the drain saturation voltage is reduced (ζv Dsat < V Dsat ) under sub-bandgap optical illumination. This also means that the change of the substrate current caused by the gate voltage is also changed by the sub-bandgap illumination, as shown in figure 5. This is because the optical source supplies extra energy to the carriers. The other observation in figure 5 is a change caused by the excitation and contribution of electrons residing on the trap levels below the Fermi level (E t < E F ). Electrons created by sub-bandgap optical illumination [4,5] cause additional impact ionization by higher electric field near the drain region. Thereby, electron-hole pairs are created, and these electron-hole pairs change the peak substrate current and the gate to source voltage at which the peak substrate current appears, as well as the shape of the substrate current on the gate voltage. This implies that the quantitative extraction of interface states is possible with substrate current monitoring under sub-bandgap photonic excitation. The optical substrate current that is denoted as ζ is shown Based on the increased substrate current caused by the excitation of the trap charges, we may regard the MOS- FET (metal-oxide-semiconductor field effect transistor) as a system responding to any given input signal. This system operates as an amplifier within the measurement range, and the multiplication factor (M) of this system depends on the gate and drain biases (V GS and V DS ). First, if we assume that the increase in the substrate current is proportional to the increase in the carrier concentration (any current density can be simply described as J = qnv), the substrate current (I SUB ) as a function of the gate bias (V GS ) under dark condition can be written as I SUB1 (V GS1, V DS1 ) n 1 (V GS1, V DS1 ) M(V GS1, V DS1 ), I SUB2 (V GS2, V DS1 ) n 2 (V GS2, V DS1 ) M(V GS2, V DS1 ), I SUBn (V GSn, V DS1 ) n n (V GSn, V DS1 ) M(V GSn, V DS1 ), (6) and the system response to the increased carriers ( n) can be described as I SUB (V GS, V DS ) (n(v GS, V DS ) + n(v GS, V DS )) M(V GS, V DS ). (7) Based on Eqs. (6) and (7), the substrate currents both with (I SUB.op ) and without (I SUB.dk ) sub-bandgap optical illumination can be modeled by I SUB.dk = I SUB.dk0 M dk (V GS, V DS ), (8) I SUB.op = I SUB.op0 M op (V GS, V DS ), (9) and I SUB.dk0 = A q n dk0 v dk, (10) I SUB.op0 = A q n op0 v op, (11) where A is the area, v dk and v op are the velocity of carriers, and n dk0 and n op0 are the channel carrier concentration under dark condition and sub-bandgap optical illumination, respectively. If the traps are only responsive to photons with subbandgap energy and directly result in the increase of the

-1286- Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004 under sub-bandgap optical illumination is written as n op0 = n dk0 + n. (12) The normalized multiplication factor M(V GS, V DS ) is derived from M dk (V GS, V DS ) = I SUB.dk (V GS, V DS )/I SUB.dk.MAX, (13) M op (V GS, V DS ) = I SUB.op (V GS, V DS )/I SUB.op.MAX, (14) Fig. 7. Difference between M op and M dk versus gate to source voltage (V GS) under sub-bandgap optical illumination in N-MOSFET 20/2 [µm/µm]. and the difference between M op and M dk is shown in figure 7. From Eq. (8) to Eq. (12), the ratio of the substrate currents (I SUB.op /I SUB.dk ) is written as I SUB.op = I SUB.op0 M op (V GS, V DS ) I SUB.dk I SUB.dk0 M dk (V GS, V DS ) = Aqv op n op0 M op (V GS, V DS ) Aqv dk n dk0 M dk (V GS, V DS ), (15) and, assuming v dk v op, the increase in the carrier density ( n) is modeled by Fig. 8. Photo-responsive energy band. E ph is the energy of a photon under sub-bandgap optical illumination, E is the photo-responsive range, qφ s is the potential at the surface, and qφ f is the potential at the bulk. The gray dot-lined box is the range in which the trap is generated (E t < E F and E C E ph E t E C). carrier concentration, the channel carrier concentration Fig. 9. Distribution of the interface trap density versus trap energy from the valence band. E C 1.12 ev; E i 0.56 ev. n = (I SUB.op/I SUB.dk ) n dk0 M dk (V GS, V DS ) n dk0 M op (V GS, V DS ) M op (V GS, V DS ) [cm 3 ]. (16) The sheet charge Q c is numerically solved by the quasi- 2D approximation [6], and n dk0 is expressed as n dk0 = Q c qt inv [cm 3 ], (17) where t inv is the effective channel thickness. If we assume that n is uniformly distributed within t inv, the twodimensional trap density N it [cm 2 ] is obtained from N it = n t inv [cm 2 ]. (18) Figure 8 shows the photo-responsive energy band. In the energy range ( E) in Figure 8, the trap can

Modeling of the Substrate Current and Characterization of Traps I. C. Nam et al. -1287- be excited with the help of the sub-bandgap optical illumination and the contribution of electrons residing on the trap levels below the Fermi level (E t < E F ) is decreased along the x-axis. The two-dimensional average trap density N it extracted from the substrate current change under sub-bandgap optical illumination is found to be 6.89 10 13 [cm 2 ] in the energy region (2qφ f < E t < E C ). By using Eq. (16), Eq. (17), and Eq. (18), D it is derived as D it = 1 q N it φ surf = 1 q and is shown in figure 9. N it V GS [cm 2 ev 1 ], (19) V GS φ surf ACKNOWLEDGMENTS This work was supported by 2004 Kookmin University Research Initiative Program, and simulation software was provided by IC Design Education Center (IDEC). REFERENCES IV. CONCLUSION In this paper, we investigated the modulation in the substrate current under dark condition and optical illumination with a sub-bandgap optical source (E ph = 0.95 ev, P opt = 5 dbm, λ = 1310 nm). The substrate current under sub-bandgap optical illumination is modeled with both the parameters extracted under dark condition and the model parameter ζ. The distribution of the interface trap density (D it ) [cm 2 ev 1 ] is extracted from the change of the substrate current which is due to optically generated electrons on the traps below the Fermi level (E t < E F and E C E ph E t E C ). [1] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K.W. Terrill, Solid-State Circuits 20, 295 (1985). [2] N. D. Arora and M. S. Sharma, IEEE Trans. Electron Dev. 38, 1392 (1991). [3] W. Li, J. S. Yuan, S. Chetlur, J. Zhou and A. S. Oates, Solid-State Electronics 44, 1985 (2000). [4] S. J. Song, H. T. Kim, S. S. Chi, M. S. Kim, W. S. Chang, S. D. Cho, H. T. Shin, T. E. Kim, H. J. Kang, D. J. Kim and D. M. Kim, J. Korean Phys. Soc. 41, 892 (2002). [5] M. S. Kim, H. T. Kim, S. S. Chi, T. E. Kim, H. T. Shin, K. W. Kang, H. S. Park, D. J. Kim, K. S. Min, D. W. Kang and D. M. Kim, J. Korean Phys. Soc. 43, 873 (2003). [6] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko and Y. C. Cheng, IEEE Trans. Electron Dev. 40, 86 (1993).