2M x 8 HIGH SPEED LOW POWER ASYRONOUS CMOS STATIC RAM Ex tended Tem per a ture TTS2MWV8 FEATURES High Speed access times 25, 35ns High-perfromace, low power CMOS process Multiple center power and ground pins for greater noise immunity Fully static operation: no clock or refresh required TTL compatible inputs and outputs VDD = 3.0V 10% Military and Extended Temperature Ranges Expansion to x16 stack for higher density DESCRIPTIONS The TTS2MWV8 is a high speed low power, 2M-word by 8-bit CMOS static RAM. This TTS2MWV is fab ri cated us ing high performance CMOS tech nol ogy. This highly re li able pro cess cou pled with in no va tive cir cuit de sign tech niques, yields higher performance and low power con sump tion de vices. When CE is HIGH (de se lected) the de vice as sumes a standby mode at which the power dis si pa tion can be re duced down with CMOS in put lev els. The TTS2MWV8 op er ates from a sin gle power sup ply and all in puts are TTL-com pat i ble. The TTS2MWV8 is available in 44 pin LCC and 52 pin Leaded and non-leaded stackable LCC (SLCC). Func tion Block Di a gram A15 A16 A17 A18 A20 A0 A1 A2 A3 A4 CE OE I/O7 I/O6 GND V DD I/O5 I/O4 I/O0 I/O1 V DD GND I/O2 I/O3 WE A14 A13 A12 A11 A10 A19 A9 A8 A7 A6 BOTTOM VIEW A5 Pin Con fig u ra tion Pin Con fig u ra tion 1
TT Semiconductor Pre lim i nary TTS2MWV8 TRUTH TABLE Mode WE CE OE I/O Op er a tion V DD Current Not Se lected (Power Down) X H X High-Z I SB1,I SB2 Out put Dis abled H L H High-Z I CC Read H L L D OUT I CC Write L L X D IN I CC ABSOLUTE MAXIMUM RATINGS 1 Sym bol Pa ram e ter Value Unit V TERM Ter mi nal Volt age with Re spect to GND -0.5 to V DD + 0.5 V V DD V DD Re lates to GND -0.3 to 4.0 V T STG Stor age Tem per a ture -65 to +220 C P T Power Dissiaption 1.0 W 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational specification is not implied. Exposure to absolute maximum rating conditions for extend periods may effect reliability. CAPACITAE 1,2 Sym bol Pa ram e ter Conditions Max Unit C IN In put Ca pac i tance V IN = 0 V 6 pf C I/O In put/out put Ca pac i tance V OUT = 0 V 8 pf 1. Test initial and after any design or process changes that may affect these parameters 2. Test Conditions: T A =25 C, f = 1 MHz, V DD = 3.3V OPERATING RANGE(V DD ) Range Am bi ent Temper a ture Mil i tary (M) -55C to +125C Ex tended Mil i tary (EM) -55C to +150C Extended Tem per a ture (ET) -55C to +175C 2
TTS2MWV8 Ex tended Tem per a ture TT Semiconductor DC ELECTRICAL CHARACTERISTICS V DD =3.3V 10% Sym bol Pa ram e ter Test Con di tions Min Max Unit V OH Out put HIGH Volt age V DD = Min, I OH = -1.0mA 1.8 - V V OL Out put LOW Volt age V DD = Min, I OL = 1.0mA - 0.4 V V IH In put HIGH Volt age 2.0 V DD +0.3 V V IL In put LOW Volt age -0.3-0.8 V I LI In put Leak age GND V IN V DD -20 20 A I LO Out put Leak age GND V OUT V DD, -20 20 A Out puts Dis abled POWER SUPPLY CHARACTERISTICS V DD =3.3V 10% -25-35 Sym bol Pa ram e ter Test Con di tions Min Max Min Max Unit I CC V DD Dy namic Op er at ing V DD = Max. Mil. 200 200 ma Sup ply Cur rent I OUT = 0 ma, f = f MAX EM. 250 250 ET 350 350 Typ 80 80 I CC1 Op er at ing V DD = Max. Mil. 150 150 ma Sup ply Cur rent I OUT = 0 ma, f = 0 EM 200 200 ET 330 330 I SB1 TTL Standby Cur rent V DD = Max. Mil. 150 150 ma (TTL In puts) V IN = V IH or V IL EM. 180 180 CS1 V IH,f = 0, CS2 = V IL ET 300 300 I SB2 CMOS Standby Cur rent V DD = Max. Mil. 150 150 ma (CMOS In puts) CS1 V DD - 0.2V EM. 180 180 CS2 0.2V ET. 300 300 Typ 8 8 1. At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at V DD = 3.0V, T A =25 C and not 100% tested. 3. ILI and ILO tested up to 150 C 3
TT Semiconductor Pre lim i nary TTS2MWV8 Pa ram e ter In put Pulse Level In put Fall and Rise Times AC TEST CONDITIONS Unit (3.3V 10%) 0.4V to VDD-0.3V 1.5ns In put and Out put Tim ing V DD /2 and Ref er ence Level (V REF ) Out put Load See Fig ures 1 and 2 READ CYCLE SWITCHING CHARACTERISTICS 1 25ns 35ns Sym bol Pa ram e ter Min Max Min Max Unit t RC Read Cy cle Time 25-35 - ns t AA Ad dress Ac cess Time - 25-35 ns t OHA Out put Hold Time 4-4 - ns t ACE CS1/CS2 Ac cess Time - 25-35 ns t DOE OE Ac cess Time - 12-15 ns 2 t HZOE OE to High-Z Ouput - 8-10 ns 2 t LZOE OE to Low-Z Out put 5-5 - ns 2 t HZCE CE to High-Z Out put 0 8 0 10 ns 2 t LZCE CE Low-Z Out put 10-10 - ns 1. Test Conditions assume signal transition times of 2ns or less, timing references levels of 1.25V. Input pulse levels of 0.4V to V DD -0.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500mV from steady state voltage. Not 100% tested. 4
TTS2MWV8 Ex tended Tem per a ture TT Semiconductor 5
TT Semiconductor Pre lim i nary TTS2MWV8 WRITE CYCLE SWITCHING CHARACTERISTICS 1,2 25ns 35ns Sym bol Pa ram e ter Min Max Min Max Unit t WC Write Cy cle Time 25-35 - ns t SCS1 / t SCS2 CS1/CS2 to Write End 18-25 - ns t AW Ad dress Setup Time to Write End 15-25 - ns t HA Ad dress Hold from Write End 0-0 - ns t SA Ac cess Setup Time 0-0 - ns t PWE WE Pulse Width 18-30 - ns t SD Data Write to End 12-15 - ns t HD Data Hold from Wrtite End 0-0 - ns t HZWE WE Low to High Z Out put - 12-20 ns t LZWE WE High to Low Z Out put 5-5 - ns 1. Test Conditions assume signal transition time of 2ns or less, timing references levels of 1.25V. Input pulse levels of 0.4V to VDD-0.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be invalid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3.Tested with the load in Figure 2. Transition is measured ±500mV from steady state voltage. Not 100% tested. 6
TTS2MWV8 Ex tended Tem per a ture TT Semiconductor 7
TT Semiconductor Pre lim i nary TTS2MWV8 DATA RETENTION SWITCHING CHARACTERISTICS Sym bol Pa ram e ter Test Con di tion Min Typ 1 Max Unit V DR V DD for Data Re ten tion See Data Re ten tion Waveform 1.6 3.6 V I DR Data Re ten tion Cur rent V CC = 1.6V, CE V CC - 0.2V - 3 60 ma t SDR Data Re ten tion Setup Time See Data Re ten tion Wave form 0 - ns t RDR Re cov ery Time See Data Re ten tion Wave form t RC - ns 1. Values are measured V DD = 3.0V, T A = 25 C Contact factory if elevated temperature is needed.. 8
TTS2MWV8 Ex tended Tem per a ture TT Semiconductor Fig ure 1: 44 Pin LCC Fig ure 2: 52Pin SLCC 9
TT Semiconductor Pre lim i nary TTS2MWV8 Fig ure 3: 52Pin "J Lead" SLCC Fig ure 3: 52 Pin Gullwing SLCC 10
TTS2MWV8 Ex tended Tem per a ture TT Semiconductor Fig ure 4: Ordering Information 10