Checking Signal Transition Graph Ipleentability by Sybolic BDD Traversal Alex Kondratyev The University of Aizu Aizu-Wakaatsu, 965 Japan Enric Pastor Universitat Politecnica de Catalunya 08071 - Barcelona, Spain Jordi Cortadella Universitat Politecnica de Catalunya 08071 - Barcelona, Spain Oriol Roig Universitat Politecnica de Catalunya 08071 - Barcelona, Spain Michael Kishinevsky y The University of Aizu Aizu-Wakaatsu, 965 Japan Alex Yakovlev z University of Newcastle upon Tyne, NE1 7RU England Abstract This paper denes conditions for a Signal Transition Graph to be ipleented by an asynchronous circuit A hierarchy of the ipleentability classes is presented Our ain concern is the ipleentability of the specication under the restricted input-output interface between the design and the environent, ie, when no additional interface signals are allowed to be added to the design We develop algoriths and present experiental results of using BDD-traversal for checking STG ipleentability These results deonstrate eciency of the sybolic approach and show a way of iproving existing tools for STG-based asynchronous circuit design 1 Introduction Synthesis fraeworks for asynchronous circuits based on STGs (see, eg, [2, 6]) involve ethods for STG analysis and verication The ain proble here is to check if a given STG is ipleentable by an asynchronous circuit Although the existing literature denes such conditions (naely, Consistency and Coplete State Coding [2, 6, 10]), they do not reect requireents to the interface between the circuit and its environent Another shortcoing of the existing analysis ethods is that they are based on explicit representation of the State GraphRecent developeents in using sybolic techniques for reachable state space traversal, based on Binary Decision Diagras(BDDs) [1, 9], can be applied to avoid state space explosion This work has been partially supported by CICYT TIC 91-1036, Dept d'ensenyaent de la Generalitat de Catalunya and ACiD-WG (Esprit 7225) y This work has been partly supported by The Danish Technical Research Council and by the UK SERC GR/J52327 z This work has been partly supported by the UK SERC GR/J52327 This paper tackles both these probles First, we dene STG ipleentability classes and the properties that ust be checked in order to ensure that a speed-independent circuit is derivable fro the STG (Sections 2 and 3) Secondly, we develop algoriths and present experiental results of using BDDtraversal approach for STG ipleentability verication (Sections 4 to 6) These results deonstrate eciency of the sybolic approach 2 STG ipleentability Let N = hp; T; F; 0 i be a Petri net (PN) [7], where P is the set of places, T is the set of transitions, F (P T ) [ (T P ) is the ow relation, and 0 is the initial arking A transition t 2 T is enabled at arking 1 if all its input places are arked An enabled transition t ay re, producing a new arking 2 with one less token in each input place and one ore token in each output place ( 1! 2 ) The sets of input and output places of transition t are denoted by t and t Siilar, p and p stand for the sets of input and output transitions of place p The set of all arkings reachable in N fro the initial arking 0 is called Reachability Set Its graphical representation is called Reachability Graph An exaple of PN is shown in Figure 1,a Signal Transition Graphs (STGs) are PNs whose transitions are interpreted as signal transitions A signal transition can be represented by a j + (or a j?) for the j-th transition of signal a fro 0 to 1 (or fro 1 to 0), while a j is a generic nae for either a rising or falling transition of a Denition 21 [2] An STG D is a triple hn; S A ; i, where N is a PN, S A is the set of signals that is a union of three non-intersecting subsets: S I ; S O and S H of input, output and internal (hidden) signals respectively, and : T! S A f1; 2; g f+;?g is the labelling function
p1 t1 p2 t2 p3 t3 p4 t4 p0 (a) p5 t5 p6 t6 p7 t7 p8 t8 r1+ a1+ (b) p0 r2+ a2+ a1- r1- r2- a2- Figure 1: A two-user utual exclusion eleent An STG exaple, which is the interpretation of PN fro Figure 1,a, is shown in Figure 1,b STGs are often shown in their shorthand for, where transitions are denoted by their labels (instead of bars) and places with only one input and output transition are oitted The behavior of an STG and a circuit can be copared on the basis of the languages they realize Denition 22 (Strong Equivalence) Circuit C with a set of signals A is strongly equivalent to STG D if: (1) there is one-to-one correspondence between signals A of C and S A of D, and (2) for each trace of signal transitions in C there is an equivalent trace of transitions in D and vice versa If we soehow anage to check that the STG can have a strongly equivalent circuit, then the logic equations for all gates of the circuit can be derived by the STG in a conventional way [2, 3, 10] This is why the STG that has a strongly equivalent ipleentation will be called gate ipleentable If there is no circuit that is strongly equivalent to the STG specication, it ight be that an equivalent circuit can be derived with soe additional signals Denition 23 (Projection) For a trace q over the set of signals S A the projection of q on the set of signals S B ; S B S A, is a sequence q # S B which is obtained fro q by deleting all transitions whose signals are not in S B A projection of a set of traces of D (L(D)) on the set of signals S B is the set of projections of all traces fro L(D) on S B (denoted by L(D) # S B ) Denition 24 (Trace equivalence) Two STGs D1 and D2 with signal sets S A1 and S A2 are trace equivalent by the set of signals S B, S B S A1 \ S A2, if L(D1) # S B L(D2) # S B Both STG and circuit behavior can be characterized by their trace sets Thus, one can copare in this way two dierent STGs, or two circuits, or an STG and a circuit Denition 24 restricts the behavior of observable signals (set S B ); no change in their ordering is allowed For specications (circuits) with external inputs and outputs an equivalence that preserves the input-output (I/O) interface is needed Denition 25 (I/O equivalence) Two STGs D1 and D2 with sets of signals S A1 and S A2 are I/O equivalent by the set of signals S B, S B S A1 \ S A2, if (1) they are trace equivalent by S B and (2) for the input and output signals of D1 and D2: S I1 = S I2 S B and S O1 = S O2 S B Trace equivalence and I/O equivalence address different design tasks and conditions If the task is to ipleent a odule, then typically the I/O interface is xed for the odule and it is necessary to use the I/O equivalence between the ipleentation and the original specication However, it is often up to the designer to decide how to decopose the odule into saller blocks and what kind of interface to choose for these blocks For the odule decoposition, only trace equivalence ay need to be ensured In this paper we are priarily interested in the conditions of ipleentability when it is not allowed to change the interface We have therefore distinguished the following (in the descending order of hierarchy) levels in the STG ipleentability: Denition 26 An STG D is called: (1) SIipleentable if there is a logic circuit C trace equivalent to D; (2) Input/Output SI-ipleentable (we will siply denote it I/O-ipleentable) if there is a logic circuit C I/O equivalent to D; (3) Gateipleentable if there is a logic circuit C strongly equivalent to D 3 Properties of STGs Our check of STG ipleentability will be based on the BDD-based sybolic traversal of the reachable set of states [1, 9] This helps to avoid or to itigate state explosion SG is a directed graph whose vertices correspond to the arkings of the Reachability Graph An SG vertex is labeled with a boolean vector s = hs 1 ; ; s n i, representing the value of the STG signals (n is the nuber of signals in the STG) This vector is called a state Two states s 1 and s 2 corresponding to arkings 1 and 2 are connected with an edge in the SG if 2 is reachable fro 1 by the ring of soe event a a of the STG i (s 1! s 2 ) This transition a i is called enabled in state s 1 Signal a is called enabled in state s if soe transition a i is enabled in s, otherwise a is called stable or disabled In general, several states in the SG ay correspond to one arking Therefore, rst the full state
{p0,p1,p5} {0000} t1 t5 r1+ r2+ {p0,p2,p5} {p0,p1,p6} {1000} {0010} t5 t1 t6 {p0,p2,p6} {p1,p7} r2+ r1+ a2+ {1010} {0011} (a) (b) State: <r1,a1,r2,a2> {p0,p1,p5},{0000} t1 t5 {p0,p2,p5},{1000} {p0,p1,p6},{0010} t5 t1 t6 {p0,p2,p6},{1010} {p1,p7},{0011} (c) Figure 2: State odels graph [11] is build Each vertex in such a graph is labelled by a pair (arking, state) The SG is then obtained by retaining only the state coponent in each vertex label Figure 2,a-c illustrates the three types of state odels: the reachability graph, the state graph and the full state graph for the utual exclusion eleent 31 Boundedness and consistency The behavior of the circuit ust be nite This is guaranteed by boundedness of the underlying Petri net A PN (STG) is called k-bounded if for every reachable arking the nuber of tokens in any place is not greater than k A PN (STG) is called bounded if there is such a nite k for which it is k-bounded, and if k = 1, then the PN (STG) is called safe The STG shown in Figure 1,b is safe Not every STG can be associated with a process of switching the circuit gates Let us assue, for exaple, that the following sequence is feasible in an STG: b 1 +; a+; b 2 +; After ring b 1 + signal b ust be at logical 1, and no correct interpretation can be suggested to the following transition b 2 + Such incorrectness can be foralized in the SG ters by state assignent consistency Denition 31 An SG has a consistent state assignent (we call such an SG consistent) i for each pair of states s 1 and s 2 connected with the edge (s 1! s 2 ) the following conditions are et: (1) if the edge is labeled by a+ transition, then signal a is equal to 0 in s 1 and to 1 in s 2 ; (2) if the edge is labeled by a? transition, then signal a is equal to 1 in s 1 and to 0 in s 2 ; (3) in all other cases the value of signal a in s 1 and s 2 is the sae An STG D is SI-ipleentable only if it is bounded and its SG is consistent[2, 5] The specic feature of speed-independent ipleentation is captured by persistency 32 Persistency Persistency eans that if a circuit signal is enabled it has to re independently fro the ring of other signals However, one should distinguish between input and non-input signals For inputs, which are controlled by the environent, it is possible to have a non-deterinistic choice, which is represented in STG and SG odels by conicts, ie, disabling of one input signal by another input signal Such conicts are always interpreted as choice and therefore do not lead to hazardous behavior For non-input signals, which are produced by circuit gates, signal transition disabling ay lead to a hazardous spike at the output of the gate, aking the circuit behavior dependent on the gate delays In the case phrased as \input is disabled by the output", we assue that these two signals are controlled independently, one by the environent and the other by the circuit If the environent is ready to change the input while the circuit is ready to change the output of a gate, then these two processes, under a speed-independent interaction, cannot inuence each other Therefore this is also a potential source of hazards and delay-dependence Denition 32 SG G is persistent if: (1) any noninput signal cannot be disabled by another signal 1 and (2) any input signal cannot be disabled by a non-input signal The following proposition (siilar to the one proved in [4]) shows that persistency is a necessary condition for the SI-ipleentability of STGs Proposition 31 An STG is I/O-ipleentable only if the corresponding SG is persistent Let us rene the potential sources of persistency violation Denition 33 (1) Transition t i is non-persistent in a PN N if t i enabled in soe reachable arking becoes disabled after the ring of another transition t j enabled in Non-persistency of t i with respect to t j is also called a direct conict between t i and t j (2) Signal a is non-persistent in an STG D if a is enabled in soe reachable state s of the corresponding SG and it becoes disabled after the ring of another signal b also enabled in s Signal persistency and transition persistency are closely related Clearly, the only source of nonpersistency of a signal a is the non-persistency of soe transition labelled with a i Yet not any nonpersistency of a i leads to the violation of persistency by signal a In Figure 3,a transitions labelled with a 1 + 1 To deal with non-deterinistic circuits (like arbiters) we can soften the requireent and allow the disabling of non-input signals in arbitration points
and b 2 + are both non-persistent However, signals a and b are persistent in the corresponding SG in Figure 3,c Although the ring of, eg, a 1 + disables b 2 + it also enables transition b 1 + So, both before and after the ring of a 1 +, signal b reains enabled By the trace equivalence (Denition 24) such a behavior of signals a and b is equivalent to the concurrent ring of a+ and b+[6] Therefore, both STG D1 and D2 have the sae SG (Figure 3,c) One can conclude that for signal b the conict of the transition b 2 + is "fake" Fake conicts are discussed further in Section 35 D1: a 1+ p1 b + 2 b + 1 a + 2 c+ p2 (a) D2: a+ b+ c+ (b) abc 0*0*0 a+ b+ 10*0 0*10 b+ a+ 110* c+ Figure 3: Transition and signal non-persistency 33 Coplete state coding SG descriptions are convenient for the derivation of the logic functions of signals Unfortunately, this procedure is not always iediately possible even for nite, consistent and persistent SGs The proble is with the state encoding, which ay soeties dene the on- and o-sets of the logic functions [2, 3, 6] not uniquely Denition 34 A state graph is said to satisfy the Coplete State Coding requireent if and only if (1) each state has a unique binary code, or (2) for pairs of states that have identical binary codes, the set of enabled non-input signals is identical The CSC requireent is the necessary condition for the gate ipleentabilty It is also the sucient condition for the ipleentation on coplex gates[2] Given an STG specication that does not obey the CSC requireent, the following question arises: Is it possible to equivalently transfor this specication to another STG for which the CSC requireent is et and therefore it is gate ipleentable? For the SIipleentability when it is allowed to change the interface of the design the answer to the question is positive, and any of the known ethods can be eployed to insert additional signals into the STG [3, 10, 6] However, for I/O-ipleentability with the xed interface of the design CSC-violations can be classi- ed into reducible and irreducible Reducible CSCviolations can be solved by adding new non-input signals, irreducible violations require changes in the interface between the circuit and the environent (c) 34 CSC reducibility With every sequence q feasible in SG we will associate the unbalanced set of q that contains all the signals for which the nubers of their + and? transitions in q are not equal Denition 35 (1) An SG is called deterinistic with respect to signal transition a if for any state s there is at ost one state s1 such that s! a s1 The SG is deterinistic if it is deterinistic for all signal transitions (2) An SG is called coutative with respect to signal transitions a and b if for any states s; s1; s2; s3; s4 such that s! a s1! b s3 and s! b s2! a s4, s3 is equal to s4 The SG is coutative if it is coutative for all pairs of signal transitions (3) An SG has utually copleentary input sequences if there is a state s which gives rise to two distinct nite sequences of input transitions which have the sae unbalanced sets and which lead to two dierent states It ight be shown that a consistent and persistent SG of a bounded STG is CSC-reducible if it is deterinistic, coutative and free fro utually copleentary input sequences The following proposition shows the list of properties necessary and sucient for the I/O-ipleentability of STGs Proposition 32 An STG is I/O-ipleentable i it is bounded and its SG is consistent, persistent and CSC-reducible Obviously, if an STG has a SG that obeys CSC requireent, then the STG is gate-ipleentable 35 Fake conicts In this section we deonstrate another property of STG, of a well-foredness type, which can be helpful in two ways Firstly, it will provide a useful echanis for perforing ecient verication of coutativity and persistency within the BDD-fraework, where the SG is not available in its explicit for Secondly, it can assist the designer in optiising the initial STG description Denition 36 (Fake conict) [5] A direct conict between two signal transitions a i and b j is called fake if the ring of one of the does not disable the signal of the other Figure 4 shows two types of fake conicts: asyetric and syetric Obviously, if the STG has a coutative SG, then each syetric fake con- ict ust correspond to the coutative subgraphs of the STG and the SG, and can therefore be always transfored to the equivalent parallel subgraphs of the
*ai 1 *bk 3 a) *bj 2 4 *ar *ai 1 *bk *bj 2 3 4 b) Figure 4: Fake conicts *ar STG and SG as exeplied in Figure 3 Asyetric fake conicts involving at least one non-input signal always contradict one of the persistency conditions in Denition 32 and therefore lead to the violations of SI-ipleentability Asyetric fake conicts between two input signals are not dangerous, since they are interpreted as a choice between two alternative traces An STG is called fake-free STG if there are no syetric fake conicts and there are no asyetric fake conicts involving a non-input signal The following properties [5] illustrate use of fake conicts: (1) If an STG has the persistent and coutative SG, then it can always be transfored to the equivalent fake-free STG (2) A fake-free STG is coutative (3) A fakefree STG has a persistent SG i all transitions labelled with non-input signals are persistent Therefore, one can either exclude fake conicts by an equivalent transforation of the STG or the STG (and its SG) is not persistent and hence not I/Oipleentable Therefore, in the analysis of ipleentability we always reject STG specications with syetric fake conicts and non-input asyetric fake conicts Fake conicts can be analyzed by the structure of the STG and that is uch sipler than the check for coutativity 4 Modeling Petri nets and STGs with logic functions Given an n-variable logic function f : B n! B, the functions f xi = f(x 1 ; ; x i?1 ; 1; x i+1 ; ; x n ) and f x 0 i = f(x 1 ; ; x i?1 ; 0; x i+1 ; ; x n ) are called the positive and negative cofactors of f with respect to x i The denition of cofactor can be extended to cubes (sets of literals) The existential abstraction of f with respect to x i is dened as: 9 xi f = f xi + f x 0 i Let N = hp; T; F; 0 i be a safe Petri net and M P the set of all arkings of N (n = jp j; jm P j = 2 n ) A arking can be represented by a boolean vector = (p 1 ; ; p n ), where p i = 1 (p i = 0) denotes that p i is arked (not arked) 2 Each set of 2 Unsafe k-bounded places can be represented by several boolean variables [9] arkings M 2 2 M P has a characteristic logic function M : B n! B, that equals 1 for those vertices that correspond to arkings in M For exaple, given the Petri net depicted in Figure 1,a, the characteristic function of the set of arkings M = f(0,1,0,0,1,0,0,0,0), (0,1,1,0,1,0,0,0,0), (1,1,0,0,1,0,0,0,0), (1,1,1,0,1,0,0,0,0), (1,1,1,1,1,0,0,0,0) g is calculated as the disjunction of boolean vectors 2 M The resulting function is M = p 1 p 4 p 0 5 p0 6 p0 7 p0 8(p 0 p 2 + p 0 3) The transition function of a Petri net is a function N : 2 M P T?! 2 M P ; that transfors, for each transition, a set of arkings M 1 into a new set of arkings M 2 as follows: M 2 = N (M 1 ; t) = f 2 2 t M P : 9 1 2 M 1 ; 1! 2 g Coputation of the transition function can be eciently ipleented by using the topological inforation of the PN Let us present the characteristic function of soe iportant sets related to a transition ^ t 2 T : E(t) = ^ p i (t enabled), p i 2 t ASM(t) = ^ p i (all successors arked), p i 2t NPM(t) = p 0 ^ i (no predecessor arked), p i 2 t NSM(t) = (no successor arked) p i 2t p 0 i Given these characteristic functions, the transition function can be coputed as follows: N (M; t) = (M E(t) NPM(t)) NSM(t) ASM(t): Assue that in the exaple of Figure 1,we calculate M 1 = N (M; t 1 ) given the set M = p 0 p 1 p 0 2 (p 5p 0 + 6 p 0 5 p 6) + p 0 1 p 3p 5 p 0 6 p0 7 : First, M E(t 1 (cofactor of M ) with respect to E(t 1 ) = p 1 ) selects those arkings in which t 1 is enabled and reoves its predecessor places fro the characteristic function (M E(t 1 = ) p 0 p 0 2(p 5 p 0 6+p 0 5 p 6)) Then the product with NPM(t 1 ) = p 0 1 eliinates the tokens fro the predecessor places (M E(t 1 ) NPM(t 1) = p 0 p 0 1 p0 2 (p 5p 0 + 6 p0 5 p 6)) Next, the cofactor with respect to NSM(t 1 ) = p 0 2 reoves all the successor places, obtaining (M E(t 1 ) NPM(t 1 )) = NSM(t1 ) p 0p 0 1 (p 5p 0 + 6 p0 5 p 6) Finally, the product with ASM(t 1 ) = p 2 adds a token in all the successor places of t 1 (M 1 = p 0 p 0 1 p 2(p 5 p 0 6 + p 0 5 p 6)) Let D = hn; S A ; i be an STG with N as underlying Petri net Let G be the SG corresponding to the STG D, and C the set of labels (state codes) of the states of G Since there is a correspondence between arkings of N and states of G, we represent the full state of the STG by the vector y = (; s), where is a arking of N and s the state code of the corresponding state in G, respectively The transition function can now be extended for STGs as a function D : 2 (M P C) T?! 2 (M P C)
For a set of full states M F, D is dened as follows: D (M F ; t) = (N (M F ; t)) a 0 a if (t) = a i + ( N (M F ; t)) a a 0 if (t) = a i? 5 Verication of ipleentability conditions STG ipleentability properties can be veried by calculating all reachable arkings (states) of the STG Given the initial arking 0 of N and the initial values of the signals s 0, the set of states of an STG can be calculated by using sybolic traversal techniques, siilar to those used for the verication of nite state achines Figure 5 describes an algorith for sybolic traversal It starts fro an initial full state ( 0 ; s 0 ) For each outerost iteration, all transitions of the Petri net are visited and red fro all the new states found so far The algorith halts when a xed point is reached (no new states are generated) traverse STG (D) f Reached = Fro = f(0; s0)g; repeat for each t 2 T do To = D ( Fro; t); Fro = Fro [ To; endfor New = Fro? Reached; Reached = Reached [ New; Fro = New; until ( New = ;); return Reached; /* The set of reachable states of D */ g Figure 5: Algorith for sybolic traversal of an STG 51 Boundedness and consistency The check that an STG (PN) is k-bounded or safe can be done within the BDD-fraework by eans of the technique described in [9] Verifying that the STG is consistent can be done during the traversal, by checking the consistency of the new generated states We rst dene the following characteristic function: E(a) = _ t:(t)=a E(t) (a is enabled) The characteristic function of the states with inconsistent assignent is derived according to Denition 31: Inconsistent(a+) = E(a+) a(a + enabled and a = 1) Inconsistent(a?) = E(a?) a 0 (a? enabled and a = 0) Inconsistent(a) = Inconsistent(a+) + Inconsistent(a?) _ Inconsistent(D) = Inconsistent(a) a2s A Let us call R(D) the set of reachable states (arkings and binary codes) of the STG D D is inconsistent if R(D)\ Inconsistent(D) 6= ; An additional proble ay appear in case the state assignent of the initial arking is unknown A siple solution for that is to initially assign a \don't care" value for all signals (or equivalently, to not encode signals in the initial arking) As soon as a arking with soe a i + enabled is generated, all reachable arkings obtained so far are encoded with a = 0 (siilarly for a i?) 52 Persistency A transition can only be non-persistent if soe of its input places is a conict place (ore than one predecessor) For soe classes of Petri nets persistency is guaranteed by the structure of the net, eg arked graphs are always persistent since all places have only one successor transition [7] An algorith to check transition persistency is shown in Figure 6(a) Only pairs (t i ; t j ) of transitions with soe coon predecessor place are analyzed Let R(N) be the set of reachable arkings of N The set of arkings with t i enabled are calculated Next, the set of arkings reachable in one step by ring soe transition t j 6= t i are obtained If t i is not enabled in any of those arkings, then t i is not persistent A siilar algorith to check the signal persistency is given in Fig 6(b) 53 Coplete State Coding The CSC requireent can be checked for each noninput signal by dening the following characteristic functions: ER(a+) = 9 P (R(D) E(a+)) ER(a?) = 9 P (R(D) E(a?)) QR(a+) = 9 P (R(D) a? E(a?)) QR(a?) = 9 P? R(D) a 0? E(a+) ER(a) is the set of binary codes that correspond to states in which soe a i is enabled (a set of excitation regions) It is obtained by abstracting the places (9 P ) fro the states of the excitation region QR(a+) (a set of quiescent regions) is the set of binary codes that correspond to states in which a = 1 but a? is not enabled (siilarly for QR(a?)) The CSC requireent for non-input signal a can now be checked as follows [8]: CSC(a) = (ER(a+)\QR(a?) = ;)^(ER(a?)\QR(a+) = ;)
transition persistency (N) f g for each p 2 P, jp j > 1 do for each t i 2 p do Enabled = R(N) E(t i ); for each t j 2 p ; t i 6= t j do if ( N ( Enabled; t j ) \ E(t i ) 0 6= ;) error (\t i disabled by t j "); (a) signal persistency (N) f g for each p 2 P, jp j > 1 do for each t i 2 p do Enabled = R(N) E(t i ); for each t j 2 p ; t i 6= t j do /* Let (t i ) = a i and (t j ) = b j */ if ( N ( Enabled; t j ) \ E(a) 0 6= ;) error (\a disabled by b"); (b) Figure 6: Algoriths to verify persistency CSC(D) = ^ a2s O [S H CSC(a) The CSC-irreducibility check can draw upon the results of the above CSC analysis To check the existence of utually copleentary input sequences, we can proceed for each non-input in the following way: Let CONT (a) be the set of contradictory states for noninput a, dened by CONT (a) = (ER(a+) \ QR(a?)) [ (ER(a?) \ QR(a+)) We rst take all the states in (QR(a+)[QR(a?))\CONT (a), and then traverse the net backward with \frozen" non-inputs (ie, ring only input signals) until the xed point is reached Then the forward traversal with frozen non-input signals is perfored fro the set of states obtained by the backward traversal As a result, the set ReachedF rozen is obtained If ReachedF rozen \ (ER(a?) [ ER(a+)) \ CONT (a) 6= ;, then there is a CSC proble for a with a utually copleentary input sequences The set of states violating nondeterinis for signal change a is trivially dened by: St i ;t j 2T; (t i )=(t E(t j )=a i) \ E(t j ) Instead of the relatively coplex coutativity check, which ust be perfored individually for each state with ore than one enabled signal, we check the freedo fro the fake conicts 54 Fake conicts One can siplify the check of both SG coutativity (another case for CSC-irreducibility) and persistency by checking for fake-freedo and transition persistency An outline of the procedure which deterines if there is any fake conict in an STG D (N is the underlying PN) with respect to a signal transition t i is as follows: We start with the set of reachable states in which t i is enabled: Enabled = R(N) \ E(t i ) Then for each t j ; t k 2 T such that 9p 2 P : t i ; t j 2 p ; t i 6= t j ; t k 6= t i ; t k 6= t j ; (t k ) = (t i ) = a, we check if the set of states reached fro Enabled by ring t j contains at least one such state that enables t k, which is labelled with a as t i (forally, if N (Enabled; t j ) \ E(t k ) 6= ;) If all these checks return false, the STG is fake-free with respect to t i The check for syetric and asyetric fake conicts is a siple odication of this basic technique 6 Experiental results Several exaples have been used to evaluate the ef- ciency of the proposed algoriths Most exaples are scalable, in such a way that the nuber of states of the syste can be exponentially increased by iteratively repeating a basic pattern Despite the regularity of these scalable exaples, we have found that BDDs ay have an exponential size if appropriate heuristics for variable ordering are not used Table 1 shows the obtained results CPU tie for each algorith is presented First, STG traversal and consistent state assignent are executed siultaneously (T+C) Next, non-input persistence (NI-p) and coutativity (Co) are veried by using the set of reachable states Finally, CSC is veried Since the aster-read and Muller's pipeline exaples are arked graphs (no conict places), the CPU tie to check persistency and coutativity is negligible The BDD sizes reported in Table 1 correspond to the size of the Reached set in the traversal algorith The nuber of variables of the BDD is the nuber of places plus the nuber of signals The results show how STGs with a high degree of parallelis and an extreely vast state space can be veried in oderate CPU ties 7 Conclusion We have presented foral conditions for an STG to be ipleented by a speed-independent circuit under three dierent notions of behavioral equivalence The ost practical one is Input-Output ipleentability, which takes into account specic requireents about the interface between the circuit and its environent This is reected in the notions of persistency and CSC-reducibility Consistency is also dened in a ore general for than before { for a full state graph, thus covering the case when one arking of an STG ay correspond to several dierent states We have developed and ipleented algoriths for checking these properties using sybolic rather than tradi-
# of # of # of BDD size CPU (seconds) Exaple n places signals states peak nal T+C NI-p CSC Total aster-read - 36 13 8932 437 225 1 0 0 1 n dining 10 90 30 6:0 10 7 2134 913 34 3 14 51 philosophers 20 180 60 3:7 10 15 8557 2019 765 142 18 927 30 270 90 2:2 10 23 28002 3381 3296 551 45 3897 n-stage 30 120 30 6:0 10 7 7897 4784 132 0 38 170 Muller's 45 180 45 6:9 10 11 23590 10634 740 0 120 860 pipeline 60 240 60 8:4 10 15 53446 18788 3210 0 315 3525 n-user 20 81 40 2:2 10 7 1688 1688 9 2 2 13 DME 40 161 80 4:5 10 13 6568 6568 82 17 16 117 arbiter 60 241 120 7:0 10 19 14648 14648 286 56 56 403 Table 1: Experiental results tional explicit state-enueration techniques Such an approach generates and explores the set of reachable states in the for of their boolean characteristic functions represented by BDDs Experiental results show that this ethod greatly reduces tie spent on STG verication, thus iproving the overall perforance of the STG-based synthesis process Acknowledgeents We are grateful to Alexander Taubin for any useful discussions References [1] Randal Bryant Sybolic boolean anipulation with ordered binary-decision diagras ACM Coputing Surveys, 24(3):293{318, Septeber 1992 [2] T-A Chu Synthesis of Self-tied VLSI Circuits fro Graph-theoretic Specications PhD thesis, MIT, June 1987 [3] M Kishinevsky, A Kondratyev, A Taubin, and V Varshavsky Concurrent Hardware: The Theory and Practice of Self-Tied Design John Wiley and Sons, London, 1993 [4] M Kishinevsky and J Staunstrup Checking speedindependence of high-level designs In International Syposiu on Advanced Research in Asynchronous Circuits and Systes, pages 44 { 53, Salt Lake City, Utah, USA, Noveber 1994 [5] A Kondratyev and A Taubin On verication of the speed-independent circuits by STG unfoldings In International Syposiu on Advanced Research in Asynchronous Circuits and Systes, pages 64 { 75, Salt Lake City, Utah, USA, Noveber 1994 [6] L Lavagno and A Sangiovanni-Vincentelli Algoriths for synthesis and testing of asynchronous circuits Kluwer Acadeic Publishers, 1993 [7] T Murata Petri nets: Properties, analysis and applications Proceedings of IEEE, 77(4):541{580, April 1989 [8] E Pastor and J Cortadella Polynoial algoriths for the synthesis of hazard-free circuits fro signal transition graphs In Proceedings of the International Conference on Coputer-Aided Design, pages 250{ 254, Noveber 1993 [9] E Pastor, O Roig, J Cortadella, and R Badia Petri net analysis using boolean anipulation In 15th International Conference on Application and Theory of Petri Nets, pages 416 { 435, Zaragoza, Spain, June 1994 [10] P Vanbekbergen, F Catthoor, G Goossens, and H De Man Optiized synthesis of asynchronous control circuits fro graph-theoretic specications IEEE Transactions on Coputer-Aided Design, pages 1426{ 1438, Noveber 1992 [11] A V Yakovlev Synthesis of hazard-free asynchronous circuits fro generalised Signal-Transition Graphs Technical Report Series 377, University of Newcastle upon Tyne, Coputing Science, April 1992