Low Latency Architectures of a Comparator for Binary Signed Digits in a 28-nm CMOS Technology

Similar documents
CS 140 Lecture 14 Standard Combinational Modules

Carry Look Ahead Adders

Lecture 8: Sequential Multipliers

EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1

UNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018

Chapter 5 Arithmetic Circuits

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

Combinational Logic Design Arithmetic Functions and Circuits

What s the Deal? MULTIPLICATION. Time to multiply

An Approximate Parallel Multiplier with Deterministic Errors for Ultra-High Speed Integrated Optical Circuits

ELCT201: DIGITAL LOGIC DESIGN

VLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20

Combinational Logic. By : Ali Mustafa

Hardware Design I Chap. 4 Representative combinational logic

Adders, subtractors comparators, multipliers and other ALU elements

ISSN (PRINT): , (ONLINE): , VOLUME-4, ISSUE-10,

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

Binary addition by hand. Adding two bits

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

ELEC516 Digital VLSI System Design and Design Automation (spring, 2010) Assignment 4 Reference solution

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Tree and Array Multipliers Ivor Page 1

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Floating Point Representation and Digital Logic. Lecture 11 CS301

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation

Area-Time Optimal Adder with Relative Placement Generator

Dual-Field Arithmetic Unit for GF(p) and GF(2 m ) *

PERFORMANCE IMPROVEMENT OF REVERSIBLE LOGIC ADDER

CSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

CprE 281: Digital Logic

Number representation

GALOP : A Generalized VLSI Architecture for Ultrafast Carry Originate-Propagate adders

Chapter 03: Computer Arithmetic. Lesson 03: Arithmetic Operations Adder and Subtractor circuits Design

Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

CPE100: Digital Logic Design I

Arithmetic Circuits-2

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process

An Optical Parallel Adder Towards Light Speed Data Processing

EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS

COE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits)

Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

Adders, subtractors comparators, multipliers and other ALU elements

E40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1

Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High speed counters

Outline. EECS150 - Digital Design Lecture 4 - Boolean Algebra I (Representations of Combinational Logic Circuits) Combinational Logic (CL) Defined

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

The equivalence of twos-complement addition and the conversion of redundant-binary to twos-complement numbers

Systems I: Computer Organization and Architecture

The logic is straightforward. Adding two 0s will result in 0. Adding two 1s results in 10 where 1 is the carry bit and 0 is the sum bit.

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Introduction to Digital Logic

Fundamentals of Digital Design

Sample Test Paper - I

Adders - Subtractors

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

Hakim Weatherspoon CS 3410 Computer Science Cornell University

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

Menu. 7-Segment LED. Misc. 7-Segment LED MSI Components >MUX >Adders Memory Devices >D-FF, RAM, ROM Computer/Microprocessor >GCPU

CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April

BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA

ALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1

Chapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory

CS221: Digital Design Data Path Components Adder

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

ECE380 Digital Logic. Positional representation

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Section 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic

Redacted for Privacy

EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap

Review for Test 1 : Ch1 5

Low Power, High Speed Parallel Architecture For Cyclic Convolution Based On Fermat Number Transform (FNT)

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

Part II Addition / Subtraction

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview

DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Digital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

VLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California

L8/9: Arithmetic Structures

Design of Low Power, High Speed Parallel Architecture of Cyclic Convolution Based on Fermat Number Transform (FNT)

CprE 281: Digital Logic

Part II Addition / Subtraction

Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

CMP 334: Seventh Class

Lecture 22 Chapters 3 Logic Circuits Part 1

Transcription:

Low Latency Architectures of a Comparator for Binary Signed Digits in a 28-nm CMOS Technology Martin Schmidt, Thomas Veigel, Sebastian Haug, Markus Grözing, Manfred Berroth Stuttgart, Germany 1

Outline Motivation Binary Signed-Digit Number System Adder Comparator Conclusion 2

Motivation 3

Motivation Applications for fast adders / multipliers: CPU / GPU Cryptography DSP 4

Motivation Applications for fast adders / multipliers: CPU / GPU Cryptography DSP FFT for optical OFDM transmitter QAM Mapper IFFT- Prozessor S 1 1 1 P I D A P N M M S Q D A 4

Motivation Applications for fast adders / multipliers: CPU / GPU Cryptography DSP FFT for optical OFDM transmitter Delta-sigma modulators for class-s power amplifiers X z 2 z 2 Y 1 +2 4

Motivation Methods to increase throughput of adders and multipliers: Carry look-ahead architectures 5

Motivation Methods to increase throughput of adders and multipliers: Carry look-ahead architectures % High complexity % Long interconnects in layout " MSB is sign bit 5

Motivation Methods to increase throughput of adders and multipliers: Carry look-ahead architectures % High complexity % Long interconnects in layout " MSB is sign bit Redundant number systems: Carry-save % Conversion necessary % Sign operation is very slow 5

Motivation Methods to increase throughput of adders and multipliers: Carry look-ahead architectures % High complexity % Long interconnects in layout " MSB is sign bit Redundant number systems: Carry-save % Conversion necessary % Sign operation is very slow (Binary) Signed-digit % Conversion necessary " Sign operation 5

Binary Signed-Digit Number System Sign-Zero Representation Difference Representation 6

Binary Signed-Digit (BSD) Number System X = N 1 i=0 x i 2 i with x i { 1, 0, 1} X x i BSD number BSD digit 7

Binary Signed-Digit (BSD) Number System X = N 1 i=0 x i 2 i with x i { 1, 0, 1} X x i BSD number BSD digit Redundancy: 0 1 1 4 3 1 1 1 2 = 3 1 0 1 1 3 7

Number Representation in BSD Number System Sign-zero representation: x = ( 1) xs (1 x z ) with x s, x z {0, 1} Sign operation equals leading-one detection Difference representation: x = x x with x, x {0, 1} Better for addition / multiplication Chosen for this design 8

Number Representation in BSD Number System Sign-zero representation: x = ( 1) xs (1 x z ) with x s, x z {0, 1} Sign operation equals leading-one detection Difference representation: x = x x with x, x {0, 1} Better for addition / multiplication Chosen for this design Coding of BSD digit x x Decimal number 00 0 11 0 10 +1 01 1 8

BSD Adder BSD-TC BSD-BSD 9

BSD-TC (Two s Complement) Adder Implementation of BSD adder with full adders and inverters: a FA b c in s = a b c c out = ab + ac + bc c out s inverted input/output 10

BSD-TC (Two s Complement) Adder Implementation of BSD adder with full adders and inverters: a FA b c in s = a b c c out = ab + ac + bc c out s inverted input/output 10

BSD-TC (Two s Complement) Adder Implementation of BSD adder with full adders and inverters: a FA b c in s = a b c c out = ab + ac + bc c out s inverted input/output Addition a + b = s n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 0 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 10

BSD-TC (Two s Complement) Adder Implementation of BSD adder with full adders and inverters: a FA b c in s = a b c c out = ab + ac + bc c out s inverted input/output Addition a + b = s BSD TC BSD n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 0 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 10

BSD-TC (Two s Complement) Adder Implementation of BSD adder with full adders and inverters: a FA b c in s = a b c c out = ab + ac + bc c out s inverted input/output Addition a + b = s BSD TC BSD n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 0 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 10

BSD-BSD Adder = BSD+(TC-TC) Addition a + b = s BSD TC BSD n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 0 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 11

BSD-BSD Adder = BSD+(TC-TC) Addition a - b = s BSD TC BSD n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 1 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 11

BSD-BSD Adder = BSD+(TC-TC) Addition a + b = a + b b = s BSD BSD BSD BSD BSD n 1 a n 1 n 2 a n 2 n 3 a n 3 0 a 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 0 FA b n 1 b n 2 b n 3 FA FA FA b 0 1 n s n n 1 s n 1 n 2 s n 2 n 3 s 1 0 s 0 11

Summary BSD Adder Advantages " Adder delay for BSD+TC sum single full adder delay " Adder delay for BSD+BSD sum two times full adder delay Delay independent of word width " Only local interconnects Easy layout 12

Summary BSD Adder Advantages " Adder delay for BSD+TC sum single full adder delay " Adder delay for BSD+BSD sum two times full adder delay Delay independent of word width " Only local interconnects Easy layout Disadvantages % Slow conversion to TC % Comparator / Sign operator is not as simple as in TC 12

BSD Comparator BSD-TC Converter Linear Search Tree Search 13

Comparator Architectures Conversion to TC MSB is sign bit Conversion to sign-zero representation Leading-One detector 14

BSD-TC Conversion n 1 a s BSD TC a n 1 n 2 a n 2 n 3 a n 3 0 a 0 FA 1 FA FA FA s n 1 s n 2 s n 3 s 0 15

BSD-TC Conversion n 1 a s BSD TC a n 1 n 2 a n 2 n 3 a n 3 0 a 0 FA 1 Ripple carry adder FA FA FA Y= s n 1 s n 2 s n 3 s 0 15

BSD-TC Conversion n 1 a s BSD TC a n 1 n 2 a n 2 n 3 a n 3 0 a 0 FA 1 Ripple carry adder FA FA FA Y= s n 1 s n 2 s n 3 s 0 15

Conversion to Sign-Zero Representation Difference representationx x Dec Sign-zero representation 00 0 x1 11 0 x1 01-1 10 10 +1 00 16

Conversion to Sign-Zero Representation Difference representationx x Dec Sign-zero representation 00 0 11 11 0 11 01-1 10 10 +1 00 a ( 1) bs (1 b z ) BSD Diff BSD SZ n 1 a n 1 n 2 a n 2 1 a 1 0 a 0 XOR AND XOR AND XOR AND XOR AND b z n 1 b s n 1 b z n 2 b s n 2 b z 1 b s 1 b z 0 b s 0 16

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 111000 zero 101011 sign 0 + 0 0 + 4 2 1 = +1 17

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 111 000 zero 101 011 sign -0+0-0 + 4 2 1 = +1 17

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 111 0 00 zero 101 0 11 sign 0 + 0 0 +4 2 1 = + 1 17

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 1110 00 zero 1010 11 sign 0 + 0 0 + 4-2-1 = +1 17

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 111000 zero 101011 sign 0 + 0 0 + 4 2 1 = +1-1 is coded in sign-zero representation: 111 0 00 zero 101 1 00 sign 0 + 0 0-4 + 2 + 1 = - 1 17

Sign-Zero Representation and Leading-One Detection Example: 1 is coded in sign-zero representation: 111000 zero 101011 sign 0 + 0 0 + 4 2 1 = +1-1 is coded in sign-zero representation: 111000 zero 101100 sign 0 + 0 0 4 + 2 + 1 = 1 Absolute value of n th -digit is larger than sum of all digits k<n Leading non-zero digit (zero i =0) of BSD number determines sign 17

Leading-One Detector: Linear Search n 1 a n 1 n 2 a n 2 1 a 1 0 a 0 XOR AND XOR AND XOR AND XOR AND b z n 1 b s n 1 b z n 2 b s n 2 b z 1 b s 1 b z 0 b s 0 Y M UX 0 1 M UX 0 1 M UX 0 1 18

Leading-One Detector: Linear Search n 1 a n 1 n 2 a n 2 1 a 1 0 a 0 XOR AND XOR AND XOR AND XOR AND b z n 1 b s n 1 b z n 2 b s n 2 b z 1 b s 1 b z 0 b s 0 Y M UX 0 1 M UX 0 1 M UX 0 1 18

Leading-One Detector: Tree Search - 2 Digits b z 1 b z 0 b s 1 b s 0 0 1 MUX AND c z 10 c s 10 19

Leading-One Detector: Tree Search - 4 Digits b z 3 b z 2 b s 3 b s 2 AND 0 1 MUX b z 1 b z 0 b s 1 b s 0 AND 0 1 MUX c z 32 c s 32 c z 10 c s 10 c z 10 c s 10 c z 32 c s 32 0 1 MUX AND d z d s 20

AND Tree - Sign Operator for 4 Digits n 1 a n 1 n 2 a n 2 1 a 1 0 a 0 XOR AND XOR AND XOR AND XOR AND b z 3 b s 3 b z 2 b s 2 b z 1 b s 1 b z 0 b s 0 b z 3 b z 2 b s 3 b s 2 AND 0 1 MUX b z 1 b z 0 b s 1 b s 0 AND 0 1 MUX c z 32 c s 32 c z 10 c s 10 c z 32 c z 10 c s 32 c s 10 0 1 MUX AND d z d s 21

AND Tree - Sign Operator for 4 Digits n 1 a n 1 n 2 a n 2 1 a 1 0 a 0 XOR AND XOR AND XOR AND XOR AND b z 3 b s 3 b z 2 b s 2 b z 1 b s 1 b z 0 b s 0 b z 3 b z 2 b s 3 b s 2 AND 0 1 MUX b z 1 b z 0 b s 1 b s 0 AND 0 1 MUX c z 32 c s 32 c z 10 c s 10 c z 32 c z 10 c s 32 c s 10 0 1 MUX AND d z Y = d s 21

Summary Comparator Transistor Delay Delay Comparator count Layout 4 digits 16 digits Ripple carry adder High Regular 48 ps 192 ps Linear search Low Regular 31 ps 153 ps AND tree Medium Hierarchical 14 ps 34 ps Delay is simulated in a 28 nm low power CMOS technology with low threshold voltage MOSFETs on schematic level (preliminary(!) models). 22

Conclusion BSD adder is independent of word width 3 BSD comparator architectures Conversion to two s complement Linear search Tree search 34 ps comparator delay for 16-digit BSD number 23

Thank you for your attention 24

2024 © sciencedocbox.com Privacy Policy | Terms of Service | Feedback