Inroducion o CMOS VLSI Design Chaper : DC & Transien Response David Harris, 004 Updaed by Li Chen, 010 Ouline DC Response Logic Levels and Noise Margins Transien Response Delay Esimaion Slide 1
Aciviy 1) If he widh of a ransisor increases, he curren will increase decrease no change ) If he lengh of a ransisor increases, he curren will increase decrease no change ) If he supply volage of a chip increases, he maximum ransisor curren will increase decrease no change 4) If he widh of a ransisor increases, is gae capaciance will increase decrease no change 5) If he lengh of a ransisor increases, is gae capaciance will increase decrease no change 6) If he supply volage of a chip increases, he gae capaciance of each ransisor will increase decrease no change Slide Aciviy 1) If he widh of a ransisor increases, he curren will increase decrease no change ) If he lengh of a ransisor increases, he curren will increase decrease no change ) If he supply volage of a chip increases, he maximum ransisor curren will increase decrease no change 4) If he widh of a ransisor increases, is gae capaciance will increase decrease no change 5) If he lengh of a ransisor increases, is gae capaciance will increase decrease no change 6) If he supply volage of a chip increases, he gae capaciance of each ransisor will increase decrease no change Slide 4
DC Response DC Response: vs. for a gae Ex: Inverer When = 0 -> = When = -> = 0 V In beween, depends on DD ransisor size and curren By KCL, mus sele such ha I = I dsp We could solve equaions Bu graphical soluion gives more insigh I dsp Slide 5 Transisor Operaion Curren depends on region of ransisor behavior For wha and are nmos and pmos in Cuoff? Linear? Sauraion? Slide 6
nmos Operaion Cuoff Linear Sauraed V gsn < V gsn > V gsn > V dsn < V dsn > I dsp Slide 7 nmos Operaion Cuoff Linear Sauraed V gsn <V n V gsn >V n V gsn >V n V dsn < V gsn V n V dsn > V gsn V n I dsp Slide 8 4
nmos Operaion Cuoff Linear Sauraed V gsn <V n V gsn >V n V gsn >V n V dsn < V gsn V n V dsn > V gsn V n V gsn = I dsp V dsn = Slide 9 nmos Operaion Cuoff Linear Sauraed V gsn <V n V gsn >V n V gsn >V n < V n > V n V dsn < V gsn V n < -V n > V n V dsn > V gsn V n > -V n V gsn = I dsp V dsn = Slide 10 5
pmos Operaion Cuoff Linear Sauraed V gsp > V gsp < V gsp < V dsp > V dsp < I dsp Slide 11 pmos Operaion Cuoff Linear Sauraed V gsp >V p V gsp <V p V gsp <V p V dsp > V gsp V p V dsp < V gsp V p I dsp Slide 1 6
pmos Operaion Cuoff Linear Sauraed V gsp >V p V gsp <V p V gsp <V p V dsp > V gsp V p V dsp < V gsp V p V gsp = - V p < 0 V dsp = - I dsp Slide 1 pmos Operaion Cuoff Linear Sauraed V gsp >V p V gsp <V p V gsp <V p > + V p < + V p V dsp > V gsp V p > -V p < + V p V dsp < V gsp V p < -V p V gsp = - V p < 0 V dsp = - I dsp Slide 14 7
I-V Characerisics Make pmos is wider han nmos such ha β n = β p V gsn5 V gsn4 V gsn -V dsp V gsp1 V gsp V gsp - 0 V dsn V gsn V gsn1 V gsp4 -I dsp V gsp5 Slide 15 Curren vs., 0 5, I dsp 1 4 4 1 Slide 16 8
Load Line Analysis For a given : Plo,I dsp vs. mus be where currens are equal in 0 5, I dsp 1 4 4 1 I dsp Vou Slide 17 = 0 Load Line Analysis 0, I dsp 0 Slide 18 9
Load Line Analysis = 0., I dsp 1 1 Slide 19 Load Line Analysis = 0.4, I dsp Slide 0 10
Load Line Analysis = 0.6, I dsp Slide 1 Load Line Analysis = 0.8, I dsp 4 4 Slide 11
Load Line Analysis = 0 5, I dsp 1 4 Slide Load Line Summary 0 5, I dsp 1 4 4 1 Slide 4 1
DC Transfer Curve Transcribe poins ono vs. plo A B 0 5 1 4 C 4 1 0 D E V n / +V p Slide 5 Operaing Regions Revisi ransisor operaing regions Region nmos pmos A B C D E A B 0 C D E V n / +V p Slide 6 1
Operaing Regions Revisi ransisor operaing regions Region nmos pmos A Cuoff Linear B Sauraion Linear C Sauraion Sauraion D Linear Sauraion E Linear Cuoff A B 0 C D E V n / +V p Slide 7 Bea Raio If β p / β n 1, swiching poin will move from / Called skewed gae Oher gaes: collapse ino equivalen inverer β p 0.1 β = n β p 10 β = n 1 0.5 0 Slide 8 14
Noise Margins How much noise can a gae inpu see before i does no recognize he inpu? Logical High Oupu Range Oupu Characerisics V OH NM H V IH V IL Inpu Characerisics Indeerminae Region Logical High Inpu Range Logical Low Oupu Range V OL NM L GND Logical Low Inpu Range Slide 9 Logic Levels To maximize noise margins, selec logic levels a β p /β n > 1 0 Slide 0 15
Logic Levels To maximize noise margins, selec logic levels a uniy gain poin of DC ransfer characerisic Uniy Gain Poins Slope = -1 V OH β p /β n > 1 V OL 0 V V IL V V n IH DD - V p Slide 1 Transien Response DC analysis ells us if is consan Transien analysis ells us if changes Requires solving differenial equaions Inpu is usually considered o be a sep or ramp From 0 o or vice versa Slide 16
Inverer Sep Response Ex: find sep response of inverer driving load cap Vi n ( ) = Vo u ( < 0) = dvou ( ) = d C load Slide Inverer Sep Response Ex: find sep response of inverer driving load cap Vin () = u ( 0 ) V Vou ( < 0) = dvou () = d DD C load Slide 4 17
Inverer Sep Response Ex: find sep response of inverer driving load cap Vin ( ) = u ( 0 ) V Vo u ( < 0) = VDD dvo u ( ) = d DD C load Slide 5 Inverer Sep Response Ex: find sep response of inverer driving load cap Vin () = u ( 0 ) V Vou ( < 0) = VDD dvo u ( ) Id sn () = d C load DD C load I V V V < V V 0 dsn () = Vou > DD ou DD Slide 6 18
I Inverer Sep Response Ex: find sep response of inverer driving load cap Vin () = u ( 0 ) V Vou ( < 0) = VDD dvo u ( ) Id sn () = d C load DD 0 0 β ) = ( V V) Vou > V V Vou ( ) β VDD V V () ou Vou < VDD V dsn ( DD DD C load Slide 7 I Inverer Sep Response Ex: find sep response of inverer driving load cap Vin () = u ( 0 ) V Vou ( < 0) = VDD dvo u ( ) Id sn () = d C load DD 0 0 β ) = ( V V) Vou > V V Vou ( ) β VDD V V () ou Vou < VDD V dsn ( DD DD 0 C load Slide 8 19
Delay Definiions pdr : pdf : pd : r : r f : fall ime Slide 9 Delay Definiions pdr : rising propagaion delay From inpu o rising oupu crossing / pdf : falling propagaion delay From inpu o falling oupu crossing / pd : average propagaion delay pd = ( pdr + pdf )/ r: rise ime From oupu crossing 0. o 0.8 f : fall ime From oupu crossing 0.8 o 0. Slide 40 0
Delay Definiions cdr : rising conaminaion delay From inpu o rising oupu crossing / cdf : falling conaminaion delay From inpu o falling oupu crossing / cd : average conaminaion delay pd = ( cdr + cdf )/ Slide 41 Simulaed Inverer Delay Solving differenial equaions by hand is oo hard SPICE simulaor solves he equaions numerically Uses more accurae I-V models oo! Bu simulaions ake ime o wrie.0 1.5 1.0 (V) pdf = 66ps pdr = 8ps 0.5 0.0 0.0 00p 400p 600p 800p 1n (s) Slide 4 1
Delay Esimaion We would like o be able o easily esimae delay No as accurae as simulaion Bu easier o ask Wha if? The sep response usually looks like a 1 s order RC response wih a decaying exponenial. Use RC delay models o esimae delay C = oal capaciance on oupu node Use effecive resisance R So ha pd = RC Characerize ransisors by finding heir effecive R Depends on average curren as gae swiches Slide 4 RC Delay Models Use equivalen circuis for MOS ransisors Ideal swich + capaciance and ON resisance Uni nmos has resisance R, capaciance C Uni pmos has resisance R, capaciance C Capaciance proporional o widh Resisance inversely proporional o widh g d k s g R/k kc d s kc kc Slide 44 g d k s g kc s d R/k kc kc
Example: -inpu NAND Skech a -inpu NAND wih ransisor widhs chosen o achieve effecive rise and fall resisances equal o a uni inverer (R). Slide 45 Example: -inpu NAND Skech a -inpu NAND wih ransisor widhs chosen o achieve effecive rise and fall resisances equal o a uni inverer (R). Slide 46
Example: -inpu NAND Skech a -inpu NAND wih ransisor widhs chosen o achieve effecive rise and fall resisances equal o a uni inverer (R). Slide 47 -inpu NAND Caps Annoae he -inpu NAND gae wih gae and diffusion capaciance. Slide 48 4
-inpu NAND Caps Annoae he -inpu NAND gae wih gae and diffusion capaciance. C C C C C C C C C C C C C C C C Slide 49 -inpu NAND Caps Annoae he -inpu NAND gae wih gae and diffusion capaciance. 5C 5C 5C 9C C C Slide 50 5
Elmore Delay ON ransisors look like resisors Pullup or pulldown nework modeled as RC ladder Elmore delay of RC ladder R C pd i o source i nodes i ( )... (... ) = RC + R + R C + + R + R + + R C 1 1 1 1 R R R R 1 N N N C 1 C C C N Slide 51 Example: -inpu NAND Esimae wors-case rising and falling delay of - inpu NAND driving h idenical gaes. A B x Y h copies Slide 5 6
Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies Slide 5 Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies R Y (6+4h)C pdr = Slide 54 7
Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies R Y = ( 6+ 4 ) (6+4h)C pdr h RC Slide 55 Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies Slide 56 8
Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C pdf = Slide 57 Example: -inpu NAND Esimae rising and falling propagaion delays of a - inpu NAND driving h idenical gaes. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C pdf ( R R R )( ) ( 6 4 ) ( ) ( 7 4h) RC = C + + h C + = + Slide 58 9
Delay Componens Delay has wo pars Parasiic delay 6 or 7 RC Independen of load Effor delay 4h RC Proporional o load capaciance Slide 59 Conaminaion Delay Bes-case (conaminaion) delay can be subsanially less han propagaion p delay. Ex: If boh inpus fall simulaneously A B x 6C C Y 4hC R R Y (6+4h)C cdr ( ) = + h RC Slide 60 0
Diffusion Capaciance we assumed conaced diffusion on every s / d. Good layou minimizes diffusion area Ex: NAND layou shares one diffusion conac Reduces oupu capaciance by C Merged unconaced diffusion migh help oo Shared Conaced Diffusioni Merged Unconaced Diffusion C C C C C Isolaed Conaced Diffusion 7C C C Slide 61 Layou Comparison Which layou is beer? A B A B Y Y GND GND Slide 6 1