Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there are two permitted values: v(t) DIGITAL t t 28/02/2006 1 28/02/2006 2 In real life The digital advantage A digital signal takes time to change from one value to another, and assumes intermediate values during transition Steady values are slightly inaccurate Voltages within certain ranges are guaranteed to be interpreted as certain permitted values (green regions) v(t) V s 0 (V s = supply voltage) Interpreted as HIGH AMBIGUOUS Interpreted as LOW A digital signal transition t Because voltages within a certain range are interpreted as a single value, a digital signal can contain a certain amount of error (eg distortion, noise, interference) and still be read correctly As long as we regenerate the signal (read it and reconstruct it with electronic circuits) before the error becomes too large, we can remove the error In an analog signal, we cannot tell whether the value is affected by error, because all values are permitted Digital signals can be copied, transmitted and processed without error Analog signals cannot 28/02/2006 3 28/02/2006 4
Combinational vs Sequential Notation; Truth Tables (2) Digital circuits may be classified as combinational or sequential In a combinational circuit, the present outputs depend only on present inputs (subject to reaction times) In a sequential circuit, the present outputs may also depend on past outputs and inputs Sequential circuits usually contain combinational subcircuits The two classes of circuits have different topologies Sequential circuits contain feedback paths from the outputs to the inputs, while combinational circuits do not The values TRUE and FALSE may also be called 1 and 0, IN and OUT, ES and NO, SET and CLEAR, ON and OFF, MARK and SPACE The truth tables have been rewritten using 1 and 0 NOT : 0 1 1 0 OR AND + 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 28/02/2006 5 28/02/2006 6 Logic gates: OR, AND, NOT Inversion bubbles, NAND & NOR If TRUE and FALSE (or 1 and 0) are represented by two different voltages, we can perform logical operations using circuits called logic gates An OR gate performs the OR (+) operation Its circuit symbol is: Z = + An AND gate performs the AND () operation Its circuit symbol is: Z = A NOT gate or inverter performs the NOT operation; its circuit symbol is: Z = The circle in the NOT gate symbol is called an inversion bubble A bubble on the output (or input) of another symbol indicates inversion; eg: means Z = In fact, an AND gate with output inversion is called a NAND gate ( Not AND ) Similarly, an OR gate with inverted output is called a NOR gate ( Not OR ) Z = () Z = (+) 28/02/2006 7 28/02/2006 8
NAND and NOR truth tables De Morgan s laws (1) By inverting the output columns of the AND and OR truth tables, we obtain the following: NOR NAND (+) () 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 For the NOR, the output is false iff (if and only if) either input is true; that is, the output is true iff both inputs are false For the NAND, the output is false iff both inputs are true; that is, the output is true iff either input is false In other words In a NOR gate, the output is TRUE iff the inverses of both inputs are TRUE; that is, a NOR gate performs and AND operation on the inverses So there are two symbols for a NOR gate: In a NAND gate, the output is TRUE iff the inverse of either input is TRUE; that is, a NAND gate does an OR operation on the inverses So there are two symbols for a NAND gate: 28/02/2006 9 28/02/2006 10 De Morgan s laws (2) The Exclusive-OR (OR) operation If we convert the two NOR symbols into algebraic expressions and equate them, we get (+) = Doing likewise with the NAND symbols, we get () = + These equations are called De Morgan s laws If they are not already obvious, try expressing them in words: Not ( or ) = neither nor = (not ) and (not ) Not ( and ) = not both and = (not ) or (not ) Now omit the middle expressions The OR function in logic is inclusive; or means or or both The exclusive-or function, as its name suggests, excludes the or both option: xor means or but not both In equations, xor is often written The truth table is xor 0 0 0 0 1 1 1 0 1 1 1 0 and the gate symbol is xor 28/02/2006 11 28/02/2006 12
Exclusive-NOR/equivalence gate AND-OR formulation of OR Inverting the output of an OR gate gives an exclusive-nor (NOR) or equivalence gate NOR truth table: ( xor ) 0 0 1 0 1 0 1 0 0 1 1 1 NOR gate symbol: ( xor ) The truth table shows why the NOR gate is called an equivalence gate: the output is true iff the inputs are the same (For the OR, the output is true iff the inputs are different) As we shall see, OR gates are used in addition and subtraction circuits Hence it is of interest to see how such gates can be constructed From the truth table, xor is true iff ( is false and is true) or ( is true and is false) More concisely, xor means ([not ] and ) or ( and [not ]) That is xor = + Note the priority of operators in the above equation: NOT ( ) comes first, followed by AND, then OR (Cf powers, multiplication, addition) 28/02/2006 13 28/02/2006 14 AND-OR and NAND-NAND forms Commutative laws The function xor = + may be implemented using the circuit below Now let us introduce two inversion pairs [top right] xor xor This circuit is equivalent to the previous one [left] because the inversions cancel out But now all the multiple-input gates are NAND gates The OR, AND and OR functions are commutative; that is, for all,, + = + = xor = xor These laws are obvious because the verbal definitions of OR, AND and OR use words like either, both and only one, which do not distinguish between the two inputs The laws can be verified by swapping the input columns in the truth tables, and then reordering the rows to restore the original patterns of 1 s and 0 s Try it 28/02/2006 15 28/02/2006 16
Associative laws Many-input gates OR and AND are also associative; that is, for all,,z, (+)+Z = +(+Z) ()Z = (Z) These laws can also be verified using truth tables The implication is that the expressions ++Z and Z are unambiguous Repeated applications of the associative laws indicate that OR and AND combinations with 4 or more variables are also unambiguous The commutative law can be brought in to show that these multi-variable expressions can be written in any order Expressions with three or more variables are implemented by logic gates with three or more inputs: Their names and functions of these gates are obvious Of course the outputs may be inverted [top right] In a multi-input AND gate, the output is true iff all of the inputs are true In a multi-input OR gate, the output is true iff any (one or more) of the inputs are true In multi-input NAND and NOR gates, the output is FALSE under the same input conditions 28/02/2006 17 28/02/2006 18 De Morgan s laws - many inputs (2) The many-input forms of De Morgan s laws, like the two input forms, yield alternative symbols for logic gates: NAND: NOR: The summary rule still holds: To make an x-gate, invert the inputs to a y-gate, where one of x,y is an AND and the other is an OR, and only one is inverted 28/02/2006 19 Other associative laws? (1) Recall that the associative laws hold for OR and AND They do not hold for NOR or NAND ((+) +Z) is not identical to (+(+Z) ), and neither is identical to the three-input NOR function (++Z) = ((+)+Z) = (+(+Z)) Similarly, (() Z) is not identical to ((Z) ), and neither is identical to the three-input NAND function (Z) = (()Z) = ((Z)) The three-way equalities are of course based on the associative laws for OR and AND 28/02/2006 20
Parity-testing circuits Each of the following circuits combines n inputs using n-1 OR gates, and produces an output of 1 iff the number of input 1 s is odd Other gate arrangements are possible n = 3: n = 6: 28/02/2006 21 Two-level logic A sum of products (SOP) or product of sums (POS) is a two-level expression because it can be implemented by two layers of gates (excluding initial inverters) The two two-level implementations of W = Z + Z + = ( + +Z )(+Z)(+) are shown below [SOP on the left, POS on the right]: Z Z W 28/02/2006 22 Z Z W Sum of products; minterms (1) Sum of products; minterms (2) The truth table for is S = A xor B Row A B S 0 0 0 0 1 0 1 1 2 1 0 1 3 1 1 0 S is true on rows 1 and 2 On row 1, A B is true On row 2, AB is true The region where S is true is the union of the two rows, so the sum-of-products form of S is S = A B + AB A product corresponding to one row of the truth table (eg A B for the row 0) is called a minterm The minterm number (or row number in the truth table) is obtained by reading the inputs as a multi-bit binary number There is a widely-used shorthand notation in which each minterm is identified by a letter m followed by the minterm number So, in a 2-input truth table, the minterms are,, and This leads to alternative notations for the sum-of-products (SOP): S = A B + AB = + = Σm(1,2) NB: In a minterm, each input appears exactly once 28/02/2006 23 28/02/2006 24
Product of sums; maxterms (1) Product of sums; maxterms (2) We stay with S = A xor B: Row A B S 0 0 0 0 1 0 1 1 2 1 0 1 3 1 1 0 The region where S is false is the union of the other two rows, or rows 0 and 3: S = A B + AB Inverting both sides and using De Morgan s laws, we get a product of sums: S = (A B + AB) = (A B ) (AB) = (A+B)(A +B ) A sum in which each input variable appears exactly once is called a maxterm Notice that the literals in the POS form of S are the complements of those in the SOP form of S But we still define the maxterm number as the row number (for each row where the function is false) So the literals in the maxterm are the complements of those on the corresponding row A maxterm is identified by a capital M followed by its number; so S = (A+B)(A +B ) = M0M3 = ΠM(0,3) Again, notice that the literals in each maxterm are complemented to work out the maxterm number 28/02/2006 25 28/02/2006 26 Three-variable SOP/POS example DON T CARE outputs The truth table for the carry-out of a full adder is: Row A B C Cout 0 0 0 0 0 1 0 0 1 0 2 0 1 0 0 3 0 1 1 1 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 Sum of products: Cout = + m5 + m6 + m7 = A BC + AB C + ABC + ABC Product of sums: Cout = M0M1M2M4 = (A+B+C)(A+B+C ) (A+B +C)(A +B+C) NB: The minterm/maxterm numbers are the row numbers for which the function is 1/0 If we know that certain combinations of inputs cannot occur, it does not matter what outputs are produced for the forbidden inputs These don t care outputs are shown as s on truth tables and K-maps For the purpose of minimizing the function on a K-map, each may be interpreted as a 1 or 0 as convenient; that is, each may be included or not included in the union of rectangles showing where the function is true, so as to simplify the pattern 28/02/2006 27 28/02/2006 28
BCD to 7-segment converter (1) Suppose we wish to display the digits 0 to 9 on a 7- segment display, as shown below For each displayed digit, the input is a Binary Coded Decimal (BCD) number, ie one of the binary numbers 0000 to 1001 The numbers 1010 to 1111 (A to F hex) are not used; these are the minterm numbers which produce don t-care outputs 28/02/2006 29 BCD to 7-segment converter (2) Each displayed digit has 7 segments, called S0, S1,, S6 The same names refer to the logical variables that control the segments; if the variable is TRUE, the segment is ON Each displayed digit is controlled by a converter with 7 outputs S0, S1,, S6 Each output is a function of four inputs A,B,C,D, which represent the BCD digit ABCD 2 S0 S0 S1 S5 S1 A BCD S2 S6 B to S3 C 7-seg S4 S4 S2 D S5 S3 conv S6 28/02/2006 30 Other implementation methods We have seen how to implement logic functions using AND-OR and OR-AND configurations Some other systematic methods (related to the AND-OR structure) make use of the following devices: Multiplexer (MU), Demultiplexer (DEMU) or decoder (Dec), Read-Only Memory (ROM), Programmable Logic Array (PLA), Programmable Array Logic (PAL) These devices are discussed on the following slides 28/02/2006 31 Multiplexer/demultiplexer pair Suppose we want to send 8 logical variables (8 bits) over a single wire We can share the wire as follows A multiplexer (MU) selects one of the 8 inputs and feeds it to the wire A decoder (Dec) or demultiplexer (DEMU) directs the signal to the appropriate output The desired input/output is indicated by a 3-bit binary number ABC Eight inputs D0 D7 8:1 MU ABC 28/02/2006 32 Z single wire 1:8 Dec E ABC D0 D7 Eight outputs
Implementation of 4:1 multiplexer 2 n :1 multiplexer If we have four inputs, the selected input can be specified with a 2-bit binary number AB From the diagram, the output is Z = A B D0 + A BD1 + AB D2 + ABD3 = D0 + D1 + D2 + D3 Only one minterm is true; let it be mi Then Z reduces to midi = 1Di = Di D0 D1 D2 D3 A B Z A 2 n :1 MU follows the same pattern It has n select lines, n inverters (for the select inputs), 2 n data inputs, 2 n AND gates (each with n+1 inputs) and a 2 n - input OR gate (Putting n=2 confirms that a 4:1 MU has 2 select lines, 2 inverters, 4 data inputs, 4 3-input AND gates and a 4-input OR gate) The 2 n :1 MU output is Z = D0 + D1 + + n-1 D2 n-1 Again, one and only one minterm is true If the true minterm is mi, the output reduces to Z = midi = 1Di = Di, which is the selected input 28/02/2006 33 28/02/2006 34 A MU can generate any function! The extra input A 2 n :1 MU with data inputs D0, D1,, D2 n produces the output Z = D0 + D1 + + n-1 D2 n-1 This is simply the sum of all the minterms for which the corresponding data inputs are true (1) We can pick any set of minterms, and hence implement any function, simply by setting the appropriate inputs to 1 In this way, a 2 n :1 MU can implement any function of n variables Indeed, it can implement any function of n+1 variables if we allow the extra variable to be true or inverted We wish to implement a function Z which depends on the n+1 variables S 0, S 1, S 2,, S n-1, S n We use the first n variables S 0, S 1, S 2,, S n-1 as the select inputs of a 2 n :1 MU For any combination of the select inputs, there are two values of S n and hence four ways in which Z can depend on S n ; these are shown as Z 0 to Z 3 in the table: S n Z 0 Z 1 Z 2 Z 3 0 0 0 1 1 1 0 1 0 1 Notice that Z 0 = 0, Z 1 = S n, Z 2 = S n and Z 3 = 1 So we feed one of these four functions of S n into each data input of the MU 28/02/2006 35 28/02/2006 36
Implementation of 1:4 decoder In the diagram we see that D0 = E A B D1 = E A B D2 = E AB D3 = E AB or, in general, Di = Emi ; i = 0,1,2,3 where mi is the ith minterm of A,B If mj is the true minterm, then Dj = E and all other Di are 0 Thus E is fed to the output selected by AB The data input is called E for Enable ; if E=0, all the outputs are 0 28/02/2006 37 E A B D0 D1 D2 D3 Minterm generator 1:4 If we set E=1, the blue equation Dec on the previous slide reduces to Di = mi ; i = 0,1,2,3 E Thus the decoder generates all the minterms at once, and we can create any function of A,B by OR-ing the available minterms The diagram shows how to implement F1 = + and F2 = ++ Notice that the minterms generated by Question: F1 and F2 the decoder can be re-used have names What are they? F1 F2 28/02/2006 38 A B AND-OR shorthand diagrams The circuit on the previous slide has an inverter array to give the complemented select inputs, an AND gate array to generate the minterms, and an OR gate array to form the desired functions from the minterms This structure can be represented by a shorthand diagram like that on the right Connections to separate gate inputs are shown as crosses on a common input line This diagram shows the same circuit as the previous slide E A B AND plane OR plane F1 F2 28/02/2006 39 1:8 decoder This shorthand diagram shows the internal circuit of 1:8 decoder It has three inverters and eight 4-input AND gates It has no OR plane, but an external OR plane might be added to compute several functions from the eight minterms (The outputs are minterms provided that E=1) 28/02/2006 40 E A B C m4 m5 m6 m7
ROM concept (1) A B C ROM concept (2) A B C The diagram shows four functions implemented by a 1:8 decoder and an OR plane The select lines specify a 3-bit binary number ABC, which we may regard as an address The four outputs W,,,Z may be regarded as a 4-bit binary number located at the address ABC Address decoder (no enable) m4 m5 m6 m7 W Z that is, WZ 2 is the contents of the address ABC 2 Thus the complete circuit comprises a Read- Only Memory or ROM If an address decoder output is connected to an OR input, there is a 1 at that address Hence the contents may be read from the connection plane Connection plane m4 m5 m6 m7 W Z 28/02/2006 41 28/02/2006 42 ROM concept (3) A cross on the connection plane means a 1 in the truth table or contents table: A B C W Z 0 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 A B C Compare Connection plane W Z 28/02/2006 43 m4 m5 m6 m7 BCD to 7-segment converter in ROM A B C D S S 0 1 S 2 S 3 S 4 S 5 S 6 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 1 0 x x x x x x x 1 0 1 1 x x x x x x x 1 1 0 0 x x x x x x x 1 1 0 1 x x x x x x x 1 1 1 0 x x x x x x x 1 1 1 1 x x x x x x x The truth table or contents table [left] is implemented directly by a 2 4 x 7 ROM (or, more likely, a 2 4 x 8 ROM with one output line unused) S0 S5 S4 S2 S3 28/02/2006 44 S6 S1