ANALYICAL SOI MOSFE MODEL VALID FOR GRADED-CHANNEL DEVICES Benjamín Iñíguez 1, Marcelo Antonio Pavanello 2,3, João Antonio Martino 3 and Denis Flandre 4 3 Escola ècnica Superior d`engenyeria Universitat Rovira I Virgili, arragona, Spain 2 Center for Semiconductor Components State University of Campinas, Campinas, Brazil 3 Laboratório de Sistemas Integráveis Escola Politécnica da Universidade de São Paulo 4 Laboratoire de Microéletronique Université Catholique de Louvain, Louvain-la-Neuve, Belgium
Outline: Introduction Analytical Model Formulation Results and Discussion Fabrication Process and Experimental Results Conclusion
Introduction - 1 he advantages of Fully-depleted SOI nmosfes over Partially-Depleted (PD) and bulk MOSFEs are well known 1) Lower subthreshold ideality factor 2) Reduced short-channel effects 3) Better analog performance 4) Better microwave performance (gain, speed and cutoff frequency) 5) Lower 1/f and thermal noise As a consequence, FD SOI MOSFE is a very good candidate for low-power and low-noise microwave circuits
Introduction - 2 However, Fully-Depleted SOI nmosfes suffer from some Parasitic Bipolar Effects due to the Floating Body Premature Drain Breakdown Parasitic Bipolar ransistor Action: Emitter Source Base Body (floating) Collector Drain Some of the proposed solutions: Í Bandgap Engineering (Ge implanted) [M. Yoshimi et al., IEDM 94, p. 429] Í Source-Body Contact [IEDM 94, p. 657] Í Asymmetric Channel Profile using tilt implantation [B. Cheng et al., IEEE Int. SOI Conference, p. 113, 1998]
HE GRADED-CHANNEL (GC) SOI nmosfe ½ FD SOI CMOS technology fully compatible processing ½ One photolitographic step is used to adjust the threshold voltage ionic implantation position L Introduction - 3 ½ his photolithographic step is the same used to mask the p-type transistor NO additional photolithographic step has to be included in the CMOS processing. ½ he effective channel length is about L- Field Oxide Source N+ N A Poly natural doping Drain N+ Field Oxide Buried Oxide Substrate
Introduction - 4 Reported results indicate: Increase in the breakdown voltage remendous reduction in the drain output conductance Increase in the transconductance he Graded-Channel SOI MOSFE is a great candidate for analog circuits resulting in improved amplifiers and current mirrors Our goal: Development of a continuos model for GC transistor to allow reliable simulation of analog circuits
Introduction - 5 Schematic doping profile along channel log(n A ) N AF, HD N AF, LD y HD y LD L y direction In the interval y HD y y LD N A = N AF,HD exp ( y y ) 210 HD -4 2
Introduction - 6 Based on physical principles, an analytical FD SOI MOSFE model was developed by B. Iñiguez et al. For a conventional fully-depleted SOI nmosfe: I DS = Wµ Q nf dφ sf dy v dq dy here is a linear relation between the surface potential, φ sf, and the inversion charge density, Q nf : nf Q nf = C V GF V FBf Q 2C b C C bb V GB V FBb + Q 2C b oxb nφ SF
Integrating the inversion charges along channel results: I DS µ W = L [ v nf,d nf, S ( Q Q ) Introduction - 7 An explicit and unified expression for Q nf is used in the I DS equation (proposed by Iñiguez et al):. 2 nf,d 2 n C Q 2 nf,s Q nf,d and Q nf,s are the inversion charge densities at the drain and source, respectively Q Q0 Qnf = C nvs C V ( ) N GF Vth Fi nv y V log 1+ exp + exp n v SN n v GF Vth n v F S nv N ( y) his model is continuous, valid from weak to strong inversion regimes
Introduction - 8 hese physical principles allow to develop a complete CAD model and to adapt it to many conditions 1- Short-channel effects included DIBL and charge sharing Velocity saturation Channel length modulation 2- Complete charge model 3- Scalability down to 0.16 µm 4- emperature dependencies included. Model validated up to 300 o C : 5-Macro-model developed to extend the model to the microwave range. Accuracy demonstrated up to 40 GHz..
Analytical Model Formulation - 1 For long-channel transistors, the transition region into the channel (from y HD y y LD ) can be considered negligible: With this assumption, there will be two explicit equations for the inversion charges in the low doped (Q nf, LD ) and conventionally doped (Q nf, HD ) parts of the channel Q = C nf,ld nv S N log 1 + Q n v 0,LD S C N V exp GF Vth Fi,LD n v nv ( y) V + exp GF Vth n v F,LD S N nv ( y) Q = C nf,hd nv S N log 1 + Q n v 0,HD S C N V exp GF Vth Fi,HD n v nv ( y) V + exp GF Vth n v F,HD S N nv ( y) V(y) is the potential variation along channel
Integrating the inversion charges along channel results: Analytical Model Formulation - 2 I DS L L = µ HDW 0 LD Q nf,hd n C dq nf, HD dy v dq nf,hd dy L = µ LDW L L LD Q nf,ld n C dq nf, LD dy v dq nf,ld dy I DS = µ HD L L W LD [ v nf,hd L nf, HD LLD 0 ( ) Q Q Q nf,hd L 2 2 n C Q nf,hd 0 2 I DS = µ LD L LD W [ v nf,ld L nf, LD L LLD ( ) Q Q Q nf,ld L 2 Q 2 n C nf,ld he GC SOI nmosfe is therefore interpreted as a series association of two conventional transistors, each one representing a part of the channel region L 2
Results and Discussion - 1 Comparison between MEDICI numerical two-dimensional simulations and model equations solution Device characteristics: t =30 nm, t Si =80 nm, t oxb =400 nm, Q ox1 /q=q ox2 /q=5 x 10 10 cm -2, N AF, HD =10 17 cm -3 and N AF, LD =10 15 cm -3. L=10 µm
Gate characteristics in the linear regime Results and Discussion - 2 1.2 1.0 I DS [A/µm] 0.8 0.6 0.4 MEDICI Model /L=0.50 /L=0.25 0.2 V DS =0.1 V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V GF [V]
Results and Discussion - 3 Gate characteristics in linear regime 10-5 10-6 /L=0.50 10-7 /L=0.25 I DS [A/µm] 10-8 10-9 10-10 10-11 MEDICI Model V DS =0.1 V 10-12 0.5 1.0 1.5 2.0 2.5 3.0 V GF [V]
Drain characteristics 0.25 Results and Discussion - 4 0.20 /L=0.5 I DS [A/µm] 0.15 0.10 /L=0.25 0.05 V G =200 mv MEDICI Model 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V DS [V] Excellent agreement between the model and MEDICI simulations he increase of I DS with /L (L( eff reduction) is greatly modeled
Experimental Results - 1 Drain characteristics - L = 4µm 100 80 /L=0.50 I DS [µa] 60 40 /L=0.37 /L=0.25 FD SOI 20 Experimental Model V G =500 mv 0 0 1 2 3 V DS [V] he tremendous increase in the Early voltage is adequately reproduced by the model
Gate characteristics in saturation - L = 2µm Experimental Results - 2 I DS [A] 10-3 10-4 LLD/L=0.51 10-5 10-6 10-7 10-8 10-9 10-10 10-11 V DS =1.5 V /L=0.25 Model Experimental 0.0 0.5 1.0 1.5 2.0 V GF [V]
Experimental Results - 3 ransconductance over drain current vs scaled drain current L = 2µm 40 g m /I DS [V -1 ] 30 20 model experimental 10 V DS =1.5 V 0 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 I DS /(W/L eff ) [A]
Conclusion - 1 Our unified FD SOI MOSFE model has been adapted to long-channel Graded-Channel SOI nmosfe based on a series association of transistors to represent the channel doping profile he validity of the proposed model has been verified by both numerical simulations and experimental results An excellent agreement has been found in both cases
Acknowledgements Brazilian Federal Agency CNPq for the financial support UCL Microelectronics Laboratory Staff for the device processing