CPU NORTH BRIDGE SOUTH BRIDGE

0_lock iagram 0_System Setting 0_Power Sequence 0_lock Gen_ISLPR 0_iamondville_US 0_iamondville_PWR 0_N-GMS(HOST) 0_N-GMS(MI) 0_N-GMS(GRPHI) 0_N-GMS(R) _N-GMS(PWR) _N-GMS(PWR) _N-GMS() _S-IHM(PWR) _S-IHM() _S-IHM() _S-IHM() _R SOIMM _R_Termination 0_Onboard VG _L onn_li _G _Mini WIFI+ T _LN_theros R _RJ _G-Sensor _US Port _amera onn _ard Reader_U 0_odec_L _udio_mp_jack _E_ENE K0 _E _Switch_SPI ROM_ebug onn _Thermal Sensor_FN _K_Touch Pad _LE_THERMTRIP _ischarge _PWR Jack/ST/US onnector 0_Srew Hole _EMI _POWER FLOW _Vcore _Power System _Power_+.V & VTTR _Power_VP _Power_+.VS & +.VS _Power_harger _E Pin efine 0_G Power _History L oard L ITP/ebug onn SPI ROM(SON) ard Reader oard S/MM ard Reader ard Reader lcor U E Internal K RT I/O oard ENE K0 US Port * US Port * I/O oard ard Reader onn luetooth onn amera onn LVS RG LP Touch Pad/SIM ard US_P US_P US US_P US_P US_P PU tom N0/N0 FG NORTH RIGE IH-M FS/00MHz GSE x MI SOUTH RIGE PIE 00/MHz hannel ZLI PIE_ US_P PIE_ PIE_ ST LOK GEN ISLPR THERML ONTROL SOIMM 00P I/O oard ZLI OE LN Realtek L HLF MINIR WIFI onn theros RM Standard ST onn 00H SUSTek omputer IN. INT MI WLN RJ- 00H.G LINE OUT/EXT MI Speaker.G WLN I/O oard 00H System Setting aron Tsao ate: Friday, March, 00 Sheet of.g

EEE P 0 P version GPI 0 GPI 0 0 0 0 0 0 0 0 0 0 0 GPI 0 0 0 0 0 0 0 0 0 0 0 0 P version US US 0 US US US US US US US US onn US onn N N ard Reader Minicard luetooth amera PIE PIE PIE PIE PIE N LN Minicard SS zalia Z_SIN0 Z_SIN Z_SIN OE N N 00H SUSTek omputer IN. 00H System Setting aron Tsao ate: Friday, March, 00 Sheet of.g

T_IN /_OK_IN dapter T attery Signal S0/S S VSUS_ON H H SUS_ON H L SUS_ON H H _T_SYS MXETI S/S Power dapter H VS attery L L Main L UL _OK _T_SYS VSUS_ON _T_SYS SUS_ON RT0 V RT0 +V +V +VSUS +VSUS VSUS_PWRG +VSUS +.V +VSUS SUS_ON +VSUS SUS_ON _T_SYS SUS_ON 0T0 0T0 PW EN +VS +VS +.VS +.V +VS +VS EN RT PL +VTT_R +.VS +V VSUS_ON VSUS_PWRG PWR_SW# ENE K0 SUS_ON SUS_ON PU_VRON VRM_PWRG E_PWROK 0 VRM_PWRG E_PWROK LVG0 PM_PWROK _T_SYS SUS_ON V RT0 EN +VS +VP VP_PWRG 0 PI_RST# LK_PI_E +VP +.V H_PWRG _T_SYS +.VS H_PWRG +.VS H_PURST# iamondville VI[:0] P0 PU_VRON +.VS LK_LK_MH +VP VORE VRM_PWRG +V_RT VRM_PWRG Intel LK_PIE_MH + 0 TT GMS PM_PWROK +VSUS LK_M_UM 0 VRM_PWRG LK_LK_PU LK_L_LVS +VSUS PI_RST# +.VSUS PLT_RST# (internal) PLT_RST# MLK_R Intel +VS IH-M SOIMM LK_PIE_IH +VS LK_ST_IH +.VS LK_M_US +VS Onboard PI_RST# +.VS +VSUS Flash LK_PI_IH +VP FS LK 00M LK_REF_IH PU MH ITP VP_PWRG VTT_PWRG# +VSUS +VS +.VS +VSUS PM_RSMRST# PM_PWRTN# MINIR SUS# Onboard LN SUS# LK_PIE_MINIR PLT_RST# LK_PIE_LN PLT_RST# REF LK M IH US LK M IH PI LK M IH E EUG ST LK 00M IH ISLPR PIE LK 00M MH IH MINIR LN LVS LK 00M MH UM LK M MH +VS 00H Flash Module SUSTek omputer IN. PI_RST# 00H 0 Power Sequence aron Tsao ate: Friday, March, 00 Sheet of.g

R [,] VP_PWRG [] LK_M_UM [] LK_M_UM# [] LK_L_LVS [] LK_L_LVS# [] LK_PIE_MH [] LK_PIE_MH# [] LK_PIE_WiMax [] LK_PIE_WiMax# [] LK_PIE_MINIR [] LK_PIE_MINIR# [] LK_ST_IH [] LK_ST_IH#.Mhz X /LK LK_XIN LK_XOUT PF/V /LK /LK/X LK_PEREQ# LK_PEREQ# LK_FS LK_ITP_EN LK_SEL_# LK_FSL LK_M LK_M# LK_FSL LK_L LK_L# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_ST LK_ST# +V_LK Selected through the Ic :isable 0:Enable PF/V /LK +VSUS ISLPRSGLF /LK 0UF/.V /LK +V_LK 0Ohm/00Mhz /LKL 0UF/.V /LK U V MHz PI&PIEX_STOP# PEREQ# PU_STOP# PEREQ# REF0/FSL FS/PILK0 O_PEREQ# VPI X 0 ITP_EN/PILK_F0 X SEL_#/_MHz VREF 0 Vtt_PwrGd/P# ST V SLK FSL/US_MHz PUT_LR0 OTT_MHzLR PU_LR0 OT_MHzLR VPU FSL PUT_LR PIeT_LR0 PU_LR 0 PIe_LR0 RESET# PIeT_LR 0 PIe_LR V VPIEX PUITPT_LR/PIeT_LR PIeT_LR PUITP_LR/PIe_LR PIe_LR VPIEX PIeT_LR PIeT_LR PIe_LR PIe_LR STLKT_LR PIeT_LR STLK_LR PIe_LR 0 VPIEX +V_LK_V +V_LK 0.UF/.V /LK LK_FSL LK_PEREQ# LK_XIN LK_XOUT LK_LK0 LK_LK#0 LK_LK LK_LK# LK_LK LK_LK# LK_PIE LK_PIE# LK_PIE LK_PIE# 0.UF/.V /LK 0.UF/.V /LK STP_PI# [] STP_PU# [] S_SM_T [] S_SM_LK [] LK_LK_PU [] LK_LK_PU# [] LK_LK_MH [] LK_LK_MH# [] LK_LK_ITP [] LK_LK_ITP# [] LK_PIE_IH [] LK_PIE_IH# [] LK_PIE_LN [] LK_PIE_LN# [] 0.UF/.V /LK 0.UF/.V /LK LK_ITP_EN LK_FSL LK_SEL_# LK_PEREQ# LK_FSL LK_FSL LK_FS LK_PEREQ# 0.UF/.V /LK 0 0.UF/.V /LK R.KOhm /LK R +V_LK /LK/N0 R.KOhm /LK/N0 R.KOhm /LK R0 R.KOhm /LK R.KOhm /LK R.KOhm /LK 0Ohm/00Mhz /LK L 0.UF/.V /LK R /LK/X R /LK/Rev R.KOhm /LK/Rev.KOhm /LK +V_LK_V +V_LK 0.UF/.V /LK FS FS FS PU PIE ST 0 0 0 T 00 LK_PI_IH LK_PI_E LK_REF_IH LK_M_US LK_M_REER LK_L LK_L# LK_PIE LK_PIE# S_SM_T S_SM_LK LK_PI_E 00 00 00 00 E E E E E E0 E E E E /X /X /X 0PF/V /X /X /X /X /X /X /LK/X /LK/X T N/ PEREQ:PIEx0 & PIEx PEREQ:PIEx & PIEx & ST PEREQ:PIEx & PIEx & PIEx [] O R o Not r00 Stuff /LK/Rev G S +V_LK R Q.KOhm /LK/Rev N00 /LK/Rev R.KOhm /LK/Rev +V_LK E Q O PMS0 /LK/Rev R 00Ohm % /LK/Rev LK_PEREQ# R0 KOhm /LK/Rev O [] /LK/Rev/X O Voltage Status [] LK_PI_E [,] LK_PI_IH [] LK_M_REER [] LK_M_US [] LK_REF_IH RN /LK Ohm RN /LK Ohm RN /LK Ohm RN /LK Ohm R Ohm /LK LK_FS LK_ITP_EN LK_SEL_# LK_FSL LK_FSL L L.~.V Performance H L 0V Power Saving H L H H 0V.~.V Power Saving Normal 00H SUSTek omputer IN. 00H lock ISLPRS aron Tsao ate: Friday, March, 00 Sheet of.g

SYS_RST# [] H_REQ#[:0] [] [] H_#[:] [] H_ST#0 H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_ST# [] H_0M# [] H_FERR# [] H_IGNNE# [] H_STPLK# [] H_INTR [] H_NMI [] H_SMI# T T +VP HR o Not Stuff r00 //X H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# P H0 N0 R0 J N G0 M H L0 M0 K J0 L K0 N J G P0 R F E 0 E0 0 M U T J R T R U G H K K M L +VP H_IERR# H_#[:0] [] H_INV#[:0] [] H_STN#[:0] [] H_STP#[:0] [] H_RS#[:0] [] SYS_RESET# [] RN00 KOHM / U []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# ST[0]# P0 REQ[0]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# ST[]# P 0M# FERR# IGNNE# STPLK# LINT0 LINT SMI# N N N N N N N FG_ / RN00 KOHM / RN00 KOHM / RN00 KOHM / HR Ohm / S# NR# PRI# EFER# RY# SY# R0# H_# H_# H_# H_IERR# T IERR# F INIT# V H_INIT# [] HR W0 KOhm / LOK# H_LOK# [] RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# PROHOT# THRM THRM THERMTRIP# LK[0] LK[] RSV RSV RSV H_# V Y U T T Y T0 W Y U0 W V0 K J H J K J M N M L K V G E E H V V H_PURST# H_RS#0 H_RS# H_RS# H_PM#0 H_PM# H_PM# H_PM# H_PM# H_PM# H_TK H_TI H_TO H_TMS H_TRST# SYS_RST# H_PROHOT# H_INV#[:0] [] H_STN#[:0] [] H_STP#[:0] [] H_RS#[:0] [] H_S# [] H_NR# [] H_PRI# [] H_EFER# [] H_RY# [] H_SY# [] H_R0# [] H_TRY# [] H_HIT# [] H_HITM# [] H_GTLREF H_PROHOT# H_THERM [] H_THERM [] H_THERMTRIP# [,] LK_LK_PU [] LK_LK_PU# [] +VP HR KOhm / HR KOhm % / +VP HR Ohm / H 0.UF/.V / H_PWR# EXTGREF H_LKPH H_LKPH +VP U H_#0 Y H_# [0]# W0 H_# []# Y H_# []# H_# []# H_# []# W H_# []# H_# []# Y0 H_# []# Y H_# []# Y H_#0 []# W H_# [0]# H_# []# Y H_# []# W H_# []# H_# []# W H_STN#0 []# Y H_STP#0 STN[0]# Y H_INV#0 STP[0]# W +VP INV[0]# V T P#0 H_# H_# []# Y HR H_# []# W H_# []# U //X H_#0 []# W H_# [0]# W H_# []# H_PURST# [,] Y H_# []# H H_# []# Y H_# []# W //X H_# []# V H_# []# U H_# []# T H_# []# H_#0 []# V H_# [0]# W H_STN# []# Y H_STP# STN[]# Y H_INV# STP[]# Y INV[]# R T P# H_GTLREF H_LKPH GTLREF U H_LKPH LKPH V T LKPH T T0 INIT# R EXTGREF EM M T EXTGTEF N T FOREPR# N T HFPLL P T MERR# T RSP# J T SEL[0] H T SEL[] G T SEL[] FG_ / SEL SEL SEL0 FS 0 0 0 00 0 0 HR0 HR o Not Stuff //X //X +VP HR KOhm / HR KOhm % / H0 0.UF/.V / T R KOhm / R //X r00 H H [] H_PWRG LK_LK_PU [] //X LK_LK_PU# [] //X +VP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# P# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# P# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# ORE_ET MREF HR //X r00 H_PWRG H //X R R P N M P J N G H N L M J H J K K L M G F E F E F T T F0 F R R U V N H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_STN# H_STP# H_INV# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_STN# H_STP# H_INV# H_OMP0 H_OMP H_OMP H_OMP H_PWRG PU_MREF T PM_PRSTP# [] H_PSLP# [] H_PWR# [] H_S# T T H_PM#0 H_PM# H_PM# H_PM# H_PM# H_PM# H_TK H_TI H_TO H_TMS H_TRST# [] LK_LK_ITP# [] LK_LK_ITP 00H SUSTek omputer IN. H_PM# H_TO H_TMS H_TI H_TK H_TRST# H_PUSLP# [] H_OMP0 H_OMP H_OMP H_OMP 00H ate: Friday, March, 00 Sheet of HR0 Ohm/ HR o Not //X Stuff HRN Ohm / HRN Ohm / HRN / Ohm HRN / Ohm HT N/ HT N/ HT N/ HT N/ HT N/ HT N/ HT N/ HT0 N/ HT N/ HT N/ HT N/ HT N/ HT N/ +VP PU_MREF +VP HR.Ohm % / HR0.Ohm % / HR.Ohm % / HR.Ohm % / TS N/ HR KOhm % / iamondville_us aron Tsao HR KOhm / H0 0.UF/.V /.G

0 m Friday, March, 00 SUSTek omputer IN. iamondville_pwr.g 00H aron Tsao 00H ate: Sheet of VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI0 [] VR_VI [] VR_VI [] VR_VI [] VR_VI [] VR_VI [] VR_VI [] VORE_V_SENSE [,] VORE_VSS_SENSE [,] +VORE +VP +VP +V +VORE +VP +VORE +VP +VORE +.V_PLL +V +Vccp +Vccp +Vccp +Vccp +.VS +Vccp +Vccp +Vccp +Vccp +Vccp +Vccp H 0.UF/.V / H UF/.V / H 0.UF/.V / + HE 00UF/.V / c 0UF/.V / H 0UF/.V //TOP H 0.UF/.V / H 0UF/.V //TOP H 0.UF/.V / HR 0Ohm / H 0.UF/.V / H 0.UF/.V / H0 0.UF/.V / T H 0UF/.V //TOP H 0.UF/.V / H 0.UF/.V / H 0UF/.V //TOP H 0.UF/.V / H UF/0V //TOP H 0UF/.V //TOP H 0.UF/.V / H 0.UF/.V / H 0.UF/.V / H 0.UF/.V / U FG_ / V0 0 0 0 0 E0 E E F0 F F G0 G G H0 H H J0 J J K0 K K L0 L L M0 M M N0 N N P0 P P R0 R R U U U U U0 U U T T R R P P N N M M L L K K J J H H G G F F E F F E E F E G G E G VF VQ0_ VQ0_ VP VP VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP VP VP VP VP0 VP VP VP VP VP VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VP VP VP VP V VI[0] VI[] VI[] VI[] VI[] VI[] VI[] V_SENSE VSS_SENSE + HE 00UF/.V / c U FG_ / 0 0 E E E E E E E F F F F F F G G G G G G H H H H H H H H J J J J J K K K K K K K L L L L L L L L L L M M M M M M N 0 0 Y Y0 Y Y W W W W W W W V V V V V V V V V U U U U U U T T T T T0 T T T T R R R R R R P P P P P P P P P P P N N N N N VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS H 0UF/.V //TOP H 0.UF/.V / H UF/0V //TOP H 0.UF/.V / H 0UF/.V //TOP H0 UF/.V / H 0.UF/.V / H 0UF/.V //TOP

[] H_#[:0] H_#[:] [] Power: +VP ROMP For alibrating the FS I/O uffer SOMP H_XROMP For Slew Rate ompenssation on the FS +VP Voltage Swing H_YROMP R.Ohm % H_YSOMP For Providing a Reference Voltage to The FS ROMP circuits +VP R.Ohm % R.Ohm % H_XSOMP R Ohm % R 00Ohm % H_XSWING 0 0.UF/.V +VP +VP R.Ohm % R 00Ohm % H_YSWING 0 0.UF/.V [] H_#[:0] H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_XROMP H_XSOMP H_XSWING H_YROMP H_YSOMP H_YSWING H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_VREF H_VREF H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_#[:] [] H_S# [] H_ST#0 [] H_ST# [] H_NR# [] H_PRI# [] H_R0# [] H_PURST# [,] LK_LK_MH# [] LK_LK_MH [] H_SY# [] H_EFER# [] H_INV#0 [] H_INV# [] H_INV# [] H_INV# [] H_PWR# [] H_RY# [] H_STN#0 [] H_STN# [] H_STN# [] H_STN# [] H_STP#0 [] H_STP# [] H_STP# [] H_STP# [] H_HIT# [] H_HITM# [] H_LOK# [] H_REQ#[:0] [] H_REQ#[:0] [] H_RS#0 [] H_RS# [] H_RS# [] H_PUSLP# [] H_TRY# [] H_VREF GTL+ I/O Voltage Reference +VP Layout Note: 0.uF should be placed 00mils or less from GMH pin. R Ohm % F H H F E K F J K H E K J J J N M K J H J N M M N N K N M V V R T R N N R U R T T R T V V W W V W W W V W 0 J K H U H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_XROMP H_XSOMP H_XSWING H_YROMP H_YSOMP H_YSWING HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ F E E J G F J E H G G E H E H G H_S# F0 H_ST#_0 H_ST#_ H H_VREF0 E H_NR# H_PRI# H_REQ0# G H_PURST# 0 H_VREF E HLKINN HLKINP H_SY# H_EFER# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_PWR# H_RY# H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_HIT# H_HITM# H_LOK# H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ H_SLPPU# H_TRY# 0 H J T U G E F M T F M T G E G F G0 E E0 0 0.UF/.V R0 00Ohm % R 00Ohm % GMS Signal voltage level = 0.*VP Trace should be 0 mil wide with 0 mil spacing /X /X LK_LK_MH# [] LK_LK_MH [] 00H SUSTeK OMPUTER IN. 00H N-GMS(HOST) aron Tsao ate: Friday, March, 00 Sheet of.g

+VP +VP LK +VS FS SEL SEL SEL0 R0 R0 L L L H H H [] PM_PRSLPVR 0KOhm 0KOhm R /N0 R KOhm /N0 r00 [,,,] PLT_RST# R PM_EXTTS#_ /X r00 R0 KOhm R /X [] MH_IH_SYN# [] PM_MUSY# MH_SEL0 MH_SEL MH_SEL MH_FG_ MH_FG_ MH_FG_ PM_EXTTS#_0 PM_EXTTS#_ [,] H_THERMTRIP# [,,] VRM_PWRG R 00Ohm % RST_IN_MH# [] LK_M_UM# [] LK_M_UM [] LK_L_LVS# [] LK_L_LVS R.KOhm R /X E G0 G J0 J H J W U FG_0 FG_ FG_ FG_ FG_ FG_ K RESERVE K RESERVE RESERVE F RESERVE RESERVE FG/RSV E IH_SYN# G PM_MUSY# F PM_EXTTS#_0 PM_EXTTS#_ THRMTRIP# PWROK RSTIN# PM LK _REFLKINN _REFLKINP J _REFSSLKINN H _REFSSLKINP J LKREQ# MI_RXN_0 MI_RXN_ MI_RXP_0 MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXP_0 MI_TXP_ MI R MUXING SM_K_0 SM_K_ SM_K_ SM_K_ SM_K#_0 SM_K#_ SM_K#_ SM_K#_ SM_KE_0 SM_KE_ SM_KE_ SM_KE_ SM_S#_0 SM_S#_ SM_S#_ SM_S#_ SM_OOMP_0 SM_OOMP_ SM_OT_0 SM_OT_ SM_OT_ SM_OT_ SM_ROMPN SM_ROMPP SM_VREF_0 SM_VREF_ Y Y Y Y V V V V F G J M0 G F K N0 N N F F G F K H J F E F J J N N E MI_RXN0 MI_RXN MI_RXP0 MI_RXP MI_TXN0 MI_TXN MI_TXP0 MI_TXP M_OOMP0 M_OOMP SM_ROMPN SM_ROMPP MLK_R0 [] MLK_R [] MLK_R0# [] MLK_R# [] MI_TXN[:0] [] MI_TXP[0..] [] MI_RXN[0..] [] MI_RXP[0..] [] M_KE0 [,] M_KE [,] M_S#0 [,] M_S# [,] R0 R0 M_OT0 [,] M_OT [,] R0 0.Ohm % R0 0.Ohm % M_VREF_MH /X /X +.V MI_TXN[:0] [] MI_TXP[0..] [] MI_RXN[0..] [] MI_RXP[0..] [] hecklist notes :an be left as N MH_LKREQ# is O pin GMS +.V [] LK_M_UM# [] LK_M_UM N N /X /X NR KOhm % M_VREF_MH NR KOhm N 0.UF/V N 0.UF/V 00H SUSTeK OMPUTER IN. 00H N-GMS(MI & FG) aron Tsao ate: Friday, March, 00 Sheet of.g

locse to GMH R0,R,R V0 /X R0 0Ohm IF USE N RE EI. MUST ONNET L LK&T [] L LK [] L T r 00KOhm V /X +VS R LKLT_EN LV_EN [0] RT_IREF RT_LUE [0] RT_GREEN [0] RT_RE [] [] LKLT_TRL LKLT_EN 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN r 00KOhm 0Ohm R Ohm % V /X R.KOhm R 0Ohm [] [] [] [] [] [0] [0] LV_EN L_LKN L_LKP [] L_TN0 [] L_TN [] L_TN [] L_TP0 [] L_TP [] L_TP LK_PIE_MH# LK_PIE_MH _LK _T N_VSYN N_HSYN RT_IREF LKLT_EN L_TL_LK L_TL_T LV_EN LVS_IREF H J Y H0 H E F F H H0 G F E G H K0 K J J0 K G F H G F F0 E F UF SVO_TRLT SVO_TRLLK G_LKINN G_LKINP MIS RT LK RT T RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT_VSYN RT_HSYN RT_IREF LVS VG L_KLTTL L_KLTEN L_LKTL L_TLT L LK L T L_VEN L_IG L_VG L_VREFH L_VREFL 0 L_LKN 0 L_LKP 0 L_LKN L_LKP L_TN_0 L_TN_ L_TN_ L_TP_0 L_TP_ L_TP_ L_TN_0 L_TN_ L_TN_ L_TP_0 L_TP_ L_TP_ SVO_TVLKIN# SVO_INT# SVO_FLSTLL# SVO_TVLKIN SVO_INT SVO_FLSTLL SVO EXP OMPI EXP IOMPO SVO_RE# SVO_GREEN# SVO_LUE# SVO_LKN TV OUT TV OUT TV OUT TV_IREF TV_IRTN TV_IRTN TV_IRTN TV SVO_RE SVO_GREEN SVO_LUE SVO_LKP TV_ONSEL0 TV_ONSEL R M N0 R0 T M0 P0 T0 P N P T N M P R 0 E0 G G J R N_EXP_OMP T T +.VS +.VS_PIE.Ohm % [0] [0] RT_HSYN RT_VSYN RT_HSYN RT_VSYN R0 Ohm R Ohm locse to GMH N_HSYN N_VSYN GMS 00H SUSTeK OMPUTER IN. 00H N-GMS(GRPHI) aron Tsao ate: Friday, March, 00 Sheet of.g

0 Friday, March, 00 SUSTeK OMPUTER IN. N-GMS(R).G 00H aron Tsao 00H ate: Sheet of M_M M_M M_Q M_Q M_Q M_Q S_RVENOUT# M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q0 M_M M_QS# M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_M M_Q0 M_Q0 M_Q M_Q M_Q M_Q0 M_Q M_Q M_QS# M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_M M_QS#0 M_Q M_Q M_Q M_M M_M M_M0 M_Q M_Q M_Q M_M M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_M M_Q M_Q M_Q M_Q S_RVENIN# M_M M_M M_M M_M M_M M_M0 M_M M_M M_QS M_QS M_QS M_QS0 M_QS M_QS M_QS M_QS M_QS# M_QS# M_QS# M_QS# M_QS# M_M M_M M_M M_M0 M_Q[:0] [] M_Q[:0] [] M_0 [,] M_ [,] M_ [,] M_QS[:0] [] M_M[:0] [] M_QS#[:0] [] M_M[:0] [,] M_S# [,] M_RS# [,] M_WE# [,] R SYSTEM MEMORY U GMS E F E H K L K H0 L J J H F H F J G G G N M J J L N H G M L H K M K M K G F F K F G J H N M K L M L J J G F E F H G G F G G G0 N0 L K K L H G F M E L0 E E E0 J K N M H J M M H K N J F N L G L G L K0 J M N J M E J0 K L N H M E 0 L F0 K L G K H K H G H J0 E S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ S_S# S_RS# S_WE# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_S# S_RS# S_RVENIN# S_RVENOUT# S_WE# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_S_0 S_S_ S_S_ S_S_0 S_S_ S_S_ N UG GMS W M L N N W V W J H W G F E K E N M L N Y J H G F E G F E N Y M F L K H G E M Y L Y W0 Y Y W 0 H K J Y W J Y0 W0 W V U V0 U0 K N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N0 N N N N N N N N N N N N N N N N N0 N N N N N N N N0 N N N N RESERVE RESERVE RESERVE RESERVE RESERVE0 RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE0 RESERVE N N N N N0 N N N RESERVE N N N N N N0 N N T T

t Package Edge t Edge Pin Location.0V~.V Max:. In avity FG_(K) Strapping : MI LNE Reversal: 0:Normal Operation (efault).:reversal Lanes, ->0,->..etc Note:GMS doesn't support MI Lane Reversal Friday, March, 00 SUSTeK OMPUTER IN. N-GMs(PWR).G 00H aron Tsao 00H ate: Sheet of +.VS +VP +.VS 0 0.UF/.V 0.UF/.V 0UF/.V c00 0 0.UF/.V 0.UF/.V 0UF/.V 0.UF/.V 0.UF/.V 0 UF/0V 0.UF/.V 0.UF/.V UF/0V 0 0.UF/.V UF/.V 0.UF/.V T /X c00 /X NTF UH GMS T R P N M P N M Y W V U T R P N M Y W V U T R P N M Y0 W0 V0 U0 T0 R0 P0 N0 M0 Y P N M Y P N M Y P N M Y P N M Y P N M Y 0 K Y W V U T R P N M Y W N V U 0 T0 R0 P0 N0 L0 W V U T R V U T R P N M 0 K0 P N M N M0 0 0 K K K R T K K K0 K K J K K K K K K V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF0 VSS_NTF VSS_NTF VSS_NTF VTT_NTF VTT_NTF VTT_NTF VTT_NTF VTT_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF V_NTF V_NTF V_NTF VTT_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF RESERVE RESERVE RESERVE RESERVE FG_ RESERVE0 RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE0 RESERVE RESERVE RESERVE RESERVE RESERVE

.V~.V Max: m..v~.v Max: 0m 0m.V~.V Max: 0m 0m.V~.V Max: 0m.V~.V Max: m 0. 0m. Friday, March, 00 SUSTeK OMPUTER IN. N-GMS(PWR).G 00H aron Tsao 00H ate: Sheet of +.VS_HPLL +.V_PLL +.V +.V +VS +.VS +.V_PLL +.VS_MPLL +.VS_MPLL +.VS +.VS_PLL +.VS_PIE +VP +.VS +.VS_PLL +.VS_HPLL +.VS_PLL +.VS_MPLL +VP +.V_PLL +.VS_RT +.VS +.V_PLL +.VS_RT +.VS_PIE +VP +.VS_GPLL +.V_PLL +.VS_GPLL +.VS_PLL +VP +.VS 0 0.UF/.V L 0Ohm/00Mhz 0.UF/.V 0 UF/0V 0.UF/.V 0.UF/.V UF/0V 0.UF/.V 0.UF/.V R KOhm % 0.UF/.V 0UF/.V UF/0V UF/0V 0.UF/.V 0 UF/0V 0.0UF/0V POWER U GMS T R P N M V U T W V T R E J J 0 P L P L P L P L G U P L G N M V U T M N M L K J H G F E N M L K J H G F E N N E F0 F E 0 0 W U R W V T R V U T 0 E E F E F E F E J J0 M L K J N M L K J H G F E N M0 L0 K0 H H0 G0 F0 E0 N U P M L G Y U P L G Y U L P G Y H0 E U U P L G F L K J H N0 J0 Y V0 V V V V V V V V V V0 V VHMPLL VHMPLL VPLL VPLL VHPLL VMPLL VRT0 VRT VSSRT VSYN VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VGG VSSGG VGPLL VG0 VG VTXLVS VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VHV0 VHV VHV VLVS VLVS0 VLVS VLVS VTV VQTV VTVG VSSTVG VTV0 VTV VTV0 VTV VTV0 VTV V V V V V V V V V0 V VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VTXLVS0 VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VTT VTT VSM VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VUX VUX VUX VUX VSSLVS VTT VTT VTT VTT VTT0 VSM VSM VSM VSM VSM0 VSM VTT 0.UF/.V 0UF/.V L uh 0.UF/.V 0UF/.V 0UF/.V 0 0.UF/.V 0.UF/.V 0.UF/.V 0.0UF/0V 0UF/.V 0.UF/.V 0 UF/.V 0.UF/.V UF/0V 0.UF/.V UF/0V TW 0.UF/.V 0.UF/.V L 0Ohm UF/0V L 0UH L 0UH 0.UF/.V L 0Ohm/00Mhz 0 UF/0V L 0NH UF/.V 0.UF/.V 0 0UF/.V 0 UF/0V 0UF/.V UF/0V 0UF/.V 0 0UF/.V UF/0V 0UF/.V 0.UF/.V UF/.V 0.UF/.V

Friday, March, 00 SUSTeK OMPUTER IN. N-PMS().G 00H aron Tsao 00H ate: Sheet of VSS UE GMS H Y V R K G E U H E M J U T R P N M J F L0 G0 E0 0 0 Y0 V0 U0 G0 E0 0 U R P N M H E K H E U T J M F Y U T R P N M G L W U N K J G H F J L G W R F M H E H F L G H N J E M W R M J F L G E U V R N H E L G E W T M K N J V R N K H E L W T G J K H F M K H F V R E H G E J F G M E J H F M0 F H M W 0 F0 K0 H0 R U H K V T F H U VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_00 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0

istribute in PI Section m 0 m 0. 0. 0m 0m Vcc =0. 0m m 0. 0m m R.G R.G R.G R.G.G change to +VS to follow R ustom Friday, March, 00 SUSTeK OMPUTER IN. S-IHM(PWR).G 00H aron Tsao 00H ate: Sheet of +.V_MIPLL +.V_STPLL +.V_USPLL +VS +VS +VSUS +VSUS +VREF +VREF_SUS +.VS +.VS +.VS +VSUS +VSUS +V_RT +VS +VS +VS +VS +.V_PLL +.VS_PIE_IH +VS +VS +.VS +VSUS +VP +VP +.VS +.V_PLL +.V_PLL +.VS +.V_PLL T 0UF/.V 0.UF/V 0.UF/.V 0 0.UF/.V ORE VPUX VGP IE PI US RX TX US ORE UF IHM G0 F E E E F F G G H H J J K K L L M M N N P P R R R R R T T T T T U U V V W W Y Y G E F G H E Y L L L L L L M M P P T T U U V V V V V V V V W W U R E E H 0 G G G 0 F G G G W P G K K K K L L L L L M M N T F G K G0 H H J J F H 0 0 0 E0 F0 F G H VREF_ VREF_ VREF_Sus Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc VccMIPLL Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc VccSus VccUSPLL VccSus_0/VccLN_0_ VccSus_0/VccLN_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_0 Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_0 VccSus_/VccLN VccSus_/VccLN VccSus_/VccLN VccSus_/VccLN Vcc_/VccH VccSus_/VccSusH V_PU_IO V_PU_IO V_PU_IO Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc VccRT VccSus VccSus VccSus VccSus VccSus VccSus VccSus VccSus VccSus VccSus 0 VccSus VccSus VccSus VccSus VccSus VccSus VccSus VccSus Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc VccSus_0_ VccSus_0_ VccSus_0_ Vcc Vcc Vcc Vcc Vcc 0 Vcc VccSTPLL Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0.UF/.V 0.UF/.V 0 UF/0V E UF/V 0 0.UF/.V 0 0.UF/.V 0.UF/.V 0 0.UF/.V E UF/V T 0.UF/.V 0.UF/.V TW /PLL 0 0.UF/.V 0UF/.V 0.UF/.V UF/0V 0.UF/.V 0 0UF/.V L 0Ohm/00Mhz 0UF/.V 0.UF/.V 00 0.UF/.V T 0.UF/.V 0 0.UF/.V 0UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V R Ohm /PLL R0 0Ohm /PLL 0.UF/.V T 0.UF/.V 0.UF/V 0.UF/.V UF/0V 0.UF/.V 0 0UF/.V E UF/V 0 TW E UF/V T R0 0Ohm /PLL 0.UF/.V 0.UF/.V UE IHM 0 0 E E E E E F F F F F F G G G G G G G G G G G H H H H H H J J J J J J K K K L L L L L M M M M M M M M M M M M N N N N N N N N N N N N N N N P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U U V V V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F G G G G G G G0 G H H H H H H Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss00 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss 0.UF/.V R 00Ohm 0.0UF/0V 0.UF/.V L 0Ohm/00Mhz TW 0.UF/.V L 0Ohm/00Mhz R 0Ohm

hange to rechargeable RT battery +V_T_R PT N/ +V_E 0UF/.V 0.UF/.V R.G change +V net to +V_E Height:. mm +V_E TWS +RTT R.KOhm T SIE SIE WTO_ON_P R 0Ohm +V_RT SR 0KOhm RTRST# R 0 delay UF/0V ~ms PT S UF/0V LRT /X Place Near Open oor RTRST# [] PF/0V 0 X_RT R0 0MOhm X_RT 0 PF/0V X SIE.Khz ME/MSV-TR.KHZ./0 [,] _Z_ITLK [] _Z_SYN [] _Z_RST# [] _Z_SOUT Ohm Ohm Ohm Ohm RN RN RN0 RN0 0 /X Z_LK Z_SYN Z_RST# Z_SOUT +VS +V_RT [] S_STLE# [] P_ST_RXN0 [] P_ST_RXP0 [] P_ST_TXN0 [] P_ST_TXP0 R R 0KOhm 0KOhm Z_SIN0 Z_SIN R R 0KOhm % OE N [] _Z_SIN0 T T [] LK_ST_IH# [] LK_ST_IH MOhm X_RT X_RT RTRST# Z_LK Z_SYN Z_RST# Z_SIN P_ST_RXN0 P_ST_RXP0 P_ST_TXN0 P_ST_TXP0 Z_SOUT STRIS/# R.Ohm % R /X r00 IE_IRQ IE_IORY Y W W Y Y W V U U V T U V V U R R T T T T F F E G H F E G H F E H0 G0 F H F H G E U RTX RTX RTRST# INTRUER# INTVRMEN EE_S EE_SHLK EE_OUT EE_IN LN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX Z_LK Z_SYN Z_RST# Z_SIN0 Z_SIN Z_SIN Z_SOUT STLE# ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRISN STRISP IOR# IOW# K# IEIRQ IORY REQ IHM RT LN -/ZLI ST IE PU LP L0 L L L LRQ0# LRQ#/GPIO LFRME# 0GTE 0M# PUSLP# TP/PRSTP# TP/PSLP# FERR# GPIO/PUPWRG Y E H G F H G G LP_RQ#0 LP_RQ# 0GTE IGNNE# G G T INIT_V# INIT# F INTR F G R_IN# RIN# NMI SMI# STPLK# THERMTRIP# 0 0 0 S# S# H F H F E G F E F F H H H E F E R.Ohm % LP_0 [,] LP_ [,] LP_ [,] LP_ [,] T T0 LP_FRME# [,] 0GTE [] PM_PRSTP# [] H_PSLP# [] H_PWRG [] H_INIT# [] H_INTR [] R_IN# [] H_NMI [] H_SMI# [] H_STPLK# [] +VP R Ohm H_THERMTRIP# [,] NO STUFF R0.PUSLP# ONLY USE IN ESTOP H_0M# [] +VP H_IGNNE# [] R Ohm 0GTE R_IN# H_INIT# H_FERR# [] R 0KOhm +VP +VS R0 0Ohm R 0KOhm [] LK_ST_IH# S /X [] LK_ST_IH S /X 00H SUSTeK OMPUTER IN. S-IH-M() aron Tsao ustom 00H ate: Friday, March, 00 Sheet of.g

+VS +VS WLN_ON [] LK_PIE_WiMax [] LK_PIE_WiMax# LN R I WIFI PIExpress ard PIE Interface for Wimax 00-0- US_O#0 US_O# US_O# US_O# US_O# WQ /G G S WLN_ON# [] [] LK_PIE_WiMax [] LK_PIE_WiMax# SR 0KOhm RN 0KOhm SRN 0KOhm RN 0KOhm SRN 0KOhm PIE_RXN PIE_RXP PIE_TXP PIE_TXN WLN_ON PLT_RST# [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP +VSUS +VS /WIFI/X /WIFI/X 0 WIFI_ON 0 SIE SIE /G PIE_RXN PIE_RXP 0.UF/V PIE_TXN 0.UF/V PIE_TXP [] US_O# [] US_O# 0.UF/V 0.UF/V 0.UF/V 0.UF/V T T T T T PI_INT# PI_INT# PI_INT# PI_INT# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ US_O#0 US_O# US_O# US_O# US_O# E F E E E G G E 0 F F0 E E E G H F F E E H H G G K K J J M M L L P P N N T T R R U IHM R P P P P E 0 0 0 0 PIRQ# PIRQ# PIRQ# PIRQ# RSV_ RSV_ RSV_ RSV_ RSV_ U PI Interrupt I/F PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp SPI_LK SPI_S# SPI_R SPI_MOSI SPI_MISO O0# O# O# O# O# O#/GPIO O#/GPIO0 O#/GPIO IHM PI-Express SPI MIS US irect Media Interface REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# REQ#/GPIO GNT#/GPIO GPIO/REQ# GPIO/GNT# /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# GPIO/PIRQE# GPIO/PIRQF# GPIO/PIRQG# GPIO/PIRQH# RSV_ RSV_ RSV_ RSV_ MH_SYN# MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS E E F E0 E 0 F F F G F F G E G H F H0 V V U U Y Y W W E E F F G G H H J J K K L L M M N N MI_OMP USRIS/# PI_REQ#0 PI_REQ# PI_REQ# PI_REQ# T PI_REQ# PI_REQ# PI_IRY# PI_PR PI_EVSEL# PI_PERR# PI_LOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# PLT_RST# PI_INTE# PI_INTF# PI_INTG# PI_INTH# PI_RST# [] PME# internal PU 0KOhm PI_PME# LK_PI_IH [,] T MH_IH_SYN# [] MI_TXN0 [] MI_TXP0 [] MI_RXN0 [] MI_RXP0 [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] LK_PIE_IH# [] LK_PIE_IH [] R.Ohm % T US_PN [] US_PP [] US_PN [] US_PP [] US_PN [] US_PP [] US_PN [] US_PP [] US_PN [] US_PP [] US_PN [] US_PP [] R.Ohm % R & hecklist US 0 US US US US US US US PI_GNT# PI_GNT# +.VS_PIE_IH US onn US onn N N ard Reader WIFI luetooth amera LK_PI_IH R KOhm r00 R R /X /X r00 r00 R 00KOhm /X R KOhm r00 PI_INT# PI_REQ# PI_LOK# PI_EVSEL# PI_INTE# PI_INTH# PI_SERR# PI_PERR# PI_INT# PI_INT# PI_INTF# PI_INT# PI_REQ# PI_REQ#0 PI_INTG# PI_IRY# PI_FRME# PI_STOP# PI_REQ# PI_REQ# PI_TRY# PI_REQ# 00H ustom IH oot IOS Select LP PI SPI PLT_RST# [,,,] RP RPH RP RPG RPH RP RPE RPF RP RP RP RPF RPG RPH RP RPE RPF RPE RP RP RPG RP RP RP SUSTeK OMPUTER IN. GNT# H H L.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM.KOHM 00H GNT# H L H uffer to Reduce Loading on PLT_RST#.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0 0 0 0 0 0 0 0 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0 +VS S-IHM() aron Tsao ate: Friday, March, 00 Sheet of.g

+VS 0//0, refer ZJ R.0 to delete and change net name from VRMPWRG to VRM_PWRG. S_SM_LK S_SM_T [] SYS_RESET# R 0KOhm STP_PI# STP_PU# [] R_REER_EN# Isolate alert# signal from thermal I [] THRM_LERT# [,,] VRM_PWRG S_SM_LK [] S_SM_T [] R 0KOhm T [] PM_MUSY# [] STP_PI# [] STP_PU# [,] PIE_WKE# [] INT_SERIRQ R0 /X r00 R 0Ohm [] Wireless_LE [] EXTSMI# S_SM_LK S_SM_T LINKLERT# SM_LINK0 SM_LINK RING# S_SPKR T SUS_STT# N/ SM_LERT# R_REER_EN# MOEM_EN PM_LKRUN# P_I P_I THRM_LERT#_S VRM_PG 0 F E G U F0 H F0 E U SMLK SMT LINKLERT# SMLINK0 SMLINK RI# SPKR SUS_STT# SYS_RST# GPIO0/M_USY# SMLERT#/GPIO GPIO/STPPI# GPIO0/STPPU# GPIO GPIO GPIO GPIO/LKRUN# IHM WLN_LE WLN T High v SM GPIO/Z_OK_EN# GPIO/Z_OK_RST# WKE# SERIRQ THRM# VRMPWRG GPIO GPIO GPIO SYS GPIO Power MGT locks ST GPIO GPIO v GPIO/ST0GP GPIO/STGP GPIO/STGP GPIO/STGP LK LK SUSLK SLP_S# SLP_S# SLP_S# PWROK GPIO/PRSLPVR TP0/TLOW# PWRTN# LN_RST# RSMRST# GPIO GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO F H H E 0 F Y E0 0 F E R E R 0 0 E0 GPIO GPIO GPIO P_I0 SUSLK ST_ET#0 GPIO GLN_OFF _S# MINIR_EN# GPIO GPIO N/ SIMR_IN# [] PM_PRSLPVR [] WLN_ON# [] K_SI# [] GPIO Internal PU 0K For +.V IMM Power +VSUS T0 N/ T PM_PWROK [,] PM_TLOW# [] PM_PWRTN# [] PLT_RST# [,,,] PM_RSMRST# [,] LK_REF_IH [] LK_M_US [] PM_SUS# [] PM_SUS# [] Int P.U GLN_OFF +.V_SEL# [] MER_EN [] R GLN_OFF R WLN_ON# o Not /G Stuff 0Ohm /WIFI or /G/X GPIO +VS R SR 0KOhm 0Ohm GPIO WLN_ON#_G_OFF [] S /X Q /X G S T_IS# [] THRO_PU [] +VSUS High High Low v x x x v x R0 0KOhm R 0KOhm RING# SYS_RESET# [] GLN_OFF MINIR_EN# WLN_ON# MOEM_EN RN 0KOhm 0KOhm RN SRN 0KOhm 0KOhm SRN Q +VSUS +VS P_I[:0] 000: R.0 P_I P_I P_I0 +VS R 0KOhm R0 0KOhm R 0KOhm R.0 for EST "" S_SM_LK +VS S_SM_T UMKN Q UMKN VRM_PWRG SM_LK [,] SM_T [,] N/ T SM_LK SM_T R_REER_EN# SM_LERT# RN SRN 0KOhm SM_LINK0 0KOhm RN 0KOhm SM_LINK RN 0KOhm ST_ET#0 PM_TLOW# _S# LINKLERT# RN.KOhm RN.KOhm RN.KOhm RN.KOhm RN 0KOhm RN 0KOhm SRN 0KOhm RN 0KOhm S_SM_LK S_SM_T +VSUS +VSUS +VSUS MER_EN PIE_WKE# THRM_LERT#_S INT_SERIRQ PM_LKRUN# VRM_PWRG GPIO GPIO GPIO GPIO PM_PWROK R 0KOhm R 0KOhm R +VS +VSUS Energy Star RN 0KOhm RN 0KOhm RN0 0KOhm RN 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN 0KOhm MOhm +VS R R R /X r00 /X r00 /X r00 P_VI : PROJET OE S_SPKR SR /X [] L_EN K_SI# EXTSMI# GPIO RN 0KOhm SRN 0KOhm SRN 0KOhm RN 0KOhm GPIO R /X r00 00H ustom PM_RSMRST# R0 MOhm R.G SUSTeK OMPUTER IN 00H S-IHM() aron Tsao ate: Friday, March, 00 Sheet of.g

ST Type GROUP GROUP SWP R onn. Height=.0mm R.G M M change to 00 uf Friday, March, 00 SUSTek omputer IN. R SOIMM.G 00H aron Tsao 00H ate: Sheet of M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_M M_M M_M0 M_M M_M M_ M_0 M_ M_M0 M_M M_M M_M M_M M_M M_M M_M M_QS0 M_QS M_QS M_QS M_QS M_QS M_QS M_QS M_QS#0 M_QS# M_QS# M_QS# M_QS# M_QS# M_QS# M_QS# M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q M_Q0 M_Q M_Q M_Q SM_T SM_LK R_VREF R_VREF SM_LK [,] SM_T [,] M_OT [,] M_OT0 [,] M_S#0 [,] M_S# [,] MLK_R0 [] MLK_R0# [] MLK_R [] MLK_R# [] M_KE0 [,] M_KE [,] M_S# [0,] M_RS# [0,] M_WE# [0,] M_Q[:0] [0] M_QS[:0] [0] M_QS#[:0] [0] M_M[:0] [0] M_M[:0] [0,] M_[:0] [0,] +.V +VS +.V +.V +.V +VS MR KOhm /IMM M 0.UF/.V /IMM M0 0.UF/.V /IMM MR KOhm /IMM M UF/.V /IMM IMM R_IMM_00P /IMM 0 0 00 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0/P 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q M /IMM/X IMM R_IMM_00P /IMM 0 0 0 0 0 0 0 0 0 0 0 0 V V V V V V V V V V0 V V VSP N N N N NTEST VREF 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS NP_N NP_N M UF/.V /IMM M0 0UF/.V /IMM M /IMM/X M 0.UF/.V /IMM

M_M[:0] [0,] M_[:0] [0,] +VTT_R [0,] [0,] [0,] [,] [,] [,] [,] [,] [,] M_S# M_RS# M_WE# M_S#0 M_OT0 M_KE0 M_KE M_S# M_OT M_M0 M_M M_M M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_0 M_ M_ MRN OHM MRN OHM /IMM MRN OHM /IMM M 0.UF/.V /IMM MRN OHM /IMM MRN OHM M 0.UF/.V /IMM /IMM MRNF OHM /IMM MRNH OHM /IMM MRNG OHM /IMM 0 /IMM MRNG OHM 0 MRNH OHM /IMM MRN OHM /IMM MRNF OHM M 0.UF/.V /IMM /IMM MRN OHM /IMM M 0.UF/.V /IMM MRNF OHM /IMM MRN OHM /IMM MRN OHM /IMM /IMM MRN OHM MRN M0 0.UF/.V /IMM OHM /IMM MRNE M 0.UF/.V /IMM OHM /IMM MRN OHM /IMM M 0.UF/.V /IMM MRNH OHM /IMM MRNG OHM /IMM 0 MRNE OHM /IMM MRNE OHM /IMM /IMM MRN Ohm M 0.UF/.V /IMM MRN /IMM Ohm MRN /IMM Ohm MRN /IMM Ohm /IMM 00H SUSTek omputer IN. 00H R_Termination aron Tsao ate: Friday, March, 00 Sheet of.g

[] RT_RE [] RT_GREEN [] RT_LUE VR 0Ohm % /VG VR 0Ohm % /VG VL 0.0uH /VG.PF/0V /VG VL 0.0uH /VG.PF/0V /VG RT_RE_ON.PF/0V /VG RT_GREEN_ON.PF/0V /VG RT_LUE_ON 0.PF/0V /VG +V_RT +VS +VS VR 0Ohm r00_h 0.UF/V /VG /VG VRN.KOhm /VG VRN.KOhm /VG +V_RT_R _T _LK F./V /VG +V_RT_F 0 FSJTP /VG +V_RT +VS VRN.KOhm /VG _T_ON /VG/X RT_HSYN_LS RT_HSYN_ON +V_RT RT_VSYN_LS PF/0V /VG RT_VSYN_ON PF/0V /VG for E measurement +VS /VG 0.UF/.V +VS +VS VR /VG/X +VS VR 0Ohm /VG V_SYN _LK_ON RT_VSYN_ON RT_HSYN_ON _T_ON MINI_VG 0 0 NP_N P_ P_ 0 P_ NP_N P_ P_ P_ OKING_ON_P /VG RT_RE_ON RT_GREEN_ON RT_LUE_ON +V_RT _LK_ON /VG/X +VS RT_RE RT_GREEN RT_LUE V_SYN PV00 /VG/X RT_HSYN [] RT_VSYN_LS RT_VSYN [] _T_ON _LK_ON RT_HSYN_LS _T [] _LK [] VRN.KOhm /VG VR0 0Ohm % /VG VL 0.0uH /VG.PF/0V /VG /VG/X VU V_SYN V_VIEO VIEO_ VIEO_ VIEO_ V_ YP IPZ /VG SYN_OUT SYN_IN SYN_OUT SYN_IN _OUT _IN _IN _OUT 0 00H Onboard VG SUSTek omputer IN. aron Tsao 00H.G ate: Friday, March, 00 Sheet 0 of

[] L_EN [] LKLT_EN L_EN [] L T [] L LK [] L_KOFF# L LK L T L_LKP L_LKN TW /LVS L_TP L_TN L_TP L_TN L_TP0 L_TN0 [] LV_EN L_EN [] [] [] [] [] [] [] [] VR0 0KOhm /LVS E 0PF/V /LVS E 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS V 0PF/V /LVS [] VR LKLT_TRL L_LKP L_LKN L_TP L_TN L_TP L_TN L_TP0 L_TN0 +VS +VS L_EN 0Ohm /LVS LV_EN_R E LVS_ON 0 0 0 0 0 0 /LVS/X WTO_ON_0P /LVS SIE SIE SIE SIE SIE +VS UF/0V /LVS R.G L_EN E /X LV_EN_R [] [] [] [] [] [] [] LKLT_TRL L_LKP L_LKN L_TP L_TN L_TP L_TN [] L_TP0 [] L_TN0 [] L T [] L LK E0 /X +VS L_EN LV_EN_R +VS 0 0 0 LVS_ON 0 0 0 /LVS/X SIE NP_N SIE SIE SIE SIE SIE NP_N SIE +V LI# /LVS/X +V VR /LVS/X r00 V /LVS/X LI_E# [] 0UF/.V /LVS +V 0 0.UF/.V /LVS LI_E# U V Output E--F /LVS hange to 0G0000 for cost issue 00H SUSTek omputer IN. 00H LVS onn_li aron Tsao ate: Friday, March, 00 Sheet of.g LI_E#

00H SUSTek omputer IN..G Module & External ntenna aron Tsao 00H ate: Friday, March, 00 Sheet of.g

M_PIE_WKE# T_PRIORITY H_T [] LK_PIE_MINIR# [] LK_PIE_MINIR [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP M_PIE_WKE# [] LK_PIE_MINIR# [] LK_PIE_MINIR +.VS m WR00 /G W 0UF/.V c00 /WIFI +VSUS PQ UMKN /WIFI +VS_G_R WR /G W 0.UF/.V /WIFI WR /G PIE_WKE# [,] W 0.UF/.V /WIFI W W MINIR use G0000K,H=mm WLN_ON_G_OFF# +VSUS 0 m MINIR WKE# Reserved Reserved LKREQ# REFLK- REFLK+ Reserved/UIM_ Reserved/UIM_W_ISLE# PERST# PERn0 +.Vaux PERp0.V_ SM_LK PETn0 SM_T PETp0 0 US_- Reserved US_+ Reserved Reserved LE_WWN# Reserved LE_WLN# Reserved LE_WPN# Reserved.V_ Reserved Reserved0.V_ MINI_PI_LTH_P /WIFI W UF/0V /WIFI WQ N00 /WIFI /WIFI/X /WIFI/X.V_.V_ UIM_PWR UIM_T UIM_LK UIM_RESET UIM_VPP NP_N NP_N G S TN/ 0 0 0 0 0 +VS_G_R +.VS +VSUS WLN_ON#_G_OFF [] USIM_PWR USIM_T USIM_LK USIM_RESET WLN_ON_G_OFF# MSM_LK MSM_T USPN USPP LE_GLN# LE_WLN# G_PWR_SEL WR 0Ohm /WIFI [] [] +VS_G +VS_G_R US_PP US_PN +VS G_PWR_SEL [0] PLT_RST# [,,,] T o N/Not Stuff T N/ WR /G WR 0Ohm /WIFI r00_h +VS_G_R +VS_G_R [,,,] PLT_RST# H for ttena WR WR WR /G r00 /G r00 0Ohm /WIFI 0OHM WRN /WIFI WR 0Ohm /WIFI WL /WIFI/X 0OHM WRN /WIFI USPP USPN USIM_PWR SM_LK [,] SM_T [,] W0 /WIFI/X 00-0-0 USIM_RESET USIM_LK USIM_T luetooth [] T_IS# W00 c00 /G/X P Near SIM Socket USIM_PWR USP USN T_PRIORITY H_T W /G W /G W /G W /G +VS MINI R NUT(.mm) * H Reserve H H for Factory ug +VS WR /T/X r00 0 /WIFI WR /G T LT_ON 0 WTO_ON_P G000 /T H USIM_PWR [] USIM_RESET [] USIM_LK [] USIM_T [] 0 /WIFI SIMR_IN# [,] W UF/0V /WIFI +VS_G_R 0 m W0 0UF/.V c00 /WIFI W UF/0V /WIFI W 0.UF/.V /WIFI W c00 /WIFI/X [] [] US_PN US_PP 0OHM WRN /T WL /T/X 0OHM WRN /T USN USP R.G T on. change to pin connector 00H SUSTek omputer IN. 00H -Mini WiFi + G + T ate: Friday, March, 00 Sheet of Minicard aron Tsao.G

00H SUSTek omputer IN 00H R aron Tsao ate: Friday, March, 00 Sheet of.g

00H SUSTek omputer IN. 00H RJ aron Tsao ate: Friday, March, 00 Sheet of.g

E E Naming Rule: I:IU? R:IR? :I? L:IL? 00H SUSTek omputer IN. 00H G-Sensor aron Tsao ate: Friday, March, 00 Sheet of.g

+VSUS +V_US +V_US_ON F L0./V /US [] US_O# 0Ohm/00Mhz /US R KOHM /US Energy Star.G change US con. to G000 [] US_PN [] US_PP 0OHM RN0 /US L /US/X 0OHM RN0 /US USPN USPP USPN I/O 0 R KOhm /US I/O V +V_US_ON +V_US_ON + E 00UF/.V /US c c00 /US/X 0.UF/V /US USPN USPP change from IP to SM.G change E E E to POSP, 00uF/.V US P_ P_ US_ON_XP /US USPP I/O I/O /US/X USPN.PF/0V /US USPP.PF/0V /US 00H SUSTek omputer IN. 00H US Port aron Tsao ate: Friday, March, 00 Sheet of.g

00H SUSTek omputer IN. 00H amera Power aron Tsao ate: Friday, March, 00 Sheet of.g

00H SUSTek omputer Inc. 00H U- aron Tsao.G ate: Friday, March, 00 Sheet of

00H SUSTek omputer Inc. 00H L- aron Tsao.G ate: Friday, March, 00 Sheet 0 of

.G add PWR LE and harge LE MI able length should be less 0cm hange R R R to 0 Ohm 00H SUSTek omputer Inc. 00H L- aron Tsao.G ate: Friday, March, 00 Sheet of

+V O 0UF/.V /E O 0.UF/.V /E O 0.UF/.V /E O 0.UF/.V /E +V OL 0Ohm/00Mhz /E +V_E O 0.UF/.V /E +V O 0.UF/.V /E OR 00KOhm /E [] FORE_OFF# O UF/0V /E OU OUT V N RNV-TR-F /E +V E_RST# O0 0.UF/.V /E SM_LK SM_T OR.KOhm /E OR.KOhm /E +V +V [] INT_SERIRQ [,] LP_FRME# [] LK_PI_E [] HRGE0_LE# [] [] [] [] R_IN# K_SI# 0GTE PI_RST# LP_[:0] [,] LP_0 LP_ LP_ LP_ E_RST# 0 0 OU SERIRQ LFRME# PILK GPIO/LKRUN# L0 L L L GPIO0/KRST# GPIO0E/SI# GPIO00/G0 GPIO0/PIRST# ERST# LP I/F V V V V V V V V/ V +V +V_E LP_FRME# E0 /E/X T N/ _OK SM_LK SM_T TP_LK TP_T T_IN _OK PM_SUS# PM_SUS# ORN 0KOhm ORN 0KOhm /E ORN 0KOhm /E ORN 0KOhm /E /E ORN 00KOhm ORN 00KOhm /E ORN 00KOhm /E ORN 00KOhm /E /E +V +V [] [] [] aps_le# KSO[:0] KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO OT N_KSO OT N/ N_KSO N/ KSI0 KSI KSI KSI KSI KSI KSI KSI[:0] KSI OT0 NUM_LE# N/ aps_le OT SRL_LE# N/ OT OT N/ OT N/ OT N/ N/ [] TP_LK [] TP_T L_SL L_S L_S L_VSYN K0QF /E PS I/F OR.G For Hotkey debounce HOTKEY_SW0# - HOTKEY_SW# internal PU 0 0 0 GPIO0/KSO0/TP_TEST GPIO/KSO/TP_PLL GPIO/KSO GPIO/KSO/TP_ISP GPIO/KSO GPIO/KSO GPIO/KSO Key Matrix GPIO/KSO Scan GPIO/KSO GPIO/KSO GPIO/KSO0 GPIO/KSO GPIO/KSO GPIO/KSO GPIOE/KSO GPIOF/KSO/E_RX(ISP) GPIO/KSO GPIO/KSO GPIO0/KSI0/E_TX(ISP) GPIO/KSI GPIO/KSI GPIO/KSI GPIO/KSI GPIO/KSI GPIO/KSI GPIO/KSI GPIO/NUMLE# LE GPIO/ETMR/PSLE# GPIO/EINT0/SRLE# GPIO/PSLK/P0_LK GPIO/PST/P0_T GPIO/PSLK GPIO/PST GPIOE/PSLK GPIOF/PST GPI/0 GPI/ GPI/ GPI/ GPO GPIO0F/PWM0 PWM GPIO0/PWM / GPIO/PWM FN GPIO/PWM GPIO/FNPWM GPIO/FNPWM GPIO/FNF GPIO/FNF GPO GPO GPOE GPOF GPXIO00/SIS# GPXIO0/SILK GPXIO0/SIO XIOGPXIO0 GPXIO0 GPXIO0 GPXIO0 GPXIO0 GPXIO0 GPXIO0 GPXIO0 GPXIO GPXIO0/SII GPXIO GPXIO XIO GPXIO 0 00 0 0 0 0 0 0 GPXIO SM_LK GPXIO [,] SM_LK SM_T GPIO/SL GPXIO [,] SM_T GPIO/S SM US GPXIO [] SM_LK GPIO/SL [] SM_T 0 GPIO/S Thermal Sensor HSW0# SPI R#/SPII GPIO0 WR#/SPIO 0 [] TP_EN# I/F GPIO0/GPWU GPIO/SPILK [] EXTSMI# GPIO0 SELMEM#/SPIS# [] LI_E# N_GPIO0 GPIO0/GPWU OT OT N_GPIO0 GPIO0/ES_LK N/ HOTKEY_SW# GPIO0/ES_T N/ 0 OT GPIO0 GPIO URT GPIO/E_TX [] PWR_SW_E# N/ GPIO GPIO/E_RX [] _OK GPIO0 [] E_RSMRST# GPIO GPIO/SPILKI/TEST_LK [] T_IN GPI GPI GPIO0/SELIO# XLK XLKI HRGE_LE# XLKO [] HRGE_LE# 0 GPIO/ES# [,] PWR_LE_UP HOTKEY_SW# GPIO/ETMR0/WT_LE# OT0 INTERNET# GPIO/EINT VR N/ GPIO/XLKK OT N/ 0 0 0 0 T_IHG T_ONFIG T_SENSE L_PWM_ MIL_LE# PM_PWRTN# [] OT FN_PWM N/ OT FN0_PWM [] FN_TH N/ FN0_TH [] OT L_KOFF# N/ O [] SPI_MOE# VSUS_ON_R T_LERN N_GPXIO SPI_LK_R E_TX E_RX N_GPIO K_XLKI K_XLKO K_VR PM_TLOW# [] O [] OT N/ OR 0Ohm /E SUS_ON [,0] PU_VRON [,] SUS_ON [,,,0] E_PWROK [] PM_LEVELOWN# [,,,,] HG_EN# [] PS-ON [] SPI_WP# [] OP_S# [] T_LERN [] OT o N/Not Stuff OT o N/Not Stuff OT N/ THRO_PU [] PM_SUS# [] PM_SUS# [] VRM_PWRG [,,] VSUS_PWRG [,] OR 0Ohm /E SPI_O [] SPI_I [] SPI_LK [] SPI_S# [] O T /E/X N/T N/ OT N/ O UF/0V /E OT N/ OT N/ L_KOFF# [] VSUS_ON [] SPI_I SPI_S#.G For Hotkey debounce [] HOTKEY_SW0# TP_EN# OR 0KOhm /E O O0 /RF/X /RF/X OR Ohm /E Energy Star +V 00H SUSTek omputer IN. HSW0# PM_LEVELOWN# E_RST# PI_RST# SPI_MOE# O /E/X O OR 00H OR 00KOhm /E OT N/ OR /E/X OR0KOhm /E /E/X.KOhm /E OR0 E_ENE K0 aron Tsao ate: Friday, March, 00 Sheet of K_XLKI PF/0V /EO OX.Khz /E +V +V /E/X K_XLKO PF/0V O /E.G

+VSUS [,] VSUS_PWRG [] E_RSMRST# O TW /E OR 0KOhm /E PM_RSMRST# [,] +VS OR 0KOhm /E [,] VSUS_PWRG [] E_PWROK O TW /E PM_PWROK [,] 00H SUSTek omputer IN. 00H E ate: Friday, March, 00 Sheet of aron Tsao.G

+V For ebug R /SW/X PWRTN# T N/ for TS PWRTN# [] R Ohm /SW +V R /SW/X PT0 N/ PWR_SW# [] LP_[:0] [,] LP_0 [,] LP_0 LP_ [,] LP_ LP_ [,] LP_ LP_ [,] LP_ [,] LP_FRME# [,] LK_PI_IH +VS 0 EUG_ON SIE 0 SIE /ebug +VS /EUG/X prevent system power on when L close /SW/X ebug ard cable use Z Touch Pad cable, P/N: G0, G00, G0 G0, G0 TP_EN# [] HOTKEY_SW0# [] SW NP_N NP_N SW_P /SW _JK_IN IN_ IN _PWR P_ P_ P_ P_ NP_N T T IN_ L 0Ohm/00Mhz / /_OK_IN SPI_WP# SPI_HOL# +V R 0KOhm /SPI R 0KOhm /SPI +V SPI_O 0.UF/0V /SPI /RF/X +V [] [] [] SPI_S# SPI_O SPI_WP# SPI_HOL# SPI_LK [] SPI_I [] 00H SUSTek omputer IN. 00H _Switch_SPI _ITP_ebug aron Tsao ate: Friday, March, 00 Sheet of.g /X SW NP_N NP_N /X SW_P /SW L 0Ohm/00Mhz / 0.UF/V c00 / _POWER_JK_P / change from IP to SM 0 0 0UF/V PSMJ0 c0_h / / UF/V / 0.UF/V c00 / U E# V SO HOL# WP# SK SI SSTVF00 /SPI

SM_LK SM_T /Thermal/X /Thermal/X +V_THRM +VS R 0Ohm /Thermal 0.UF/.V /Thermal [] SM_LK [] SM_T [] THRM_LERT# U SLK ST LERT# S00EP /Thermal V + - T_RIT# +V_THRM PM_THERM# H_THERM [] H_THERM [] H_THERM H_THERM 000PF/0V /Thermal +V_THRM +VS U use 0G0000, second source 0G0000 R PM_THERM# /Thermal/X FORE_OFF# [] R o Not r00 Stuff /Thermal/X +VS +VS [] FN0_TH R.KOhm % /FN RN.KOhm /FN RN.KOhm /FN FN_TH /FN/X +VS FN SIE SIE Wto_ON_P /FN 0 0UF/.V c00 /FN 0.UF/V /FN +V +VS hange to G000(The sam as other EP) [] FN0_PWM RN.KOhm /FN RN.KOhm /FN Q PMS0 E /FN FN_PWM /FN/X 00H SUSTek omputer IN. 00H Thermal Sensor_FN aron Tsao ate: Friday, March, 00 Sheet of.g

+VS L 0Ohm/00Mhz /TP +V_TP 0.UF/V /TP For Touch-Pad For Keyboard onnector KSO[:0] [] KSI[:0] [] K /X KSO [] TP_LK [] TP_T TP_T TP_LK [] USIM_PWR [] USIM_RESET [] USIM_LK [] USIM_T [] SIMR_IN# +V_TP P00 R.0G KSO KSO KSO KSO KSO KSO KSO0 K /X KSO K /X KSO0 0.UF/V /TP E 0PF/V E 0PF/V 0 TOUH_P SIE 0 SIE ZIF_ON_P G00S /TP K /X K /X K /X K /X K /X K0 /X K KSO /X KSI For assembly direction, K pin to K conn. pin KSI KSI KSI0 K 0 SIE 0 SIE 0 0 KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSI KSI0 KSI KSI KSI KSI KSI KSI KSO KSO KSO KSO KSO KSI KSI K KSO KSI KSI KSO KSO KSO KSO /X FP_ON_P /K 00H SUSTek omputer IN. 00H K_Touch Pad aron Tsao ate: Friday, March, 00 Sheet of.g

.G change to EVERLIGHT for HRGE LE Height:0.mm for POWER LE White for FLSH LE White PWR_LE- FLSH_LE- [,] PWR_LE_UP PT Q UMKN /LE +VS R0 0KOhm /LE Q UMKN FLSH_LE# /LE FLSH_LE HRGE_LE- HRGE0_LE- hange LE resistor to 0 Ohm, about m for WIFI/lueTooth LE White +VSUS [] HRGE0_LE# HRGE0_LE PT Q UMKN /LE aps_le- Wireless_LE- FLSH_LE- HRGE_LE- HRGE0_LE- PWR_LE- +VS +VSUS +VSUS [] Wireless_LE S GPIO Wireless_LE- Q UMKN Wireless_LE /LE +VSUS HRGE_LE 0.UF/V /udio for aps Lock LE White [] HRGE_LE# aps_le- +VS R0 0KOhm /LE aps_le Q UMKN /LE Q UMKN /LE R0 0KOhm /LE Q UMKN /LE 0 LE_ON 0 SIE SIE R0 0KOhm /LE Q UMKN /LE Q UMKN /LE WTO_ON_0P /LE [] S_STLE# TW /LE FLSH_LE# R0 0KOhm /LE +VS [] aps_le# Q UMKN /LE R0 0KOhm /LE From E PSLE# 00H SUSTek omputer IN. 00H LE Kenneth_Hung ate: Friday, March, 00 Sheet of 0.G

00H SUSTek omputer IN. 00H ischarge aron Tsao ate: Friday, March, 00 Sheet of.g

PWR oard/st/ln/us onnector [] P_ST_RXP0 [] P_ST_RXN0 [] P_ST_TXN0 [] P_ST_TXP0 I 0.0UF/V [,] PIE_WKE# /ST I 0.0UF/V I 0.0UF/V /ST /ST T VSUS_ON [] LK_PIE_LN [] LK_PIE_LN# [] PIE_RXP [] PIE_RXN [] PIE_TXN [] PIE_TXP [] US_PN [] US_PP [] US_PN [] US_PP [] US_PN [] US_PP [] LK_M_REER [,] _Z_ITLK [] _Z_SYN [] _Z_SIN0 [] _Z_SOUT [] _Z_RST# [] MER_EN [] R_REER_EN# [,] PWR_LE_UP [] OP_S# [] US_O# [] PWRTN# [,,,] PLT_RST# [] P_V_EN_0 [] VSUS_ON [,,,,] PM_LEVELOWN# [,] VSUS_PWRG [,,,0] SUS_ON I 0.0UF/V /ST ST_RXP0 ST_RXN0 ST_TXN0 ST_TXP0 to TO_ON_0P /to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +VS +VS +VSUS +VSUS +VS +V _T_SYS SW _T_IN# _SM_LK _SM_T L L L L only for S0 SP and SP 0Ohm/00Mhz /T0Ohm/00Mhz /T0Ohm/00Mhz /T T_IN# [] SM_LK [,] SM_T [,] T T IN 0.UF/V c00 /T /T/X 00PF/0V /T /T/X 0 00PF/0V /T /T/X [] P_V_EN_0 G S Q /T/X [] T_EN# R o Not /T/X Stuff r00 R r00 /T/X TT_SWITH_P /T ON R 0Ohm r00 /T R KOhm /T SW IP_SWITH_P /T 0UF/.V /T T _SM_LK _SM_T _T_IN# 0.UF/V c00 /T 0 TT_ON WTO_ON_0P /T 00H SUSTek omputer IN. 0 _PWR oard/st/ln/us onnector aron Tsao 00H +VS I /US_PWR/X ate: Friday, March, 00 Sheet of.g

H NP_N +.VS E /X /X +VS E /X +VS E /X +VS E /X +VS E /X +VS E /X H NP_N H0 0N 0N s00 s00 /PU /PU NP_N H H H +VS E00 +.VS _T_SYS E /X +VS +VSUS +VS +VSUS +VS +VSUS +.VS +Vccp E E E /X E /X /X +VS E /X /X +VSUS /X H H +Vccp 0 0.UF/.V +Vccp 0.UF/.V +VS 0.UF/0V +VS 0.UF/0V +VS 0.UF/0V NP_N NP_N +VS +VS +VS +VS /X /X 0.UF/0V 0.UF/.V 0.UF/.V 0.UF/.V +VSUS 0 0.UF/0V +VSUS 0.UF/.V +VSUS 0.UF/.V +.V 0.UF/.V R.G hange +.VS 0.UF/.V +.VS 0.UF/.V +V 0.UF/.V +V 0.UF/.V +V 0.UF/.V 00H SUSTek omputer IN. 00H Srew Hole aron Tsao ate: Friday, March, 00 Sheet 0 of.g

[,] _Z_ITLK E 0PF/V EP /X.G For ES _T_SYS E0 00PF/V +VS [,] VORE_V_SENSE [,] VORE_VSS_SENSE [,] H_PURST# +VS 0 0.0UF/0V +VS 0.UF/.V +VS 0.UF/.V E /X E /X E0 /X _T_SYS E 00PF/V +Vccp +VS 0.UF/.V +VSUS 0.UF/.V [] RTRST# [,] PM_RSMRST# [,] PM_PWROK E /X E /X E /X +VTT_R E 0.UF/.V +V +V _T_SYS E 0.UF/.V 00PF/V +VS _T_SYS E 0.UF/0V 00PF/V _T_SYS E 00PF/V _T_SYS E 00PF/V +.V +VTT_R E 0.UF/.V _T_SYS +.VS E +VS +.V E 0.UF/0V 00PF/V +VSUS +.V E 0.UF/.V E 0.UF/0V +VSUS +VS _T_SYS E E /X 00PF/V T +VS +VSUS E 0.UF/.V E /X +V _T_SYS E 00PF/V _T_SYS E 00PF/V _T_SYS E 00PF/V _T_SYS E 00PF/V +VS +VSUS +VS +VSUS E E 0.UF/.V 0.UF/.V +VS E 0.UF/.V +VSUS +VS E0 0.UF/0V +VSUS +VS E 0.UF/.V +VS E0 0.UF/.V +VS E 0.UF/.V +VS E 0.UF/.V +VS E 0.UF/.V +VSUS +VSUS E 0.UF/.V +VSUS +Vccp E 0.UF/.V +.VS E 0.UF/.V +VSUS E /X +VSUS E /X +VSUS E /X +.V E 0.UF/.V _T_SYS E 00PF/V +.VS +VS E +VSUS E +Vccp E0 /X 0.UF/.V 0.UF/.V 00H SUSTek omputer IN. 00H EMI aron Tsao ate: Friday, March, 00 Sheet of.g

/_OK_IN TSEL_P#, PREHG, T_LERN, HG_EN# M (ontrollor) _PR_U_0 T HG_OK#_0 SI (SWITH) SIN SWITH _T_SYS _T_SYS RT0 (ontroller) VSUS_ON Power oard +VSUS() +V (0.) +VSUS() SUS_ON SUS_ON RJK0 (SWITH) RJK0 (SWITH) Power oard +VS +VS (0.) () up +.VS (0.) +V (0.) Power oard up +V_E (0.) Power oard UP (ontroller) +.V () UP VTT_R(0.) SUS_ON (0.) + +.V_PLL RT0PQW (ontroller) +.VS () RT0PQW (ontroller) +VP(.0V) (.) PU_VRON VR_VI0~VR_VI, PU_VRON, VP_PWRG, VORE_VSENSE,VORE_VSSSENSE P (ontrollor) +VORE () VRM_PWRG, LK_EN# 00H SUSTek omputer IN. 00H Power Flow aron Tsao ate: Friday, March, 00 Sheet of.g