Nonideal Effects in SC circuits

Nonideal Effects in SC circuits Switches: Nonzero on -resistance Clock feedthrough / charge injection Junction leakage, capacitance Noise Capacitors: Capacitance errors Voltage and temperature dependence Random variations Leakage Op-amps: DC offset voltage Finite dc gain Finite bandwidth Nonzero output impedance Noise 1

Switched-Capacitor Integrator

Nonzero Switch on -Resistance φ R on ~ 1 k( V V gs t ) out i out = C = Id dv dt i triode C is charged exponentially Body effect! φ Vds Vin Vout φ C To lower on-resistance and clock feedthrough: CMOS gate; Wp,Lp =Wn,Ln. For settling to within 0.1%, T 7R C (Worst-case Ron). settling on 3

Digital CMOS Scaling Roadmap Want analog circuit to operate at low supply voltage 4

Floating Switch Problem in Low-Voltage Vdd 0 Vdd C 0 Vdd Vtn Vdd Vtn 0 Small headroom Vtp NO headroom 0 Vtp 5

Using Low-Threshold Transistors Precise control over process and temperature difficult Switch leakage worsens as threshold voltage is lowered (i.e. hard to turn off) 6

Using Clock Voltage Booster Boosted clock voltage (e.g. 0 Vdd) is used to sufficiently overdrive the NMOS floating switch useful in systems with low external power supply voltage and fabricated in high-voltage CMOS process Voltage limitation is violated in low-voltage CMOS Vdd Vdd 0 Vdd φ φ 0 Nakagome et al. JSSC-1991 φ φ 1 7

Using Boostrapped Clock Abo et al., JSSC-1999 Steensgaard, ISCAS-1999 Singer et al., ISSCC-000 Dessouky et al., JSSC-001 (fast) Hernes et al., ISSCC-004 φ φ φ Principle: pre-sample Vdd before placing it across Vgs (various lowvoltage issues complicate implementation) Input sampling such as this can be used for low-voltage CMOS or for high-linearity sampling No fundamental topological limitation on higher input signal frequency w.r.t. sampling frequency 8

Switched-Opamp Technique Floating switch is eliminated Opamp output tri-stated and pulled to ground during reset φ Slow transient response as opamp is turned back on during Crols et al., JSSC-1994(1.5-V) Peluso et al., JSSC-1997(1.5-V) Baschirotto et al., JSSC-1997(1-V) Peluso et al., JSSC-1998(1-V) Cheung et al., JSSC-00 (1-V) φ φ φ φ φ 1 φ φ Switched-opamp integrator Conventional integrator 9

Switched-Opamp Example Crols et al., JSSC-1994 Peluso et al., JSSC-1997 The entire opamp is turned off during Demonstrated 1.5-V operation (ΣΔ ) with Vtn= Vtp =0.9V 115kHz at -60dB THD & 500kHz at -7dB THD φ φ φ φ φ1 Baschirotto JSSC-1997: 1-V operation Peluso JSSC-1998: 0.9-V operation 1.8MHz at -40dB THD Cheung et al., JSSC-00(1-V) 10

Opamp-Reset = Unity-Gain Configuration Bidari et al., ISCAS-1999 Keskin et al, ESSCIRC-001 & JSSC-00 Chang et al, CICC-00 & JSSC-003 Chang et al, VLSI-003 & TCAS1-005 Li et al, VLSI-004 & JSSC-005 φ φ High speed operation Free of reliability issues φ φ φ φ Conventional integrator Switched-opamp integrator 11

Floating Reference Avoids Fwd Bias C3 is precharged during C3 (floating reference) in feedback duringφ DC offset circuit (C4=C1/) compensates for Vdd reset of C1 effective virtual ground = Vdd/ Vdd Vdd φ C4 φ1 C3 1 φ Vdd φ C φ Vdd/ Vin φ C1 φ Vout 1

Switched-RC = Resistor Isolation φ φ No floating switch Highly linear sampling Free of reliability issues φ φ φ φ Conventional integrator Switched-opamp integrator 13

Switched-RC = Resistor Isolation Ahn et al., ISSCC-005 Paper 9.1 14

Simple SC integrator Charge Injection (1) S1 structure 15

Charge Injection (1) (Cont d) The lateral field is v / L, the drift velocity is µv / L, and hence the current is i = qch µ v / L The on-resistance is R on = v / i = L /( qch µ ) And hence Ron qch = holds. L / µ 16

From device physics, Charge Injection () q ch = W L C ox ( Vdd vin Vtn ) Unless S1 is in a well, connected to its source, Vtn depends on Vin, so qch is a mildly nonlinear function of Vin. When S1 cuts off, part of qch(qs) enters C1 and introduces noise, nonlinearily, gain and offset error. To reduce qs, choose L small, but μ and Ron large. However, for 0.1% settling R C < T /14 = 1/(14 f ) on Hence qch and v 1 c, min = L C /( Ron,max µ ) = 14 L f c 1 / µ = d q / C = 14 d L err, min ch,min 1 c f / µ where d = q s / q ch. 17

Clock Feedthrough Capacitive coupling of clock signal via overlap Cov between gate and source. The resulting charge error is q ov = V dd C ov C /( C 1 + C 1 ov ) It adds to qs. Usually, q V ov dd C ov Linear error; normally q << q. ov s Same for S1 and S. 18

Methods for Reducing Charge Injection Transmission gates: cancellation if areas are matched. Poor for floating switches, somewhat better for fixed-voltage operation Dummy devices: better for d~0.5 (a) (b) (c) (d) 19

Advanced-Cutoff Switches Signal-dependent charge injection leads to nonlinear distortions; signal-independent one to fixed offset. Advanced-cutoff switches can reduce signal dependence 0

Advanced-Cutoff Switches (Cont d) Remaining charge injection is mostly common-mode in a differential stage Suppressed by CMRR. In a single-ended circuit, it can be approximated 1

Floating Clock Generator To reduce signal dependence, reference the clock signal to vin: This makes Ron also signal independent, so the settling is more linear. Clock feedthrough remains signal dependent, but it is a linear effect anyway

Charge Injection Suppression in a Comparator Advance cutoff to reduce injection when 0: 3

Delta-Sigma ADC 4

Junction Leakage I1 ~10 pa/mil, 0.4pA/5µ 5µ, but doubles for each o 0 C 100 o C fmin ~ 100Hz at, but 5kHz at o 10 C Fully differential circuit and Martin compensation works 5

Capacitances Inaccuracies Depends only on C ratios. Strays are often p-n junctions, lead to harmonic distortion also. For stray-sensitive integrator, all strays should be < 0.1% of αc C can be systematic or random. Random effects (granularity, edge effects, etc.) cannot be compensated, but systematic ones can, by unit-capacitor/common-centroid construction of αc and C 6

Oxide gradient Capacitances Inaccuracies (Cont d) Common-centroid geometry Compensated C1/C against linear variations of Cox, and edge related systematic errors (undercut, fringing) 7

Capacitances Inaccuracies (Cont d) Voltage and temperature coefficients c C v = 1 c γ usually γ v ~ 10 ppm / V C v c C usually T = 1 c γ γ T ~ 0 ppm / V C T Smaller for ratios, especially for common-centroid layout: Fringing, undercut: systematic edge effects. Reduced by commoncentroid geometry, since perimeter/area ratio is the same for C1 and C, C perimeter, C area. 8

OPAMP Input Offset In most analog IC, the active element is the opamp. It is used to create a virtual ground (or virtual short circuit) at its input terminals: v i i = 0 v = 0 This makes lossless charge transfer possible. In fact, in a CMOS IC, i 0 but v 0 due to offset, 1/f and thermal noise and finite opamp gain A. Typically, v = 5 ~ 10mV. This affects both the dc levels and the signal processing properties. The effect of v is even more significant in a low-voltage technology where the signal swing is reduced, and A may be low since cascoding may not be available. 9

Techniques for Reducing the Effect of Imperfect Virtual Grounds Autozeroing or Correlated Double Sampling Schemes: Scheme A: Stores and subtracts v at the input or output of the opamp; Scheme B: Refers all charge redistributions to a (constant) v instead of ground; Scheme C: Predicts and subtracts v, or references charge manipulations to a predicted. Compensation using extra input: An added feedback loop generates an extra input to force the output to a reset value for zero input signal. Chopper stabilization: The signal is modulated to a safe (low-noise) frequency range, and demodulated after processing. Mixed-mode schemes: Establish a known analog input, use digital output for correction. 30

Circuits Using Autozeroing Comparators Amplifiers S/H, T/H, delay stages Data converters Integrators Filters Equalizers 31

Simple Autozeroed Comparator Nonidealities represented by added noise voltage: v n = v = Vos + v1 / f + vthermal µ vout; µ = 1/ Aopamp φ =1 Input-referred noise at the end of v n, in( n) = vn( n) vn( n 1/ ); interval: Transfer function without folding: H 4sin N = ( ωt / 4) µv out Vos, V1/f and (for oversampled signals) may be reduced by H N. Here, µv out is not considered, since it is not important for a comparator. 3

An Offset- and Finite-Gain-Compensated SC Amplifier Haug et al., 1984 ISCAS 33

Analysis of Compensated Gain Amplifier Input-output relation for inverting operation: v out ( n) = C1 / Cvin ( n) + (1 + C1 / C )[ v ( n) v ( n 1/ )] The S/H capacitor switches from 0 to v v ( n) = V v ( n 1/ ) as. Hence, os µ out 1 ( n 1/ ) v ( n 1) = V v ( n 1/ ) out out os µ out At low signal frequencies where, the error term is only C1 / C H (1) = (1 + C / C ) µ 1 ( 1+ C1 / C ) µ v out v out, where µ = 1/ A. ( n) v ( n 1). The dc gain is The output step at reset is only Av Vos µ vout ( C1 / C3 ) vin, where the last term enters for noniverting operation only. Av is usually 1~10 mv. The slewing required is minimal. The output offset is µ 1+ C / C ). out ( 1 V os Clock feedthrough generates some residual offset. Can be used as a compensated delay stage. 34

Finite Opamp DC Gain Effect ( jωt ) / jωt ( C / ) For 1 C e A0, H i ( e ) = sin(( ωt ) / ) jωt jθ ( ω ) jωt For A < H ( e ) = (1 + m( ω)) e H ( e ). 0, Here, the relative gain error m 1/ A0 )(1 + C1 /(C the relative phase error θ ( C1 / C ) /( A0ωT ). (Martin, PhD thesis, U of Toronto, 1980) i ( )) A0 Inverting delay-free stray-insensitive integrator. At unity-gain freq. ω : sin( i i T / ) = C1 / C, m ω i ) ~ θ ( ωi ) ~ Usually, the magnitude error is smaller the (C1/C) error and is negligible. The phase error shifts poles/zeros horizontally, like dissipation: important! ( 1/ A ω 0 35

Finite Opamp DC Gain Effect (Cont d) Non-inverting integrator: similar derivation, same m (ω), θ (ω). In a biquad, s s 1 1/ A ) due to m(ω). The phase errors result in p 1 Q p ( 0 p 1 Q p 1 + θ1( ω0 ) + θ ( ω0 ) ~ Q p + A 0 A0 Change in peak gain: 0 lg(1 + Q p / A0 ) (in db) can be large for >> 1! Q p For Q p = 15, A0 = 1000, G ~ 0. 6dB High Q p use high A0 opamp! Gain-squaring integrators! 36

Finite Opamp Bandwidth Effect One-pole opamp model: ω0 1 A ( s) = s s1 s / ω0 + 1/ A0 Or, in time domain, 1 1 dvo ( t) vo ( t) + = v( t) A ω dt v = 0 0 Vo ( s) V ( s) Combine with KVL, charge conservation. Finding and sampling vo(t), jωt calculating Vo(z)/Vi(z), and setting z = e,for an inverting integrator results in k1 m( ω) = e (1 k cosωt ) e k 1 θ ( ω) = k sinωt Where k = C /( C1 + C) is the feedback factor. k 1 = kω 0T / = kπf 0 / f c should be >>1. Time constant: τ = /( kω ) should be << T/. 1 0 37

Finite Opamp Bandwidth Effect (Cont d) Since k kπω / ω, for k~1, if ω 0 5ω then k 1 15 and e k = 1 0 c c < 3 10 1 ω 0 5ω c. 7 θ, so both m and are negligible. Hence, for C1<<C, use Due to the exponential behavior, the error increases rapidly if too small! ω 0 is The derivation assumes vin(t) is constant. If several stages settle simultaneously, or if there is a continuous-time loop of opamp and coupling C s, then computer analysis (SWITCAP, Fang/Tsividis) is needed. 38

High-Q Biquad Vin OA1 V1 * * OA Vout * * For original phases, both opamps settle when φ 1. Changing the *φi, they settle separately. V1 changes twice in one cycles, but OA1 still has the same T/ time (T for the change at 1 ) to settle and to charge C3. The transient when φ 1 has a full period to settle in OA1 and OA. 39

Slew Rate Nonlinear slewing followed by linear settling: t slew = xt ~ xt / S = r ( dvout ) /( dt). For v ( t ) = V t max max sinω B where ω B is the maximum sine wave freq. at input, the slope dv / dt of the envelope v(t) is ω B V max. Then S V r ~ ω B max / x, very pessimistic estimate! 40

Noise Considerations Clock feedthrough from switches External noise coupled in from substrate, power lines, etc Thermal and 1/f noise generated in switches and opamps (1) Has components at f=0, fc, can be reduced by dummy switches, differential circuit, etc. May be signal dependent! () Discussed elsewhere. (3) Thermal noise in MOSFETs: PSD is S T vnt = = 4θR f, θ = kt For f 0 only (one-sided distribution). Flicker noise: S vnt f f = = C ox k WLf Total noise PSD: S=ST+Sf. 41

Noise Considerations (Cont d) Corner frequency: fcr=1~50khz S( f ) = vn / f Offset compensation (CDS correlated double sampling); subtracts noise, T/ second delayed H CDS = 1 e H = 4sin ( ωt jωt / / 4) H S( f ) CDS 1. Pick up noise, no signal. Pick up noise, plus signal 3. Substract fc Modulated 1/f noise fc 4

Chopper Stabilization Fully differential circuits needed. 43

Chopper Stabilization (Cont d) φ φ φ φ + V in V in Differential SC amplifier. 44

φ Noise Aliasing Vin + - C Mean-square values are the same ( θ / C) within all windows. 0 1 φ mt T v cn t Direct noise power: S/H PSD: s / H ( vcn ) f ( v d cn ) mθ = C τ sin fτπ = Tfτπ k = k = S( f kf c ) 0 t d v cn S(f): RC filtered direct noise Most noise at dc! 0 t S H v / cn 0 mt mt+t mt+t mt+3t t 45

Equivalent Circuit for Direct Noise v nt = S ( f ) f T ~ Ron Vin=0 + - C S(f) for direct noise: low-pass filtered and windowed white noise. θr on f sw 1 = 4R on C For satisfactory settling (0.1%), R C mt 7 = m /(7 f ), fsw 3. 5 fc. on f sw 1 = 4R C on / c 46

Aliasing for fsw = 5 f c Noise Aliasing S(f) is magnified by f / = 10! The PSD is θ Cf ) after aliasing (i.e. sampling but not holding). Noise power = kt/c. sw f c /( c 47

For low frequencies (f<<fc) S S S / H ) d ( f ) (1 m θ f C ( f ) mθr S ( f ) / S c S / H S / H in db (0) 0-5 -10-15 -0-5 -30 decreases with m increases with m Low frequency noise ratio r 3.5(1/ m 1) > on 3.5 Noise Spectra S/H noise spectrum for m=0.5 1 3 4 5 r S S = S / H d (1 m) m For m=0.5, r=31.5! Noise generated in stage independent of Ron, but the noise generated in preceding stages (direct noise) gets filtered, so the Ron should be as large as possible! f c 1 R on C f/fc 48

Switched-Capacitor Noise Two situations; example: Situation 1: only the sampled values of the output waveform matter; the output spectrum may be limited by the DSP, and hence VRMS,n reduced. Find VRMS from ktc charges; adjust for DSP effects. Situation : the complete output waveform affects the SNR, including the S/H and direct noise components. Usually the S/H dominates. Reduced by the reconstruction filter. 49

Calculation of SC Noise (Summary) In the switch-capacitor branch, when the switch is on, the capacitor charge noise is lowpass-filtered by Ron and C. The resulting charge noise power in C is ktc. It is a colored noise, with a noisebandwidth fn=1/(4ronc). The low-frequency PSD is 4kTRon. When the switch operates at a rate fc<<fn, the samples of the charge noise still have the same power ktc, but spectrum is now white, with a PSD=kTC/fc. For the situation when only discrete samples of the signal and noise are used, this is all that we need to know. For continuous-time analysis, we need to find the powers and spectra of the direct and S/H components when the switch is active. The direct noise is obtained by windowing the filtered charge noise stored in C with a periodic window containing unit pulses of length m/fc. This operation (to a good approximation) simply scales the PSD, and hence the noise power, by m. The lowfrequncy PSD is thus 4mkTRon. 50

Calculation of SC Noise (Summary) (Cont d) To find the PSD of the S/H noise, let the noise charge in C be sampledand-held at fc, and then windowed by a rectangular periodic window w(t)=0 for n/fc<t<n/fc+m/fc w(t)=1 for n/fc+m/fc<t<(n+1)/fc n=0,1,, Note that is windowing reduces the noise power by (1-m) squared(!), since the S/H noise is not random within each period. Usually, at low frequencies the S/H noise dominates, since it has approximately the same average power as the direct noise, but its PSD spectrum is concentrated at low frequencies. As a first estimate, its PSD can be estimated at (1 m) kt /( fcc) for frequencies up to fc/. 51