Floating Point Representation and Digital Logic Lecture 11 CS301
Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8 at 5pm Program #1 assigned w Due Thursday, 10/18 at 11:59pm Read Appendix C.1-C.3, C.5
Digital Logic (How do we construct a processor?)
Multi-Million Transistor Chips Intel Core i7 Extreme Edition - 731 million transistors, 263 mm^2 area
MOS Semiconductor Transistors Source Wire Gate Wire Drain Wire n-type Si e - e - n-type Si Gate e - e- e - e - e - e - Source Drain e - e - Oxide e - e - e - e - e - e - Silicon Bulk (p-type) e - e - P-type silicon: Excess positive charges (electron holes) N-type silicon: Excess negative charges (electrons) Oxide: Insulator Gate: Metal pad In this state, current (electrons) cannot flow between source and drain switch is OPEN
MOS Semiconductor Transistors n-type Si Drain Wire Source Wire 5V Gate Wire n-type Si Gate e e - e- - e - e e - - e - e - Source e - e - e - e - e - e - e - e - e - Drain e - Oxide e - e - Silicon Bulk (p-type) Place a positive charge on the gate wire (gate = 5V) The gate s positive charge attracts negatively-charged electrons This row of electrons forms a channel connecting the Source and Drain Current can flow Switch is CLOSED
Transistors Transistors w Emits 0 or 1 when on or off w Can connect transistors in series or parallel to create larger building blocks called gates A 5V GND Z Pull-up pmos transistor Pull-down nmos transistor CMOS Inverter created from two transistors
Digital Logic Voltages represent values w Logically false - 0 w Logically true - 1 Values are complements or inverses
Gates: Basic Building Blocks: Depending on organization of transistors, different inputs give specific outputs Basic gates equivalent to boolean operators w INVERTER or NOT,! w AND, && w OR, A A Combinational logic A B w Outputs based on inputs A B w No memory A B A B
Truth Tables Functionality fully specified by truth table n inputs w n input columns w 2 n input rows m outputs w m output columns A Z 0 1 1 0 A B Z 0 0 0 0 1 0 1 0 0 1 1 1 A B Z 0 0 0 0 1 1 1 0 1 1 1 1 NOT AND OR
Combinational Logic Gates can be combined in w Series w Parallel Any combination of both possible B A B Y Y Z Z A A A 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1
Other Important Gates NAND NOR A B Z 0 0 1 0 1 1 1 0 1 1 1 0 A B Z 0 0 1 0 1 0 1 0 0 1 1 0 A B A B A B A B
Universal Gates Any other gate can be constructed from some arrangement of universal gates w Examples: NAND / NOR Important because frequently less expensive to design chips with homogeneous gates
Universal Gates (NAND) NOT A A AA 0 1 1 1 0 0 A A A
Universal Gates (NAND) NOT AND A A AA 0 1 1 1 0 0 A B AB 0 0 0 0 1 0 1 0 0 1 1 1 A A A
Universal Gates (NAND) NOT AND A A AA 0 1 1 1 0 0 A B AB AB 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 A A B A A A B
Universal Gates (NAND) OR A B AB 0 0 0 0 1 1 1 0 1 1 1 1
Universal Gates (NAND) OR A B AB AB 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 A B AB
For Fun: XOR A B A B 0 0 0 0 1 1 1 0 1 1 1 0
For Fun: XOR A B A B 0 0 0 0 1 1 1 0 1 1 1 0
Few Final Notes Gates can have more than 2 inputs w Generally keep number small due to electrical engineering issues Circuits that create current computers are constructed from these basic gates
Equivalent Truth tables Circuit Boolean algebra expression Truth tables are great for evaluating when circuit or Boolean expression evaluate to true
Combinatorial Logic: Multiplexor Really a selector: One of the inputs is selected by the control C = (A * ~S) (B * S) 23
Combinational Logic: Multiplexor 2 n inputs n:1 MUX 1 output n control n control lines select which of 2 n inputs goes to output n possible input lines requires ceiling(log2n) control lines. Equivalently, n control lines with 2 n input lines.
1-bit MUX AS BS
Combinational Logic: De-Multiplexor 1 input n:1 DEMUX 2 n outputs n control n control lines select which of 2 n outputs input goes to
1 to 2 De-multiplexor
Combinational Logic: Decoder n control 2 n outputs n control lines select which of 2 n outputs set to 1
1 to 8 De-multiplexor
Combinational Logic: Encoder 2 n inputs n bit output One of 2 n inputs set to 1. Output encodes which input set to 1.
4 to 2 Encoder
8 to 3 Encoder 33
Combinational Logic Comparator w Given 2 inputs, sets output to 1 if inputs match
Combinational Logic Half-Adder w No carry in
Combinational Logic Half-Adder w No carry in A B Sum Carry Out 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 A B AB
1-bit Full Adder Three inputs: w A w B w C in Two outputs: w Sum = (A B) C in w C out = AB (A B) C in
Ripple Carry Adder Construct n-bit adder with n 1-bit adders Delay is problem Faster alternative: w Carry-lookahead adder