EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well LOCOS Field oxide General Features of the EE410 Process 7 mask levels 0.45µm minimum dimensions 540nm field oxide LOCOS isolation 10nm gate oxide p+ poly-si gate for PMOS transistors and n+ poly-si for NMOS transistors single mask n + and p + source/drain definition (no LDD) single level of aluminum/silicon metallization phosphosilicate glass (PSG) passivation non-silicided contacts (high metal contact resistance to poly and active regions) 2 2 1
Dual Well CMOS Technology Global Interconnect Semi-global Interconnect N-well P+ P+ N+ N+ LDD P-well LOCOS Isolation PMOS NMOS 3 Feature Size Trend & Moore s Law 1 Generation 0.1 micron L GATE 0.01 0.001 1980 1990 2000 2010 2020 Reduction in transistor area has resulted in higher packing density and hence more complex chips 4 2
Scaling of MOS Gate Dielectric K I D g m thickness (Ref: S. Asai, Microelectronics Engg., Sept. 1996) Gate SiO 2 thickness is approaching < 10 Å to improve device performance How far can we push MOS gate dielectric thickness? How will we grow such a thin layer uniformly? How long will such a thin dielectric live under electrical stress? How can we improve the endurance of the dielectric? 5 MOS Technology in 2010 Gate oxide thickness ~ 1 nm Channel Length ~ 20 nm Junction depth ~ 1-2 nm Size of an atom ~ 5Å In integrated system 10 billion components 10 interconnect layers Technological Issues Gate dielectrics/electrode Shallow junctions Isolation Contacts Interconnections 6 3
Problems in Scaling of Gate Oxide Below 20 Å problems with SiO 2 Gate leakage => circuit instability, power dissipation Degradation and breakdown Dopant penetration through gate oxide Defects 7 MOSFET Scaling Limit: Leakage Total Leakage Trend Gate Leakage S/D Leakage Source: Marcyk, Intel Lo et al.,ieee EDL, May 1997. Total Power Trends Ability to control I off will limit gate-length scaling Thermionic emission over barrier QM tunneling through barrier Band-to-band tunneling from body to drain To suppress D/S leakage, need to use: Higher body doping to reduce DIBL lower mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric to improve gate control higher gate leakage Ultra-shallow S/D junctions to reduce DIBL higher R series 8 4
High-k Dielectric Technology Evolution Physical thickness can be increased for MOS gate dielectric operation by using a higher K dielectric K I D g m thickness Long term Today 20 Å SiO 2 K 4 Si Near future 40 Å Si 3 N 4 K 8 100 Å high K K 20 Higher thickness -> reduced gate leakage 9 Silicide R csd Parasitic S/D Resistance Sidewall R dp R ext N ext (x) y = 0 R ov Gate N ov (y) R R ch sd Lchtox ( V V ) th R sh gs 1 N X sd Scaled with L g (L ch, t ox ) j Difficult to scale (N sd const, X j ) R sd /R ch I DS [( ) I DS R SD ] α SAT = Κ V GS V T Problem in junction scaling: With scaling parasitic S/D resistance R SD increases compared to channel resistance Contact resistance R csd is one of the dominant components for future technology Problem more serious for PMOS Source: Jason Woo, UCLA 10 5
Solutions to Shallow Junction Resistance Problem Extension implants Elevated source/ drain Silicidation 11 Device Isolation pitch as a function of minimum dimension 2.5 2.0 16M 1.5 64M 1.0 1G 0.5 P. Fazan, Micron, IEDM-93 With decreasing feature size the requirement on allowed isolation area becomes stringent. 0.0 0.0 0.2 0.4 0.6 0.8 1.0 Minimum dimension [µm] 12 6
Scaling of Device Isolation Semi-recessed LOCOS Nitride Pad oxide Nitride Field oxide LOCOS based isolation technologies have serious problems in loss of area due to birdʼs beak. Shallow trench isolation P-substrate N-well Deep trench isolation Trench isolation can minimize area loss 13 Physical Limits in Scaling Si MOSFET Source/Drain Contact resistance Band-to-band tunneling Doping level, abruptness Source Gate stack Tunneling current Gate depletion, resistance Gate Drain High E-Field Mobility degradation Reliability te Substrate Channel Surface scattering - the universal mobility tyranny Subthreshold slope limited to 60mV/decade (kt/q) V G - V T decrease DIBL leakage Net result: Bulk-Si CMOS device performance increase commensurate with size scaling is unlikely beyond the 65 nm generation 14 7
3 New Structures and Materials for Nanoscale MOSFETs 5 4 2 1 Si G S C D Si SiO 2 Source High µ channel Top Gate Bottom Gate BULK SOI Double gate Drain High-K 1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage 2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay 3. Parasitics - Schottky S/D - Reduced extrinsic resistance 4. Gate leakage - High-K dielectrics - Reduced power consumption 5. Gate depletion - Metal gate 15 Non Planar MOSFETs Vertical FET D Double Gate FinFET Channel Tri Gate FET Gate 1 Gate 2 Source SiO 2 Tsi:45nm Lch=250nm Drain Gate1 Gate2 Source Gate Source Drain Stanford UC Berkeley 16 Intel 8
Mobility Enhancements in Strained-Si MOSFETs Gate electrode n + p o l y LTO gate oxide spacer Strained Si n + Relaxed Si 1-x Ge n + x Si 1-x Ge x Graded layer Si Substrate Mobility Enhancement Factor 2.0 1.8 1.6 1.4 1.2 Calculated for strained Si 1.0 MOS inversion layer M S. Takagi, et al., J. Appl. Phys. 80, 1996..80 0.0 0.10 0.20 0.30 0.40 Substrate Ge fraction, x V DS = 10 mv 300 K NMOS Measured, J. Welser, et al., IEDM 1994. Gibbons Group, Stanford 17 Intel PMOS Seemingly Useful Devices Limited Current Drive Cryogenic operation Limited Fan-Out Critical dimension control Challenging fabrication and process integration B + = ~ 2 nm Spintronics Need high spin injection and long spin coherence time Limited thermal stability New architectures needed 18 Carbon Nanotubes Controlled growth 9
Limits of Interconnect 22nm Node 32nm Node 2.5X Combined Grain Boundary Scattering Surface Scattering Cu (bulk) Old A New (scaled) l 19 bit rate B A/l 2 Scaled wire with lower A and longer l has higher R,C and L and thus reduced bandwidth, higher delay and higher power dissipation Current Interconnect Technologies Copper 6 Copper 5 Copper 4 Copper 3 Copper 2 Copper 1 Current Al technology (Courtesy of Motorola) Current Cu/low-K technology (Courtesy of IBM) Tungsten Local Interconnect Reduced resistivity and dielectric constant results in improvement in performance. 20 10
Carbon Nanotubes 1-D conductors: 3-D conductors: E Quantum Wires: Very limited phase space for scattering. Mean free paths as large as 1.6µm. Lower resistivity E Conventional metal wires : Backscattering through a series of small angle scatterings. Mean free paths ~ 30nm. Higher resistivity Potential Candidates for GSI Interconnects. 21 Can Optical Interconnects help? On-Chip Optical Interconnects 40Tb/s Optical I/O1024 x OC-768100Tb/s On-ChipBisection BW For Clock Distribution P Chip-to-chip Optical Interconnects modulator chip grating grating receiver chip Signal wires Reduce delay Increase bandwidth incoming short Clock distribution laser pulse Reduce jitter and skew I/O with very high bandwidth Reduce power 22 fiber 11
Summary: Technology Progression Bulk CMOS Cu interconnect Low-k ILD FD SOI CMOS Wafer bonding Crystallization Double-Gate CMOS 3D, heterogeneous integration Optical interconnect Nanotechnology Metal gate High k gate dielectric Strained Si Ge channel Detectors, lasers, QWM, waveguides Si (tensile) Si 0.8Ge 0.2 Si 1-xGe x Self-assembly Nanotube Si Interconnects and contacts for nanodevices Molecular devices 100 nm Feature Size 23 2 nm 12