E18 DR. Giorgio Mussi 14/12/2018

Similar documents
Last Name Minotti Given Name Paolo ID Number

Last Name _Di Tredici_ Given Name _Venere_ ID Number

Lecture Notes 7 Fixed Pattern Noise. Sources of FPN. Analysis of FPN in PPS and APS. Total Noise Model. Correlated Double Sampling

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

MOSFET: Introduction

Lecture Notes 2 Charge-Coupled Devices (CCDs) Part I. Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis

MOS Transistor I-V Characteristics and Parasitics

Choice of V t and Gate Doping Type

SWITCHED CAPACITOR AMPLIFIERS

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

MOS Transistor Theory

Lecture 12: MOS Capacitors, transistors. Context

Section 12: Intro to Devices

Advances in Radio Science

MOS Transistor Theory

Semiconductor Physics Problems 2015

PN Junction and MOS structure

Semiconductor Physics fall 2012 problems

FIELD-EFFECT TRANSISTORS

ECE 342 Electronic Circuits. 3. MOS Transistors

Junction Diodes. Tim Sumner, Imperial College, Rm: 1009, x /18/2006

Power Dissipation. Where Does Power Go in CMOS?

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

EE5311- Digital IC Design

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

Lecture 12 CMOS Delay & Transient Response

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Topic 4. The CMOS Inverter

The Devices: MOS Transistors

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Lecture 3: CMOS Transistor Theory

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Estimation and Modeling of the Full Well Capacity in Pinned Photodiode CMOS Image Sensors

ECE 497 JS Lecture - 12 Device Technologies

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

Section 12: Intro to Devices

Lecture 5: CMOS Transistor Theory

Integrated Circuits & Systems

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

EE105 - Fall 2006 Microelectronic Devices and Circuits

6.012 Electronic Devices and Circuits Spring 2005

Last Name _Piatoles_ Given Name Americo ID Number

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

EE105 - Fall 2005 Microelectronic Devices and Circuits

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

6.012 Electronic Devices and Circuits

ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling

VLSI Design and Simulation

EE 560 MOS TRANSISTOR THEORY

MOS CAPACITOR AND MOSFET

Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi

Lecture 5 Junction characterisation

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

The Gradual Channel Approximation for the MOSFET:

Extensive reading materials on reserve, including

Class 05: Device Physics II

Lecture 4: CMOS Transistor Theory

Mixed Analog-Digital VLSI Circuits & Systems Laboratory

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

Digital Integrated Circuits A Design Perspective

Effects of Transfer Gate Spill Back in Low Light High Performances CMOS Image Sensors

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies. Philips Research, The Netherlands

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

1. The MOS Transistor. Electrical Conduction in Solids

Lecture 04 Review of MOSFET

OPTI510R: Photonics. Khanh Kieu College of Optical Sciences, University of Arizona Meinel building R.626

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?

Lecture 2. Introduction to semiconductors Structures and characteristics in semiconductors

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

Integrated Circuits & Systems

Lecture 5: DC & Transient Response

ECE PN Junctions and Diodes

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Lecture 11: MOS Transistor

Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors

Electrical Characteristics of MOS Devices

Lecture 12: MOSFET Devices

ECE-305: Fall 2017 MOS Capacitors and Transistors

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

(Refer Slide Time: 03:41)

Classification of Solids

Semi-Conductors insulators semi-conductors N-type Semi-Conductors P-type Semi-Conductors

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

PURPOSE: See suggested breadboard configuration on following page!

Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today

EE115C Digital Electronic Circuits Homework #6

ECE321 Electronics I

Digital Electronics Part II Electronics, Devices and Circuits

Transcription:

POLITECNICO DI MILANO MSC COURSE - MEMS AND MICROSENSORS - 2018/2019 E18 DR Giorgio Mussi 14/12/2018 In this class we will define and discuss an important parameter to characterize the performance of an image sensor: the dynamic range (DR); we will then analyze how the dynamic range limits the maximum achievable signal-to-noise ratio (SNR) of a pixel; finally, we will quantify the error committed when neglecting the full expression of the photodiode capacitance. PROBLEM A digital still camera features a 3T CMOS active pixel sensor (APS), as the one shown in Fig. 1. Each pixel occupies an area of (3 µm) 2, with a fill factor of 45%. The technology used by the foundry for the production of the sensor allows a maximum voltage of 3.3 V and a minimum size of the devices equal to 150 nm; the oxide capacitance per unit area of a MOS transistor is 4 ff/µm 2. The quantum efficiency of the considered pixel is 0.65. In operation, each photodiode is reverse biased and its depletion region is 1 µm wide. In this configuration, the dark current of the pixel is equal to 0.2 fa. We are asked to... 1. Calculate the dynamic range at the analog output as a function of the integration time, and its value for an integration time of 10 ms. 2. Choose the number of bits for the analog-to-digital converter (ADC) at the output of the sensor. 1

3. Determine the maximum signal-to-noise ratio at the given integration time. 4. Determine the effects of the variation of the depletion capacitance on the dynamic range. Figure 1: Standard 3T APS. PART 1: DEFINITION AND CALCULATION OF THE DYNAMIC RANGE The dynamic range is defined as the ratio between the maximum detectable signal and the minimum detectable signal: DR maximum detectable signal minimum detectable signal. While the minimum detectable signal is set by noise, the maximum signal is the signal that causes the saturation of the pixel, i.e. the signal for which the output voltage would either rise above or drop below the supply rails of the circuit. A camera with a good dynamic range is capable to simultaneously distinguish details both in bright and in dark areas of the same scene. Some scenes have a wide dynamic range, meaning that there is a significant difference in brightness between the shadows and the highlights (e.g. shooting a silhouette at sunset), while others have a much narrower range of brightness 2

levels. When you take a picture, there are actually two dynamic ranges to consider: the dynamic range of the scene you re photographing and the dynamic range of the camera s imaging sensor. The sensor inside your digital camera can only record a fixed dynamic range (in a single exposure). As long as the difference in brightness between the darkest and lightest areas of a scene fall within this dynamic range, you ll be able to record detail in both areas simultaneously. For example, if a camera sensor has a certain dynamic range and the difference between the shadows and highlights of the scene is lower, then you ll be able to capture detail in all areas of the scene. However, if the dynamic range of the scene or subject exceeds that of the camera sensor, you ll end up with a picture where the shadows are completely black or where the highlights have blown and become totally white - and sometimes both. Regarding the integration capacitance, with the given data, the photodiode capacitance turns out to be C PD ɛ Si A pi xel F F 0.42 ff. x dep We know that the integration capacitance is given by the parallel (the sum) of the photodiode intrinsic capacitance and the parasitic capacitance from the integration node to ground: C int C PD +C P. The main contribution to this parasitic capacitance is given by the input capacitance of the source follower. Let s assume a minimum-size transistor: W L 150 nm; in order to have high fill factors, transistors within the pixel will be likely designed with minimum lengths. In this situation (rough approximation), C SF C ox W L 4 ff/µm2 0.15 µm 0.15 µm 0.09 ff, which is lower than the photodiode capacitance. Hence, the assumption C int C PD is valid. We can make a couple of reasonable approximations, to estimate the dynamic range: when estimating the maximum signal, we suppose that the photocurrent will be much larger than the dark current: i ph i d ; when estimating the minimum detectable signal, we suppose that the photocurrent will be much smaller than the dark current: i ph i d, i.e. dark shot noise dominates over signal shot noise. The minimum detectable signal, N ph,min, is the one for which the signal to noise ratio equals one, i.e. when SNR 1. We do not consider here the ADC quantization noise, which will be later designed in such a way that its noise contribution can be neglected with respect to the dark shot noise and reset noise. We get: σ dark,n qid t int q 3.5 electrons. 3

and Hence: ktcpd σ reset,n 8.3 electrons. q N ph,min σ tot,n σ 2 dark,n + σ2 8.9 electrons. reset,n We should now determine the maximum signal, in terms of charge, that can be accumulated by the pixel. The integrative method of gathering photocurrent is based on the capacitance of the photodiode. The capacitance, in turn, is based on the dopings (set by the process used in sensor manufacturing), the pixel area (set during pixel layout), and the bias voltage (an operating parameter). The size of this capacitance creates a limit on the total amount of charge a pixel can hold during integration. When considering the case of the 3T APS, assuming that all gate-source DC voltages can be neglected, as the maximum variation of the photodiode voltage is, saturation is avoided as long as Q ph C PD <. The full-well charge, FWC, or the maximum detectable signal, Q ph,max, can be thus estimated as the product of C PD and the maximum voltage swing across the photodiode, : i.e. Q ph,max C PD 3.3 V 0.42 ff 1.38 10 15 C, N ph,max Q ph,max q 8650 electrons. Said in other words, the pixel is initially reset at the supply voltage V RST ; during the integration phase, the voltage linearly decreases down to a certain value: ( ) iph + i d V PD (t int ) V PD C int t int. In this condition, if the diode voltage falls below 0 V, the pixel saturates. When the pixel saturates - see e.g. the blue (the steepest) curve in Fig. 2 - the output voltage is no longer a valid signal. The dynamic range can now be easily calculated: DR Q ph,max 1.38 10 15 C Q ph,min 1.43 10 18 C N ph,max 8650 electrons 965 59.7 db. N ph,min 8.9 electrons We can write the complete expression of the dynamic range of our sensor: DR Q ph,max C PD Q ph,min qid t int + ktc PD Some considerations (see Fig. 3): ɛ Si A pi xel F F x dep q J d A pi xel F F t int + kt ɛ Si A pi xel F F x dep. 4

Figure 2: Anode voltage of the photodiode in a 3T topology. The four curves correspond to increasing photocurrents. The blue one experiences pixel saturation. the dynamic range is independent from the signal, i.e. it is an intrinsic property of the sensor; note that the dynamic range is the same for all the pixels, while the signal-tonoise ratio can change across different pixels; the dynamic range depends on the integration time: the longer the exposure time, the poorer the dynamic range; the maximum dynamic range is thus obtained for low integration times, when q J d A pi xel F F t int σ 2 reset ; further decreasing the integration time has no effect on the dynamic range; the dynamic range improves with the square root of the area, i.e. bigger pixels with larger overall area and fill factor are better; the dynamic range is technology dependent, as the dark current density J d depends on the quality of the silicon substrate; the dynamic range improves when increasing the supply voltage. Fig. 3 reports the graphical solution of the dynamic range as a function of the integration time, for three different diode areas. The just calculated dynamic range (59.7 db) turns out to be close to the maximum dynamic range of the sensor, which can be calculated for short integration times, i.e. when assuming the dark current shot noise negligible, i.e. when reset noise dominates: DR max DR (t int 0) ɛ Si A pi xel F F x dep kt ɛ Si A pi xel F F x dep kt C PD 8650 electrons 1050 60.4 db. 8.3 electrons 5

Figure 3: Dynamic range as a function of the integration time, for different pixel areas. For comparison, the dynamic range of the human eye is around 90 db, while real world scenes have dynamic ranges far greater than 100 db. This is the reason why a lot of research is put into finding strategies for high dynamic range (HDR) digital imaging. PART 2: CHOICE OF THE ADC The analog-to-digital converter (ADC) is used to convert the acquired analog data into the digital domain. The maximum digital level of an analog-to-digital converter should correspond to the maximum analog voltage swing, i.e.: V re f,adc 2 N bi t LSB, where N bi t is the number of bits of the ADC and LSB is the least significant bit, expressed in volts: LSB V re f,adc 2 N, bi t An ADC with a high number of bits enables low quantization noise, but the raw output image requires more space in the storing memory. A possible way to choose the ADC resolution is to make the quantization noise just lower than the analog noise given by the pixel itself. As the minimum noise condition occurs for very short integration times, were reset noise 6

dominates, we can impose Hence: from which one gets σ quant,v LSB 12 σ reset,v. V re f,adc 2 N bi t 12 N bi t > log 2 ( 2 N bi t 12 σ reset,v, 12σreset,V ) 8.24. We can then choose an ADC with 9 bits. We can calculate the corresponding quantization noise in terms of number of electrons, as σ quant,n V re f,adc 2 N bi t 1 C diode 4.9 electrons. 12 q As desired/expected, this noise contribution is slightly lower than the previously-calculated reset noise. PART 3: MAXIMUM SIGNAL-TO-NOISE RATIO We are now interested in finding the maximum signal-to-noise ratio that can be obtained at the integration time of 10 ms, i.e. assuming a certain photocurrent for which the pixel gets close to saturation with a 10 ms integration time. We can write the expression of the signal-to-noise ratio for the maximum signal Q ph,max : SNR max Q ph,max Q ph,max Q ph,min q ( ). i ph,max + i d tint + ktc PD Since we are dealing with the maximum SNR, i.e. with big signals, we can reasonably assume that, in this situation, the dominant noise contribution is given by the signal shot noise. Hence, Q ph,max SNR max Q ph,max Qph,max N ph,max 8638 92.9 39.4dB. qi ph,max t qqph,max q int The maximum signal-to-noise ratio is proportional to the square root of the maximum number of electrons N el,max that can be collected by the photodiode. This is an expected result. As signal shot noise dominates, noise distribution follows Poisson statistics: given a certain signal N, its variance is equal to the signal itself, σ 2 N N, i.e. σ N N. The maximum signal-to-noise ratio thus increases with the supply voltage and with the diode area (and with the fill factor, as well). 7

The maximum signal-to-noise ratio does not depend on the integration time. The complete graph of the signal-to-noise ratio as a function of the photocurrent is represented in Fig. 5. The dynamic range can be evaluated from this graph by considering the x-axis distance between the two points were the SNR goes to 0 db (the first one refers to the minimum detectable signal, the second one refers to pixel saturation, i.e. the maximum signal). Figure 4: SNR as a function of the photocurrent, for two integrations times (10 and 100 ms). PART 4: DEPLETION CAPACITANCE EFFECT Up to now, we assumed that the width of the depletion region and therefore the depletion capacitance of the photodiode, on which the charge is integrated, is constant (x dep 1 µm). If the voltage variation V PD ( i ph + i d ) tint /C PD is small, with respect to, this assumption is correct. Otherwise, a more correct model should take into account the dependence of the depletion region width to the reverse bias voltage: x dep 2ɛ 0 ɛ r (V PD + ) qn A, 8

where V PD V PD and is the Silicon built-in voltage (typically about 0.7 V). This results in a photodiode capacitance C PD : C PD ɛ 0ɛ r A qɛ Si N A A x dep 2(V PD + ) C 0, 1 + V PD where C 0 is the photodiode capacitance with V PD 0 V applied (different from the capacitance computed at reset with V PD that we always use!). We can integrate the capacitor relationship to find the exact charge integrated across C PD : 0 0 C 0 Q ph,max C (V PD ) dv PD 1 + V PD dv PD We substitute x V PD / to compute the integral more easily and we get to the final result: 0 Q ph,max 2C 0 (1 C 0 V 0 bi dx C 0 1 + x 1 + ). dx 1 + x C 0 [2 1 + x] 0 The result is a negative number, which reflects the fact that the voltage across the diode decreases. We can consider its absolute value. With this result, we can quantify the percentage error we commit on the maximum charge C when considering a constant capacitance equal to C PD,const 1+VDD 0 : / er r or Q max,appr ox Q max,real C 0 1 +VDD / ) 2C 0 (1 + 1 ( ) 0.7, 2 1 + 1 + 1 computed with 3.3 V and 0.7 V. This result means that the maximum signal that we computed is actually 70% of the maximum signal a real (non-linear) photodiode would reach. Therefore, without approximation we would get a DR larger by about 20 log 10 (1/0.7) 3 db than what we computed a few pages ago. Bear in mind that the parasitic capacitance due to the interconnections, in parallel with the diode, is linear: this mitigates the discrepancy that we have described. The parasitic capacitances due to MOS transistors add further non-linear contributions that were not considered in this description. Now you can understand why we always stick to the constant-capacitance approximation! 9

Figure 5: Non-linear C (V ) function of a photodiode. The area below the function represents the charge integrated onto the photodiode capacitance. The blue area represents the charge computed with the constant-capacitance approximation. The orange area represents the error committed with such approximation. The sum of the two areas is the actual maximum signal charge. 10