Introduction Delay-Locked Loops DLL overview CMOS, refreshg your memory Buildg blocks: VCDL PD LF DLL analysis: Lear Nonlear Lock acquisition Charge sharg DLL Applications Phase-Locked Loops PLL Applications Outle Paulo.Moreira@cern.ch Delay-Locked Loops 1
Clock skew control Clock skew control Why Delay-Locked Loops? IC Int. CLK The DLL automatically nulls the skew between these two pots Q Output pad Ext. CLK Clock pad DLL clock re Clock buffers and terconnects troduce delay External clock DLL delay + Clock buffers + Clock re delay = Clock period Phases 0 and 2π are distguishable Internal clock Phase aligned Output data Output data registers delay Paulo.Moreira@cern.ch Delay-Locked Loops 2
DLL Block Diagram 1 st order Delay-Locked Loop functional blocks Voltage Controlled Delay Le (VCDL): Takes the reference clock as an put and delays it by some amount D. The delay D is function of a control voltage D(V control ). Sometimes the control quantity can be a current. In this case we have a Current Controlled Delay Le (CCDL) We will assume that the higher the voltage (or the current) the shorter will be the propagation delay through the delay le. Phase Detector (PD): Compares the phase of the signal at the put and put of the VCDL. Dependg on the type, produces an error signal that: It is proportional to the phase difference between the put and put phases; It just gives an dication on the sign of the phase error (bang-bang detector). Loop filter (LF): Elimates the high frequency components of the error signal: It can be implemented as: An RC low-pass filter An active low pass filter A charge-pump and a capacitor Paulo.Moreira@cern.ch Delay-Locked Loops 3
DLL Buildg Blocks We will describe details and possible implementations of the DLL buildg blocks: Voltage Controlled Delay Le (VCDL) Phase-Detector (PD) Loop Filter (LF) All the circuits we will discuss are CMOS circuits. Before proceedg to the circuit details, we need to refresh the basic concepts on the operation of a MOS transistor from the circuit pot of view. CMOS: C: complementary: N and P type transistors M: Metal gate: Polysilicon modern technologies O: Silicon dioxide dielectric S: Semiconductor NMOS: Charge carried by electrons Turned on by gate voltages positive relation to the source PMOS: Charge carried by holes Turned on by gate voltages negative relation to the source Paulo.Moreira@cern.ch Delay-Locked Loops 4
CMOS Transistors Simple Model In saturation: Gate-to-source capacitance Voltage controlled current generator between source and dra Lear region: A gate capacitance Voltage controlled resistor between the source and dra Cutoff region: Gate capacitance Infite resistance between source and dra Circuit: Dra of a transistor is loaded by the gate of the next Next gate represents a capacitance to the previous transistor. Dra current used to charge (or discharge) the gate capacitance of the followg transistor I ds C W μ ox V 2 L gs T ( V ) 2 In saturation D G I ds D G V ds V gs C gs I V ds V gs S S S S Paulo.Moreira@cern.ch Delay-Locked Loops 5
The Voltage Controlled Delay Le (VCDL) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 6
Intrsic Delay CMOS Circuits Ideal MOS Time it takes to discharge C from V dd to V dd /2 VIN VGS I (VGS-VT) 2 C Δt = C I V 2 dd μ C C V ox Assumg V T 0 Assumg V T 0 dd L W V dd VIN 0 t VOUT V dd delay 50% level 0 t Paulo.Moreira@cern.ch Delay-Locked Loops 7
Common-source configuration: CMOS Inverter NMOS can only discharge (pull-down); PMOS can only charge (pull-up); V dd Both P and N transistors are thus needed. CMOS verter: No static power consumption. Mobility electrons > mobility holes: PMOS transistors are weaker than NMOS. To compensate: C L W p /W n = μ n /μ p 3/1 (for L n = L p, typically mimum length digital circuits). What s the best way to control the verter delay: V dd? C L? None of the two! Paulo.Moreira@cern.ch Delay-Locked Loops 8
The Starved Inverter V dd I up Controllg I up controls the chargg time Δt up = C I up V 2 dd Switchg transistor not limitg C L Controllg I down controls the dischargg time Δt down = C I down V 2 dd I down Delay as short as possible: I up = I down = max Switchg transistors limitg. Δt = C I V 2 dd C μ C V ox dd L W Paulo.Moreira@cern.ch Delay-Locked Loops 9
Biasg the Starved Inverter V dd 1:N I up I bias = I up /N C L V control I down Paulo.Moreira@cern.ch Delay-Locked Loops 10
Makg Sure it Will Work Can we run the starved verter fitely slow?. No, must have: trise = tfall < m(pulse width) V dd put Pulse too short put Filtered by the starved verter I up C L Pulse wide enough put 1 0 V control I m put 1 0 Pulse appears delayed at the put I m prevents t rise and t fall from becomg too long Paulo.Moreira@cern.ch Delay-Locked Loops 11
Voltage Controlled Delay Le V dd In In a a real real implementation implementation these these nodes nodes troduce troduce poles poles the the VCDL VCDL transfer transfer function. function. Care Care must must be be taken taken so so they they are are at at high high frequencies frequencies not not to to disturb disturb the the DLL DLL dynamic dynamic behavior. behavior. I up V control I m t d t f(v control ) = vcdl V control d = f(v control ) = K vcdl V control (lear approximation valid around the workg pot) (lear approximation valid around the workg pot) Paulo.Moreira@cern.ch Delay-Locked Loops 12
Differential Delay Cell Advantages: Insensitive to common-mode; Signal and the Inverted signal available. Constant power consumption: low switchg noise Disadvantages: Consumes static power; Half of the tail current used to charge/discharge the load; Differential to sgle ended converter required to terface with CMOS logic V dd 1 1 1 - + + I up V control I m 1 2 Paulo.Moreira@cern.ch Delay-Locked Loops 13
The Phase Detector (PD) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 14
XOR: A Simple Phase Detector put Output lags the put by π/2 (T/4) VCDL put signal VCDL put signal error put error Φ err = <Phase-detector put> Φ err = <Phase-detector put> <error> = ½ V dd Output lags the put by π/4 (T/8) put put error <error> = ¼ V dd put Output lags the put by 3π/4 (3T/8) The The phase-error phase-error or or phase phase difference difference is is not not the the stantaneous stantaneous value value of of the the phase phase detector detector put put but but its its average average value. value. That That is is one one of of the the reasons reasons why why the the loop-filter loop-filter is is required. required. put error <error> = ¾ V dd Paulo.Moreira@cern.ch Delay-Locked Loops 15
XOR Uncertaty VCDL put signal VCDL put signal error Output lags the put by π/4 (T/8) put Output lags the put by 3π/4 (3T/8) put put error Output leads the put by π/4 (T/8) put put error Output leads the put by 3π/4 (3T/8) put put error put error The phase detector can not distguish between these two conditions. Neither between these two conditions. Paulo.Moreira@cern.ch Delay-Locked Loops 16
Non-Lear and Limited Range <error> [Volts] K pd dv = < 0 dφ ½V dd V dd K pd dv = > 0 dφ <phase error> [rad] 0 π ¾ π 2π Output phase Leads 0 π/2 Output phase Lags Slope: K pd, [V/rad] or [V/s]; Slope sign depends on the operation region: Negative ga Positive feedback; Positive ga Negative feedback; Ga version occurs at teger multiples of π; XOR phase detector must work with a static phase difference of π/2; For the XOR, a phase difference equal to π/2 is zero error phase ; The type of phase detector dictates the static phase difference. Paulo.Moreira@cern.ch Delay-Locked Loops 17
XOR Non-Idealities XOR ripple is at twice the operation frequency: Advantage for RC filterg; A problems if a charge-pump filter is used. error XOR drawback: sensitive duty-cycle; Different duty-cycles Same phase difference error Different averages Paulo.Moreira@cern.ch Delay-Locked Loops 18
More Non-Idealities error error error Ga saturation (for 25% duty-cycle) 0 π Duty-cycle distortion also causes saturation of the phase detector transfer function Paulo.Moreira@cern.ch Delay-Locked Loops 19
The DFF Phase Detector VCDL put signal D Q error Sign formation only: No phase error magnitude formation; It distguishes early or late only; VCDL put signal It is called a bang-bang phase detector. Output lags the put put Loop operation: When lock the phase change occurs virtually every clock cycle and the average phase error becomes zero. Its advantages are: put error simplicity of operation; Operation possible at the maximum FF operation frequency; Mimum pulse width 1/f; Output leads the put put The phase range spans from π to +π. Insensitive to duty-cycle distortion the CK put (however: duty-cycle distortion on the D put creates asymmetry the transfer function) put v dd error π 0 π Paulo.Moreira@cern.ch Delay-Locked Loops 20
DFF PD Implementation Carefully design one. SR2 Dummy gate SR3 To avoid phase errors and Metastability: Internal nodes same fan; Gates the same drivg capability; Every two gates the same latch same fan-; The latch SR1 is critical should reach its fal state as fast as possible; Decision a fraction of the reference clock period Otherwise creased jitter. D Lay is critical for operation: Device matchg; Dummy gate SR1 Large area devices; Lay as symmetrical as possible; Keepg the wire loadg identical on correspondg nodes. Paulo.Moreira@cern.ch Delay-Locked Loops 21
The Loop Filter (LF) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 22
A simple loop filter: RC Low-pass VCDL put signal VCDL put signal VCDL control voltage V control = K pd <phase error> V control = K pd <phase error> K pd = V dd /π [V/rad] K pd = V dd /π [V/rad] The simplest possible filter is an RC low-pass filter; Output voltage controls the VCDL. Filter bandwidth: a few or several decades lower than f ref ; In steady state conditions, the filter DC put voltage is proportional to the phase error. Advantage: Simplicity Disadvantage: Corrective action can only be achieved at the price of a phase offset. The phase offset value depends on the phase detector ga: Small ga K d large phase offset! Phase detector ga is dictated by V dd Paulo.Moreira@cern.ch Delay-Locked Loops 23
Fite DC Ga is a Disadvantage T 1 π/2 T 2 > π/2 T 2 < T 1 <V control > = ½ V dd <V control > > ½V dd VCDL for a reference signal with period T 1. propagation delay T 1 /4 achieved exactly at V dd /2; Reference period changed to T 2 < T 1 To run with a shorter propagation delay a higher VCDL control voltage is necessary; With the RC filter, higher voltage can only be obtaed at a cost of an extra phase lag; This is undesirable it troduces an error the VCDL propagation delay. The error can be reduced by creasg the open-loop ga: K = K pd K lf K vcdl. (K lf is the filter ga, 1 for the passive RC filter). Paulo.Moreira@cern.ch Delay-Locked Loops 24
Improvg the RC Filter Increasg the open-loop ga reduces the phase offset: Increasg Vdd creases K pd (K pd = V dd /π): Not a practical solution; The ga crease would be small. More effective: Add a ga stage between the filter and the VCDL: Increase the ga of the VCDL (K vcdl ) Draw backs: Small V cnt fluctuations converted large variations of the VCDL propagation delay (jitter); Secondary poles might result a badly behaved transient response or even stability. The XOR phase detector and the passive RC filter are thus not the favorite choice for tegrated DLLs VCDL G To To reduce reduce the the phase phase offset, offset, add add ga ga or or crease crease K vcdl vcdl Paulo.Moreira@cern.ch Delay-Locked Loops 25
Capacitor: A Current Integrator Consider what happens when a current is fed to a capacitor: The voltage across the capacitor (V) is simply the time tegral of the current (I) beg fed to the capacitor: V t 1 = C () t I() t dt + V0 0 We can thus easily tegrate the phase error if we feed to a capacitor a current that is proportional to the phase error measured by the phase detector: t Φ 0 err t I ( t) Φ ( t) 1 C () dt I() t t 0 err dt I V Paulo.Moreira@cern.ch Delay-Locked Loops 26
Active Loop-filter: Charge-Pump + Capacitor I cp VCDL D Q late V control V control VCDL early I cp V cap error Late = lag sign(φ err ) = 1 Early = lead sign(φ err ) = -1 V t Icp ( t) = Vcap( t) = sign( Φerr ( t)) dt V C control + 0 0 Paulo.Moreira@cern.ch Delay-Locked Loops 27
Charge-Pump for Bang-Bang Detector M1: current sk, M2: current source; M3 and M4: switches: Alternatively closed and opened: V dd Current always flows to or of the filter capacitor (never directly between V dd and ground); M2 Reference leads: M4 closed, M3 opened Control voltage creases. VCO leads: error M4 V control M3 closed, M4 opened Control voltage decreases Keep sk and source currents well matched: M3 C mimize static phase error; Charge sharg effects need be controlled (discussed later). I cp M1 Paulo.Moreira@cern.ch Delay-Locked Loops 28
The Delay-Locked Loop Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 29
Bang - Bang Operation Overview D Q Late Q Early V control Early Late Late Late Early Late Paulo.Moreira@cern.ch Delay-Locked Loops 30
Bang-Bang Operation Tradeoffs Trackg jitter: The loop trackg behavior troduces jitter: In lock put phase constantly oscillates back and forward around the phase of the reference signal: It is a result of no phase error magnitude formation. Possible to reduce the loop trackg jitter to significant levels; Other jitter sources: Thermal and shot noise; Substrate noise; Power supply noise. Tradeoffs: Optimization for low-jitter: Increase the loop-capacitor C; Decrease: I cp and K vcdl. Optimization for fast-lock: Decrease the loop-capacitor C; Increase: I cp and K vcdl. Optimization for low-jitter and fastlock: It is possible to optimize for both: Use a large I cp durg lock-acquisition; Use a small I cp after lockg. Optimization agast substrate and power supply noise: Same as for fast-lock; Paulo.Moreira@cern.ch Delay-Locked Loops 31
DLL: lear analysis Loop filter: Charge-pump + capacitor. Phase detector: Considered Lear signal proportional to the phase error. Phase detector put: Pulse of duration proportional to the phase error (e.g. ΔT(high)-ΔT(low) an XOR phase detector). Contuous time approximation: Valid for bandwidths a decade or more below the operatg frequency. (Keep md that DLLs are fact nonlear devices.) A sgle pole is present the loop filter: The DLL is a 1 st order network. Combation charge-pump and loopcapacitor: Acts as a perfect tegrator; Modeled as an tegrator. VCDL PD dt Paulo.Moreira@cern.ch Delay-Locked Loops 32
DLL Modelg Choice of variables: DLL response formulated terms: Input delay; Output delay; Output delay: The VCDL delay: D O (t) or D O (s) Input delay: The delay to which the phase detector compares the put delay: D I (t) or D I (s) Note that D I (t): It is phase detector dependent; It s frequency dependent; Δt DI ( s) DO ( s) D O (s) PD = T Δt T T Phase detector put is active durg this fraction of the reference period dt V cont Δt = T Icp s C D O ( s) = K V ( s) vcdl VCDL cont (s) V cont Paulo.Moreira@cern.ch Delay-Locked Loops 33
DLL Transfer Function D O (s) PD 1 s Phase error D O ( s ) = [ D ( s ) D ( s )] I T O I cp s C K vcdl Charge pump Duty-cycle Control voltage VCDL propagation delay H ( s ) = D D O I ( s ) ( s ) = 1 1 s + ω n The The closed closed loop loop transfer transfer function function is is 1 1 st st order order It It is is characterized characterized by by the the natural natural frequency frequency ω n n ω n = I cp T K C vcdl Paulo.Moreira@cern.ch Delay-Locked Loops 34
The DLL is a 1 st Order System ω n = I cp T K ω n naturally tracks the reference frequency. C vcdl D fal d D( t) dt t =0 = D fal τ Designg a DLL it is equivalent to choose its natural frequency ω n : Choose I cp and C. K vcdl fixed by the VCDL design and technology parameters (some degree of control but not much). T is fixed by the operation frequency/frequencies. Sce the system is 1 st order it is herently stable: Make sure the higher order (unwanted but unavoidable poles) are at least 10 times higher that ω n. τ = 1 ω n The closed-loop behavior is similar to that of a 1 st order low-pass RC filter: Settlg to 2% t 4τ Settlg to 0.1% t 7τ Fast settlg requires large ω n : Trades off agast low trackg jitter. ω n might start approachg the higher order poles. t Paulo.Moreira@cern.ch Delay-Locked Loops 35
DLL Design The parameters: I cp C ω n = K vcdl are technology, temperature and supply voltage dependent ω n would track the operation I cp T K C frequency (i.e. proportional to 1/T) if the other parameters were absolutely constant: Self-biasg techniques can make ω n track the operation frequency over several decades: see Maneatis 1996 vcdl Example: F = 100 MHz T = 10 ns I cp = 1 μa C = 100 pf K vcdl = 2 ns/v This leads to: ω n = 2 krad/s τ = 0.5 ms Notice that: The DLL bandwidth is many orders of magnitude lower than the operation frequency. When locked to a low jitter clock signal this PLL will display low trackg jitter. A VCDL, when subjected to substrate or power supply noise, will generate jitter. Under such circumstances, a DLL with such a low bandwidth will be effective trackg the put phase and thus suppressg its own jitter. Paulo.Moreira@cern.ch Delay-Locked Loops 36
Bang-Bang DLL Nonlear Analysis When a DLL uses a DFF as the phase detector, the contuous time approximation can not be used. Simple expressions can be found for: The response to a period step; The trackg jitter. Phase step: The new period is 2/3 T i < T f < 2 T i : DLL will rega lock to the new phase; The VCDL delay will ramp to the new value. The new period is side the above bounds: The Phase-Detector will give the wrong phase formation and the DLL will lose phase lock. Period T itial d D( t) dt = K Reference The DLL will try to catch the new period at a rate given by: dv dt control vcdl = Units: [rad/s] or [s/s] VCDL K vcdl I C cp T fal t Example: Usg the previous example the trackg slope is: 20 ns/ms Paulo.Moreira@cern.ch Delay-Locked Loops 37
Frequency Step f 2 > f 1 T 1 The DLL is locked to the reference signal (period T 1 ) T 2 < T 1 Phase is detected late, the VCDL delay is gog to be decreased. Immediately after the frequency step (period T 2 < T 1 ) the VCDL delay is too big and the PD will activate the late signal until the de VCDL propagation delay becomes equal to T 2 VCDL put period VCDL propagation delay VCDL D Q Late Q Early C.P. Paulo.Moreira@cern.ch Delay-Locked Loops 38
Frequency Step f 1 > f 2 T 1 The DLL is locked to the reference signal (period T 1 ) T 2 > T 1 Immediately after the frequency step (period T 1 < T 2 ) the VCDL delay is too short and the PD will activate the early signal until the de VCDL propagation delay becomes equal to T 2 Phase is detected early, the VCDL delay is gog to be creased. VCDL D Q Late VCDL put period VCDL propagation delay Q Early C.P. Paulo.Moreira@cern.ch Delay-Locked Loops 39
Frequency Step: Limit Values T 1 T 1 T 2 T 2 If T 2 < 2 / 3 T 1 the phase detector will activate the early put stead of the late. The delay will crease stead of decreasg. If T 2 > 2 T 1 the phase detector will activate the late put stead of the early. The delay will decrease stead of creasg. Paulo.Moreira@cern.ch Delay-Locked Loops 40
T Bang-Bang Trackg Jitter Jitter: Uncertaty on the position of the fallg and risg edges. Seen a scope as thick traces on the risg and fallg positions. Jitter Ideally every clock cycle the phasedetector should alternate between an early and a late decision. In practice, due to charge-pump unbalance or jitter, it is very likely that the PD decision will be frequently mataed durg two consecutive clock cycles to either side. The mimum P-P trackg jitter is thus given by: d D( t) 4 T = 4 K dt vcdl I cp C T late early I ΔVcont = 4 C cp T ΔV cont Example: Usg the trackg slope from the previous example: J pp = 4 (20 ns/ms) (10 ns) J pp = 0.8 ps The trackg jitter can be thus made to be very small. The jitter is likely to be domated by thermal, supply and substrate noise. Paulo.Moreira@cern.ch Delay-Locked Loops 41
DLL Lock Acquisition Typical Bang-Bang DLL startup procedure: 1. Set the VCDL to its mimum value (maximum control voltage) 2. Force the VCDL delay to crease until the phase detector gives a consistent early dication (e.g. 32 consecutive early detections) 3. Once the PD consistently dicates early, pass the control of the loop to the phase detector which will fally take the DLL to lock. 1 st phase VCDL set to its mimum delay Here the PD wrongly dicates late 2 nd phase Here, due to jitter, the PD sometimes gives the correct and sometimes the wrong dication 3 rd phase Paulo.Moreira@cern.ch Delay-Locked Loops 42 The PD is now a safe zone, it correctly and consistently dicates early.
Charge Sharg Charge-pumps perform almost like ideal tegrators however charge sharg might degrade their performance. This node charges to V dd when M4 is open V dd M2 When M4 closes V control jumps of: ΔV cont Cd 2 = C + C d 2 ( V dd V cont ) late M4 M3 C d2 V control C When M3 closes V control jumps of: ΔV cont Cd1 = C + C d1 V cont Notice that: The voltage jump is proportional to the control voltage itself; proportional to C d1 and C d2; verse proportional to C; (usually C>> C d1 or C d2 ): I cp M1 C d1 Example: If C = 100 pf, C d1 = 10 ff and V control = 1V: ΔV control = -100 μv Compare with: I cp T/C = 100 μv This node discharges to gnd when M3 is open Paulo.Moreira@cern.ch Delay-Locked Loops 43
Charge Sharg Control V dd Charge sharg is elimated. I cp M2 M4 Clock feed-through is present through C gd of M5 and M6. However the voltage swg at the gate of these transistors is relatively small M6 late V control I cp M3 M1 M5 C Voltage Voltage on on this this node node never never rises rises much much above above V dd -V th. So turn-on is relatively fast. dd -V th. So turn-on is relatively fast. Voltage Voltage on on this this node node never never drops drops much much below below V th. So turn-on is relatively fast. th. So turn-on is relatively fast. RC time constant Paulo.Moreira@cern.ch Delay-Locked Loops 44
Delay cha feed through Parasitic C dg troduces ripple on the control les. In lock the raisg and fallg edges effects cancel each other. V dd I up To mata symmetry, buffer the dummy cell control les. V control I m Paulo.Moreira@cern.ch Delay-Locked Loops 45