Konstruktion av Vippor och Latchar

Similar documents
ELCT201: DIGITAL LOGIC DESIGN

Sequential Logic Circuits

Chapter 4. Sequential Logic Circuits

Topic 8: Sequential Circuits

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

Introduction to Digital Logic

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Sequential Circuits Sequential circuits combinational circuits state gate delay

Sequential vs. Combinational

Synchronous Sequential Logic

Latches. October 13, 2003 Latches 1

Chapter 14 Sequential logic, Latches and Flip-Flops

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

Topic 8: Sequential Circuits. Bistable Devices. S-R Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4 - B.

P2 (10 points): Given the circuit below, answer the following questions:

CPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner

Chapter 3 Digital Logic Structures

Integrated Circuits & Systems

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Sequential Circuit Analysis

Chapter 7 Sequential Logic

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EET 310 Flip-Flops 11/17/2011 1

EE141- Spring 2007 Digital Integrated Circuits

Lecture 7: Sequential Networks

Digital electronics form a class of circuitry where the ability of the electronics to process data is the primary focus.

Problem Set 9 Solutions

Chapter #6: Sequential Logic Design

Overview of Chapter 4

Lecture 17: Designing Sequential Systems Using Flip Flops

Unit 7 Sequential Circuits (Flip Flop, Registers)

Lecture 3 Review on Digital Logic (Part 2)

ALU A functional unit

I. Motivation & Examples

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

ALU, Latches and Flip-Flops

Lecture 7: Logic design. Combinational logic circuits

CS61C : Machine Structures

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Digital Integrated Circuits A Design Perspective

Gates and Flip-Flops

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CS61C : Machine Structures

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review.

Using the NOT realization from the NAND, we can NOT the output of the NAND gate making it a NOT NOT AND or simply an AND gate.

Digital Circuits and Systems

Module - 19 Gated Latches

Digital Integrated Circuits A Design Perspective

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Laboratory Exercise #8 Introduction to Sequential Logic

SRC Language Conventions. Class 6: Intro to SRC Simulator Register Transfers and Logic Circuits. SRC Simulator Demo. cond_br.asm.

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

Synchronous Sequential Circuit

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

Mealy & Moore Machines

Digital Integrated Circuits A Design Perspective

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

Sequential Logic (3.1 and is a long difficult section you really should read!)

GMU, ECE 680 Physical VLSI Design

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

Adders, subtractors comparators, multipliers and other ALU elements

9/18/2008 GMU, ECE 680 Physical VLSI Design

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Sequential Logic Worksheet

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

Hold Time Illustrations

CS/COE0447: Computer Organization

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab

Digital Design. Sequential Logic

Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts

ELCT201: DIGITAL LOGIC DESIGN

Chapter 7. Sequential Circuits Registers, Counters, RAM

CPE100: Digital Logic Design I

Fundamentals of Boolean Algebra

UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables

CPE100: Digital Logic Design I

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Time Allowed 3:00 hrs. April, pages

Lecture 24. CMOS Logic Gates and Digital VLSI II

EE141Microelettronica. CMOS Logic

CS/COE0447: Computer Organization

I. Motivation & Examples

ELEN Electronique numérique

6. Finite State Machines

UNIVERSITY OF WISCONSIN MADISON

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

Transcription:

Konstruktion av Vippor och Latchar Datorarkitektur 1 (1DT038) Fördjupning November 2009 karl.marklund@it.uu.se

Om du läser IT (1DT038) är detta material överkurs du bör dock redan vara bekant med hur det går till att konstruera minnesceller (vippor och latchar) mha grindar från kursen i elkretsteori.

A simple cominational circuit Q = 1 when at least one of A and B equals 1 Q = 1 when both A and B equal 0 A B Q Q 0 0 0 1 0 1 1 0 1 0 1 0 Q = 0 when at least one of A and B equals 1 1 1 1 0 Q = 0 when at least one of A or B equal 1

When Q 0 is true, the bottom NOR-gate actcs like an inverter (no matter the value of S) and Q 1 becomes false... What happens if we change to true here?... which becomes the input to the top NOR-gate Q 1 = true = Q 0 (Q is unchanged) A pair of cross-coupled NOR-gates. Due to the feedback loop, this is no longer a cominational circuit - it s an sequential circuit.

What happens if we change back to false again? Asserting R will give Q = false...... which becomes the input to the bottom NORgate Q = true... which becomes the input to the upper NORgate Q = false

Deasserting R won t change anything, Q remains false no matter the value of R. What happens if we change to true here? When both R and S are deasserted, the cross-coupled NOR-gats remembers the values of Q and Q

What happens if we change S back to false?... which becomes the input to the top NOR-gate Q = true Asserting S gives Q = false...

Again, when both R and S are deasserted, the crosscoupled NOR-gats remembers the values of Q and Q Deasserting S won t change anything...

R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1?? Logisim DEMO

R S Q n+1 Q n+1 both zero 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 0 0 Overriding the memory feedback action. What happens if both R and S drops (voltage change is not instanteneous) to zero simultaneously?

R drops first...... resulting in Q = 1 S drops first...... resulting in Q = 0

An example of sequential logic: The output depends not only on the present input but also on the history of the input. R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 Restricted If both R and S drops to zero at the same time metastability

R S Q Q R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 Restricted A SR Latch (Set and Reset Latch) can store 1-bit of data.

SR Latch Setting C to 1 will only reset Q if D is 0 at the same time. D Latch D can only function as Set when C (clock/ enable) is true.

C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change 1 0 0 1 Reset 1 1 1 0 Set

C Q A D Latch (Data Latch) can store 1-bit of data. D Q C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change 1 0 0 1 Reset 1 1 1 0 Set

R S Q Q A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time. SR Latch R S Q n+1 Q n+1 0 0 Q n Q n 0 1 1 0 1 0 0 1 1 1 Restricted A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. C D Q Q D Latch / Flip-Flop C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change 1 0 0 1 Reset 1 1 1 0 Set

C D Q Q D Latch C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change 1 0 0 1 Reset 1 1 1 0 Set D C Q When the latch is open (C=1) Q follows D (a transparent latch)

Changing C back to zero The output Q of the master latch follows input D when clock is high (which closes the slave latch).

Changing C back to zero opens the slave latch taking the Q output of the master latch as D input.

D C Q Output Q only changes on falling clock edges (non transparent).

C D Q n+1 Q n+1 Comment non-falling X Q n Q n No Change 1 1 0 Set 0 0 1 Reset

The triangle indicates an edge-trigged latch a flip flop. C Q A D Flip-Flop The inversion bubble on the clock input indicate a falling-edge triggered flip-flop D Q C D Q n+1 Q n+1 Comment non-falling X Q n Q n No Change 1 1 0 Set 0 0 1 Reset

Logisim DEMO 8 bit D flip-flop register

Clock 8 D Flip-Flops used to form a 8 bit register. 0001 0011 2 A falling edge trigged D flip-flop C Q D Q

Clock goes to high... output remains unchanged. 0001 0011 2

Clock falls back to low... output equals input. 0001 0011 2

Changing input... does not affect ouput. 1000 1100 2

2024 © sciencedocbox.com Privacy Policy | Terms of Service | Feedback