ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email: Lynn.Fuller@rit.edu Department webpage: http://www.rit.eduu/kgcoe/microelectronic/ 4-25-2017 LowPowerCMOS.ppt Page 1
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INTRODUCTION CMOS is suppose to be low power because CMOS gates only draw current from the supply during switching. In steady state High or Low CMOS gates do not draw power (almost zero). This document will investigate Energy and Power used by a complex CMOS integrated circuit and propose methods for reducing power consumed by the circuit. Page 3
INTRODUCTION What is a complex integrated circuit. Answer: A big chip with many small transistors on it. The biggest chips could be as large as 1 by 1 and the small transistors could be 20nm gate lengths or smaller. Chip Area is: 1 x1 or 25.4mm x 24.5mm = 645 mm 2 Transistor size is : L=20nm and W = several times larger, plus room for drain and source, contact cuts and metal. This might be around 100nm x 100nm = 10,000 nm 2 A complex chip could have as many as #N transistors based on area: #N = Chip Area / Transistor Area #N = 645 mm 2 / 10,000 nm 2 = 645x1E12/10,000 = 64.5 Billion Transistors!! Page 4
INTRODUCTION Transistor count for selected microcontrollers. Name # s of Transistors Date Design Size Area Transistor Count" Wikipedia: The Free Encyclopedia. Wikimedia Foundation, Inc., Web. 25 April 2017. https://en.wikipedia.org/wiki/transistor_count Page 5
CMOS INVERTER CURRENT DURING TRANSITION Vout Imax =70uA Imin =0uA Vin Page 6
POWER MEASUREMENTS Power consumed by a micro circuit can be easily measured. Power = I V just measure I and V (while chip is operating) To compare chips of different sizes we can use power density. Power Density = Power / Chip Area Example: 5 volts, 10 amps, chip area = 1cm x 1cm P = 50 watts Power Density = 50 w/cm 2 Very Hot!! Page 7
COOLING MICROCHIPS Why is one chip cooled and not the others. Page 8
POWER DENSITY TRENDS CMOS is suppose to be low power. Power density surpassed hot-plate at 0.5um technology node. 1000 Nuclear Reactor Watts/cm 2 100 10 1 Hot Plate Pentium Pro Pentium i486 Pentium III Pentium II 1.5u 1u 0.7u 0.5u 0.35u 0.25u 0.1u 0.13u 0.1u 0.07u Fred Pollack, Intel Page 9
WE DEMAND HIGH SPEED COMPLEX CHIPS CMOS running at high speed with millions of active gates is needed to provide capabilities we demand: Java interpreter Text/Graphics processing Speech recognition Video decompression Protocols Encryption Handwriting recognition Games more.. Page 10
COOLING MICROCHIPS Chip Cooling is Expensive Page 11
POWER USED BY A CMOS INVERTER How Do we get to such high power densities? CMOS is suppose to be low power because CMOS gates only draw current during switching. Lets investigate a CMOS inverter first and maybe we can apply what we learn to more complex integrated circuits. First Review: Power (electrical) P = I V (watts) Power Density P = P / Area (watts/cm 2 ) Energy W = Power x Time (watt-seconds, joules) Charge storage in a battery Q = I t (amp-hours) note: battery voltage is known so Energy W = V Q Example: CR2032 (3 volt battery is rated at 200 ma-hr) it can deliver 720 coulombs of charge or 2160 joules of energy Page 12
POWER FOR INVERTER TRANSITION Vin +V 0 Vout +V t Q = CV I = Q/t = CV/t P = IV P = CV 2 /t Vin V+ I C Vout 0 I Imax 0 t t Each low to high transition is accompanied by a pulse of current from the V+ supply. Assume no current from V+ to ground when both transistors are on during switching. (current only to charge C) Page 13
SPICE OF INVERTER FOR PULSED INPUT Zoom in of output Transition waveforms on next page Page 14
SPICE OF INVERTER FOR PULSED INPUT Because there are internal capacitors connected from gate to drain (input to output) we see some spikes from capacitive feed through. We also see the voltage and current during the transition of the output. Lets find the average current per transition. Feed through I load Vin Output High to Low Transition Iave Feed through Vout Output Low to High Page 15
SPICE OF INVERTER FOR PULSED INPUT Current from power supply during the low to high transition is Iave = 1/t integral of i(t) dt Iave here ~ 50uA Current to the load capacitor Iave= ~ 10uA I supply I load and should equal CV/t =0.48fF 2.5/120ps=10uA Difference is current through both transistors during switching ~40uA Page 16
MATCHING RISE AND FALL TIME IS GOOD I in C1 Vout Wpmos = 1.25 x Wnmos Gate Rochester delay Institute is of the Technology time to get to 50% of the final value. td LTH = 604ps td HTL = 652ps Page 17
CURRENT COMPONENTS FOR CMOS INVERTER The current flows from the V+ to the capacitive load during the low to high transition, t LTH. That current is CV/t LTH. Current also flows from V+ through the PMOS and NMOS during switching when both transistors are on. Current also leaks through the reverse biased drain and source junctions to the substrate plus gate leakage. (assume small compared to the two currents above) Page 18
TOTAL POWER Supply Iave per transition = Iave Power per transition = Iave x V+ Load Capacitance = C Power to load only = C V 2 / t LTH Clock frequency = f Transitions/sec = some?% of possible transitions Number of gates = thousands or millions Total Power = combination of above Total Power = Iave x V x f x t LTH x?% x N Power to charge load capacitance only = C V 2 / t LTH x f x t LTH x?% x N Page 19
EXAMPLE POWER CALCULATION Example for 2um technology: Assume rise and fall time are matched thus I load will be matched and = 100uA. Iave from supply is 300uA per transition. Assume V+ = 3 volts, Load C = 0.028pF, clock f = 1Mhz, Transitions = 20% of clock, t LTH = 600ps, Number of gates N = 20 million Total Power = Iave x V x f x t LTH x 20% x N = 300u x 3 x 1M x 600p x 20% x 20E6 = 2.16 watts Power to charge load capacitance only = C V 2 / t LTH x f x t LTH x?% x N = 0.028p x 9 x 1M x 20% x 20 million = 1.01 watts Page 20
SUMMARY Power is an important design criteria 1. Reduce Vdd (at 28nm node Vdd ~0.5 volts) 2. Lower clock speed (not always possible) 3. Reduce transistor size 4. Minimize capacitances 5. Optimize and minimize gate delays 6. Use dynamic logic where appropriate Page 21
REFERENCES 1. Microelectronic Circuits, Sedra and Smith, 7 th edition. 2. More Page 22
HOMEWORK LOW POWER CMOS 1. If some gates used dynamic logic techniques it might be possible to reduce power by reducing current. Investigate and compare static CMOS gate versus dynamic logic gate for power. 2. Compare power for 2um technology with power for 200nm technology. Assume same number of gates. Show an example approximate calculation. Page 23