And device degradation Slide 1
Z. Guo, ISSSCC 2018 Inter-die Variation & Cell Failures
Failures in SRAM Array Overall Cell Failure: [ ] P = P Fail = P A! R! W! H F F F F F P MEM Redundant Columns PASS AF FAIL RF P F WF HF 1-P F P F P COL P COL : Probability that any of the cells in a column fail P COL = 1 (1 P ) F N ROW
Transistor Sizing Failure Probability (Log) Failure Probability (Log) -4-6 -8 105 115 125 Width of Pull-Up Transistor (nm) -5-10 -15 185 215 245 Width of Pull-Down Transistor (nm) Failure Probability (Log) -4-6 -8-10 130 140 150 Width of Access Transistor (nm) = Read Vt Failure i Vt Write Failure Access Failure Cell Failure 0 L MIN i W LW MIN i Slide contributed by K. Roy, Purdue
Impact of Redundancy on Memory Failure Actual Col. Red. Col. Failure Probability svt P MEM svt Total Area=Const. Cell Failure Larger redundancy Redundant Col / Total Col. [%] (1) more column to replace (less memory failure). (2) smaller cell area (larger cell failure).
Question q Array redundancy a) Improves cell stability b) Degrades cell performance (i.e increases read and write times) c) Does not require any change to cell peripheral circuits d) Row redundancy is better than column redundancy Slide 6
Example: Multi-VCC for SRAM Cell 1.2 1.6 V2 (V) 1 0.8 0.6 0.4 - V_WL-V_Cell = 0V V_WL-V_Cell - = -0.1V - V_WL-V_Cell = -0.2V Cell write margin (normalized) 1.4 1.2 1 0.8 0.6 0.4 Improved Write Margin 0.2 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 V1 /(V) 0 0 0.1 0.2 0.3 V_WL V_Cell (V) Create differential voltage between WL and Cell to decouple the Read & Write Write: V_WL > V_Cell Read: V_WL < V_Cell Source: K. Zhang et. al. ISSCC 2005
Dynamic Circuit Techniques for Variation Tolerant SRAM V WL = V DD + D Higher V WL => V cell = V DD - D Lower V WL => V WL Read lower V read (weak AX) Write Strong AX helps discharge AXL 1 PL NL PR NR 0 AXR V cs Higher V cs => lower V read (strong PD) Lower V cs => Weak PUP Higher V trip V BL = 0 - D V BL = 0 V BR =V DD V BL Weak impact Negative V BL for 0 => strong AX helps discharge
Example: Dual-Vcc based Dynamic Circuit Techniques VCC MUX WL cell cell cell cell cell VCC_SRAM WL BI MUX VCC MUX VCC_hi VCC_lo cell cell cell cell cell W R R R MUX (8:1) MUX MUX MUX MUX MUX VCC_Select VCC_Hi VCC_Lo Dynamic VCC MUX is integrated into subarray VCC selection is along column direction to decouple the Read & Write Source: K. Zhang et. al. ISSCC 2005
Negative Bit Line Scheme Conventional This Scheme BL WL, PCHG BR BL BR BIT_EN & WL, NSEL PCHG ~ C boost /C BL BL BR cell P1 P2 C boost WR PCHG BIT_EN BIT_EN generating block CS Vin C boost NSEL NSEL V BL N BL,P BL N BR,P BR C BL DB= 1 D= 0 Source: S. Mukhopadhyay, R. Rao et. al, TVLSI 2009
Effectiveness Considerations: Writability improvement Norm. write fail prob 10 0 10-5 10-10 Fast Monte-Carlo simulations for 45nm PD/SOI V cell = V DD - D V WL = V DD + D V BL = - D V BL = - D V cell = V DD - D 10-15 0 50 100 150 200 change in terminal voltage (D) [mv] Various dynamic schemes have different effectiveness in improving writability for similar read stability Higher V WL is most effective Source: S. Mukhopadhyay, R. Rao et. al, TVLSI 2009
Impact on Active Data-Retention V cell = V DD - D Fail probabilities are normalized to write fail prob. at nominal condition WL 2 = 0 Sel. col. -D V DD Active dataretention fails DC-NBL Lower V cell Column based read-write control adversely impact the active data-retention failures DC negative bitline has higher active data-retention failures Tran-NBL and lower V cs have comparable failure rates Source: S. Mukhopadhyay, R. Rao et. al, TVLSI 2009
Dynamic Circuit Techniques for Variation Tolerant SRAM V WL = V DD + D Higher V WL => V cell = V DD - D Lower V WL => V WL Read lower V read (weak AX) Write Strong AX helps discharge AXL 1 PL NL PR NR 0 AXR V cs Higher V cs => lower V read (strong PD) Lower V cs => Weak PUP Higher V trip V BL = 0 - D V BL = 0 V BR =V DD V BL Weak impact Negative V BL for 0 => strong AX helps discharge
Implementation Consideration: Half-Select Stability WL 1 =V DD + D WL 2 = 0 V cell = V DD - D Sel. col. V DD Half-sel col. -D V DD V DD V DD Higher V WL - Row-based scheme - Degrades half-select read stability of the unselected columns Lower V cell or negative bit-line + Column-based scheme + Half-select read stability remains same
Assist Methods
Question q Of the various assist methods a) Negative bit line scheme does not help 8-T sram cell b) Word line under drive does not help 8-T sram cell c) Word line over drive does not help 7-T conditionally decoupled sram cell d) VCDL does not help any kind of assymetric sram cell Slide 17
High Performance vs Dense Cells W_PG W_PU W_PD AXL PR NR High-Performance and READ stable W PD >> W PG for READ stability Low READ access time Large cell footprint NL PL AXR Less RDF induced V T fluctuation in PD Microprocessors etc. W_PD W_PU W_PG AXL PR NR Dense and WRITE stable W PD ~ W PG for WRITE stability Large READ access time AXR Small cell footprint NL PL Large RDF induced V T fluctuation in PD Dense applications PDA etc. W_PD1 (A. Bansal, IRPS 2009)
Block Diagram 2 m bits A 0 A 1 WL[0] Precharge Circuit Row Decoder CELL 2 n 2 n x 2 m cell CELL WL[2 n -1] A n CELL CELL BL 0 BLB 0 BL 2 m -1 BLB 2 m -1 A n A n+m-1 Column Decoder Sense Amplifier & Write Driver Blocks Block Decoder Address Address Buffer Global Data Bus R/W CS Timing & Control Global Read/Write Slide 19
FET characteristics and BTI Threshold voltage (V T ) Current degradation approximately corresponds to V T degradation Known sensitivities PBTI is more sens. to Voltage V tlin (mv) NBTI is more sens. to AC fitting AC data temperature DC fitting Semi-empirical model (for both 10 NBTI and PBTI) -1 DC data 10-2 10 0 10 2 10 4 10 2 10 1 10 0 DC AC @ sense2 Net Stress Time (sec) V = AV a b n T DC _ stress DDT t (without including recovery)
Recovery after stress *Ramey et. al., Intel, IRPS 2009 Ø Recovery happens when FET is OFF V T = after _ relax FRx VT DC _ stress Fraction Remaining FR = 1+ t t relax stress n 1 Ø In other words, if probability of 1 at the gate of an NFET is say P 1, then, duty_cycle = t stress tstress + t relax = P Ø Biggest benefits of recovery when duty_cycle < 95% 1 Fraction Remaining *Ramey et. al., Intel, IRPS 2009
FET stress-recovery Let s take an example of simple CMOS inverter 1 0 PFET OFF 0 1 PFET ON NFET ON NFET OFF PFET is relaxing: Gate-source HIGH and drain LOW NFET is stressed: Gate is HIGH and source-drain LOW PFET is stressed: Gate is LOW and source-drain HIGH NFET is relaxing: Gate-source LOW and drain HIGH - If a FET is ON, it s stressed (for both NFET and PFET) - If a FET is OFF, it s relaxed (for both NFET and PFET)
FET stress-recovery For other circuit types say transmission gate PFET ON 0 PFET OFF 1 1 1 0 0 Either 1 or 0 Either 1 or 0 NFET ON 1 NFET OFF 0 - Both the FETs are either ON or OFF together - Source-drain voltages during relaxation depends on other circuit blocks on left and right - e.g., negative gate-drain or gate-source voltage in NFET may speed up recovery (also true for inverter on previous slide)
Static or DC stress Nature of Stresses/recovery FETs are in the same voltage bias condition during the USAGE PFET ON NBTI 0 1 1 ΔVT t PBTI NFET ON PBTI ΔVT NBTI Examples: t SRAM cells storing the same data for long time Circuit paths not used for long time but powered on Word line drivers, local and global eval circuits
Nature of Stresses/recovery Alternating or AC stress FETs turn ON (stress) and OFF (recover) during the USAGE It s composed of several DC stress and recovery conditions Durations of stress and recovery depend on nature of program running and typically can not be estimated ΔVT PBTI t ΔVT NBTI Examples: SRAM cells frequently changing the stored data Logic circuit paths doing computations t
Question q The bias temperature instability device degradation in a circuit can be reduced by a) Using assymmetric transistors since they will degrade at different rates b) Avoiding pass gates in the design and always using transmission gates c) Increasing the supply voltage of the circuit d) Ensuring that all nodes in a circuit switch every N cycles Slide 26
Timing Failure due to BTI 0 1 0 1 0 1 t FlipFlop
BL SRAM Operating Mode: READ V DD 1 1 PL PR AXL 0 V L V R 1 NBTI AXR BR BL and BR are pre-charged to VDD and then left hanging Voltage WL BL V L DV WL 1 NL NR Sense-Amp fires Time PBTI Access FETs (AXL & AXR) are ON for short duration while cell is accessed => assumed negligible degradation The data stored should not flip during READ => NL (NR) should be stronger than AXL (AXR): PBTI can make NL weak (bad!) Sufficient DV to fire SA should be developed while WL = 1 => AXL-NL should fast discharge BL: Weak NL will slow discharge (bad!) (A. Bansal, MicroReliability 2009)
BL SRAM Operating Mode: WRITE NBTI V DD BR BL and BR are FIXED to data WL 1 PL PR L 0 AXL 1 0 AXR 1 R Voltage R L WL 1 NL NR PBTI Time Weak cross-coupled inverters (NL-PL and NR-PR) are good for writing The data stored must flip during WRITE => AXL (AXR) should be stronger than PL (NR) NBTI (PBTI) can make PL (NR) weak (good!) Data should flip while WL = 1 => WL pulse width increased (good) (A. Bansal, MicroReliability 2009)
Static and Alternating Stress 1 BL V DD NBTI BR 1 BL 1 V DD NBTI BR 1 1 WL PBTI 0 V L 1 V R Static Stress Cell is storing same data for long time => asymmetric May be READ multiple times but not flipped DVt for static stress larger than alternating stress (no recovery) READ gradually becomes unstable Increases READ access time 1 WL PBTI 0 V L 1 V R Alternating Stress Cell is regularly flipped => symmetric Equal time/relaxation for storing 1 and 0 to maintain symmetry DVt for same usage is less (low power-on time) β-ratio between pull-down and pass-gate FETs varies => PD weakens and READ fail increases Increases READ access time ØTypically all cells in between Static to Alternating stress (A. Bansal, MicroReliability 2009)