-Spring 006 Digial Inegraed Circuis Lecure Design Merics Adminisraive Suff Labs and discussions sar in week Homework # is due nex hursday Everyone should have an EECS insrucional accoun hp://wwwins.eecs.berkeley.edu/~ins/newusers.hml PC accouns for 5 Cory will be se up before he firs lab EECS EECS Las Lecure Challenges in Digial Design Las lecure Inroducion, Moore s law, fuure of ICs oday s lecure Inroduces basic merics for design of inegraed circuis how o measure delay, power, cos, ec. DSM Microscopic Problems Ulra-high speed design Inerconnec Noise, Crossalk Reliabiliy, Manufacurabiliy Power Dissipaion Clock disribuion. /DSM Macroscopic Issues ime-o-marke Millions of Gaes High-Level Absracions Reuse & IP: Porabiliy Predicabiliy ec. Everyhing Looks a Lile Differen? and here s a Lo of hem! EECS EECS Design Absracion Levels + S n+ SYSEM MODULE GAE CIRCUI DEVICE G D n+ his Class Inroduces basic merics for design of inegraed circuis how o measure delay, power, ec. Groups layou recangles ino ransisors and wires ransisors and wires ino gaes Gaes ino funcions (Funcional blocks ino sysems) e.g. EECS50 Need o verify ha he assumpions are valid EECS 5 EECS 6
Design Merics Ouline How o evaluae performance of a digial circui (gae, block, )? Cos Robusness Reliabiliy Scalabiliy Speed (delay, operaing frequency) Power dissipaion Energy o perform a funcion Design Merics Cos Robusness Speed Power EECS 7 EECS 8 Cos of Inegraed Circuis Mask Cos is Increasing NRE (non-recurren engineering) coss design ime and effor, mask generaion one-ime cos facor Recurren coss silicon processing, packaging, es proporional o volume proporional o chip area Cos [in $000] 500 000 500 000 500 0 0.8 μm 0.5 μm 5nm 65nm 90nm 0. μm 996 998 000 00 00 006 008 Year EECS 9 EECS 0 oal Cos Cos per IC Die Cos Wafer fixed cos cos per IC variable cos per IC + volume Single die Variable cos cos of wafer cos of die dies per wafer * die yield cos of die + cos of die es + cos of packaging variable cos final es yield Going up o (0cm) From: hp://www.amd.com EECS EECS
Yield No. of good chips per wafer Y 00% oal number of chips per wafer Wafer cos Die cos Dies per wafer Die yield π ( wafer diameer/) π wafer diameer Dies per wafer die area die area Defecs Yield 0.5 Yield 0.76 α defecs per uni area die area die yield + α α is approximaely die cos f (die area) EECS EECS Some Examples (99) Chip 86DX 86 DX Power PC 60 HP PA 700 DEC Alpha Super Sparc Penium Meal layers Line widh 0.90 0.70 0.70 Wafer cos $900 $00 $700 $00 $500 $700 $500 Def./ cm.0.0..0..6.5 Area mm 8 96 56 96 Dies/ wafer 60 8 5 66 5 8 0 Yield 7% 5% 8% 7% 9% % 9% Die cos $ $ $5 $7 $9 $7 $7 Cos per ransisor cos: -per-ransisor 0. 0.0 0.00 0.000 0.0000 0.00000 Fabricaion cos per ransisor 0.000000 98 985 988 99 99 997 000 00 006 009 0 EECS 5 EECS 6 Robusness Noise in Digial Inegraed Circuis DC Operaion Volage ransfer Characerisic V(y) i() v() V DD f V(y)V(x) VOH f(vol) VOL f(voh) VM f(vm) V Swiching hreshold M Inducive coupling Capaciive coupling Power and ground noise V(x) Nominal Volage Levels EECS 7 EECS 8
Mapping beween analog and digial signals Definiion of Noise Margins V IH Undefined Region V IL V ou Slope - Slope - 0 NM H Undefined Region NM L V IH V IL Noise margin high: NM H V IH Noise margin low: NM L V IL 0 V IL V IH V in Gae Oupu (Sage M) Gae Inpu (Sage M+) EECS 9 EECS 0 Noise Budge Allocaes gross noise margin o expeced sources of noise Sources: supply noise, cross alk, inerference, offse Differeniae beween fixed and proporional noise sources Key Robusness Properies Absolue noise margin values are decepive a floaing node is more easily disurbed han a node driven by a low impedance (in erms of volage) Noise immuniy is he more imporan meric he capabiliy o suppress noise sources Key merics: Noise ransfer funcions, Oupu impedance of he driver and inpu impedance of he receiver; EECS EECS Regeneraive Propery Regeneraive Propery ou ou v v f(v) finv(v) v v v finv(v) f(v) v 0 v v v v v 5 v 6 A chain of inverers 5 V (Vol) v 0 v EECS v 0 Regeneraive in v 0 v in Non-Regeneraive EECS Simulaed response 0 v v 6 8 0 (nsec)
(V ) V o u Fan-in and Fan-ou he Ideal Gae V ou N M g R i R o 0 Fanou NM H NM L V DD / Fan-ou N Fan-in M V in EECS here is a modified definiion of fan-ou for CMOS logic 5 EECS 6 Example: An Old-ime Inverer 5.0 Example: An Old-ime Inverer.0.0.0.0 0.0 NM L V M.0.0 NM H.0.0 5.0 V in (V).6V 0.V V IL 0.6V V IH.V NM H V IH.V NM L V IL 0.V EECS 7 EECS 8 Delay Definiions Ring Oscillaor V in 50% v 0 v v v v v 5 phl plh v 0 v v 5 V ou 90% 50% f 0% r p N EECS 9 EECS 0 5
A Firs-Order RC Nework Power Dissipaion R vou Insananeous power: p() v()i() V supply i() vin C Peak power: P peak V supply i peak p ln () τ 0.69 RC Imporan model maches delay of an inverer EECS Average power: + Vsupply + P ave p( ) d i supply () EECS d Energy and Energy-Delay A Firs-Order RC Nework Power-Delay Produc (PDP) R v ou E Energy per operaion P av p vin C L EECS Energy-Delay Produc (EDP) qualiy meric of gae E p EECS E0 0 0 V DD PDD () d VDD idd () d VDD CLdvou EC 0 0 V DD PC () d vou il () d CLvoudvou 0 0 CLVDD CLVDD Summary Undersanding he design merics ha govern digial design is crucial Cos Robusness Speed Power and energy dissipaion Nex Lecure A firs glance a an inverer CMOS manufacuring process EECS 5 EECS 6 6