ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email: Lynn.Fuller@rit.edu Department webpage: http://www.rit.edu/kgcoe/microelectronic/ 2-15-2019 MOS_Amplifiers.ppt Page 1
OUTLINE Introduction Voltage Transfer Curve (VTC) NMOS Inverting Amplifier Resistor Load NMOS Enhancement Load NMOS Enhancement V++ NMOS Depletion Load CMOS Biasing The Amplifier Resistor RG Feedback Resistor from Vout to Vin References Homework Appendix SPICE Models Cadence Parameter Sweeps Page 2
INTRODUCTION There are many ways to make an inverting amplifier. Lets start with the common source with resistor load inverting amplifier. The voltage transfer curve, VTC (Vout vs Vin) shows where large change in Vout vs Vin occurs and if the circuit is biased in this region we can realize a voltage amplifier. Vin Vout R +V Vout +V Vout Slope = Gain SYMBOL Vin RESISTOR LOAD 0 0 VTC +Vin Page 3
VIN CALCULATION OF VOLTAGE TRANSFER CURVE R +V DD VOUT NMOS-M1 RESISTOR LOAD First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth Note: Rochester Vin Institute = Vgs, of Technology Vout = Vds, therefore Vgd = Vin-Vout Vth might be +1volt +V 0 VOUT 0 M1 Off Vth M1 Saturation M1 Linear VTC +V VIN Page 4
CALCULATION OF VTC VIN R +V DD I D VOUT NMOS-M1 RESISTOR LOAD Next calculate Vout = V DD I D R using the correct equation for I D for the transistor depending on region of operation Linear (Non-Saturation) I D = µw Cox (Vg-Vt-V d /2)V d L +V 0 VOUT 0 M1 Off Vth M1 Saturation Cox = Cox/Area = o r/xox M1 Linear Saturation +V VIN I D = µw Cox (Vg-Vt) 2 2L Page 5
CALCULATION OF VTC M1 in Saturation Vout = V DD R I D = Given: V DD and R We know the following: Cox = Cox/Area = o r/xox o = 8.85e-14 F/cm r=3.9 for oxide Xox = gate oxide thickness W= width of MOSFET L=Length of MOSFET Vt = Threshold Voltage µ = mobility V DD - R µw Cox (Vin-Vt) 2 2L Page 6
CALCULATION OF VTC M1 in Non-Saturation Vout = V DD I D R Vout = V DD I D R = V DD - R µw Cox (Vg-Vt-V d /2)V d L Kx Vo = V DD - R Kx(Vin-Vt-Vo/2)Vo Vo = V DD - R Kx(Vin-Vt)Vo- RKxVo 2 /2 quadratic formula 0 = V DD - R Kx(Vin-Vt - 1)Vo- RKxVo 2 /2 a x 2 + bx + c = 0 x = -b +/- b 2-4ac 2a Page 7
CALCULATION OF VTC M1 in Non-Saturation Vout = b +/- b 2-2V DD /KxR b=(vin Vt + 1/KxR) 2a Page 8
CALCULATION OF VTC Note: Equations only valid in specific regions Page 9
LTSPICE VTC PARAMETER SWEEP OF RL Add the step command to the schematic. Runs SPICE with different values of RL See appendix for Cadence PSPICE parameter sweeps IDS = 1.0mA RL= 10K 50K R1=10K VGS = 2.63V Gain of ~12V/V for 10K Rload and 1mA Page 10
COMMON SOURCE MOSFET AMPLIFIER +V DD Vin RS C1 RG RD + VGS - C2 RL NMOS M1 VOUT VG I D = µw Cox (Vg-Vt) 2 2L Middle of DC load line is I D = ½ Vdd/RD Page 11
COMMON SOURCE MOSFET AMPLIFIER I D = µw Cox (Vg-Vt) 2 2L If V DD =20V and RD=10K find Vg to give I D =1mA Middle of DC load line is I D = ½ Vdd/RD We know µ, W, L, Cox, Vt see SPICE Model at end of this document We can find Vgs to give I D =1mA For the RIT4007N7 transistor SPICE model Uo=1300 Ueff=~650 W=170u L=10u Tox=4E-8m Vt=1.4 KP=µCox =650 8.85e-14 3.9 / 4E-6 = 0.056m KP x W/L = 0.056m x 170µ/10µ = 0.952m Solve for Vg to give ID of 1mA Vg = (2 x 1m/0.952m )^0.5 + 1.4 = 1.53+1.4 = 2.93volts Vov = 1.53volts Page 12
AC EQUIVALENT CIRCUIT Vin RS RG + Vgs - gm Vgs ro RD RL + Vo - Batteries are short circuits, current sources are open circuits, capacitors are shorted. Transistor is replaced by its AC equivalent circuit. (inside dotted box) gm = d Id / d Vgs ro = d Vds / d Id at the Q point 1/slope from ID-VDS family at the Q point Page 13
ro, gm AND Vt FROM MEASURED ID-VDS Measured CD4007 NMOS Id vs Vds Family of Curves Extraction of Lambda, gm and Vt from measured Ids vs Vds Family of curves. ro = 1/slope = 20.9K ohms DID = 0.8ma l = slope/idsat = 0.0479/5.837ma = 0.0082 ~0.01 ID VGS = 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V DVG = 0.5V gm = DID/DVG =0.8ma/0.5V = 1.6m S Vt = VGS where ID ~ zero = ~1.4V Page 14
gm is the change in current ID with change in gate voltage Vg (in excess of the threshold voltage, Vov) at the Q point ID gm= d ID / d VG slope of ID vs VG textbook gm = µcox (W/L) Vov TRANSCONDUCTANCE gm RIT4007N7 Vt=1.4 Vgs = 2.6V Vov = 1.2V gm = 1.4m gm ID gm Mobility (µ) decreases with increase in doping concentration, increase in gate and drain voltage, increase in temperature. LTSPICE Simulated Id-Vgs Curves in Saturation Region Page 15
SPICE CIRCUIT FOR ID vs VGS IN SATURATION Page 16
SPICE CIRCUIT FOR ID vs VGS NON-SATURATION Page 17
gm AND Vt FROM MEASURED ID-VGS Measured CD4007 NMOS Id vs Vgs Curves ID VG = VD gm = did/dvg gm = 1.5mS @Vgs=3V Vt = x-intercept = ~1.38V Extraction of gm from measured Ids vs Vgs in saturation region Vdg = 0 Extraction of Vt from measured Ids vs Vgs in linear region Vds = 0.1V Page 18
AC EQUIVALENT CIRCUIT Vin RS RG + Vgs - gm Vgs ro RL RD + Vo - µ is reduced to ½ of Uo to account for mobility degradation, Ueff = ~650 Voltage gain Vo = -gm Vgs ro//rd//rl = Vgs (ro//10k//rl) Vgs= RG/(RS+RG)Vin = Vin if RG is very big KP W/L = µ Cox (W/L) =(650)(8.85E-14)(3.9)(17)/4e-6=0.953m gm = 0.953m x Vov = 0.953m x 1.53 = 1.45mS Vo/Vin = -gm RD = -1.45m 10K = -14.5 V/V (if RL is infinite and RG is big) This gm from did/dvgs using textbook equation for ID in saturation Page 19
SPICE FOR MOSEFET AMPLIFIER CIRCUIT Page 20
SUMMARY Hand Calculation SPICE IC 1mA 1mA VGS 2.93 V 2.63 V gm 1.45 ms 1.4 ms Rin Infinite infinite ro infinite 20 K ohm Vo/Vin 14.5 V/V 10.9 V/V Hand calculations from equation for ID for MOSFET in saturation. LTSPICE for CD4007 NMOSFET in common source amp circuit. Page 21
VIN VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD +V M1 VO M2 NMOS ENHANCEMENT LOAD I M1 Vt + V - Vt 0 +V M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor with gate connected to the drain is smaller in size and also limits current. See the I-V characteristics. In the first quadrant the transistor approximates the resistor. However, Vout high is below VDD by the threshold voltage of M1 Cox = Cox/Area = o r/xox I 1/R V +V 0 VOUT M2 Off Vt Page 22 Gain = M2 & M1 Saturation M2 Linear W/L switch W/L load VIN I D = µw Cox (Vg-Vt) 2 2L Saturation
DERIVATION OF GAIN EXPRESSION VIN +VDD M1 VO M2 Assume Vout = Vin and both transistors are in saturation for the steep part of the VTC. The current in M1 is equal to the current in M2 is equal. Also assume Vt is the same for both transistors. I 2 = I 1 µw 2 Cox /2L 2 (V G -V t ) 2 = µw 1 Cox /2L 1 (V G -V t ) 2 W 2 /L 2 (V G -V t ) 2 = W 1 /L 1 (V G -V t ) 2 But, V G2 is VIN and V G1 = VO +Vt (W 2 /L 2 ) (V IN -V t ) 2 = (W 1 /L 1) (VO +Vt -V t ) 2 Gain = d VO/d V IN Gain = W2/L2 W1/L1 Gain = W/L switch W/L load Page 23
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD Gain = W/L switch W/L load G=9.5 G=5.5 G=2.2 Note: increasing L of the load is equivalent to increasing R of a resistor load, Vout high is Vdd Vt M1, Gain is shown. Page 24
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS VIN V++ +V M1 VO M2 NMOS ENHANCEMENT LOAD V++ GATE BIAS Gain = W/L switch W/L load M2 is the switch and M1 is the load. The load limits the current when M2 is on. The load could be a resistor but an NMOS transistor is smaller. M1 is always on because the gate voltage is above the supply voltage. (Vgs is always above the threshold voltage. Vout max is the supply voltage. The threshold voltage of M1 depends on source to substrate voltage for M1. Page 25
VTC NMOS INVERTER- NMOS ENHANCEMENT LOAD AND V++ GATE BIAS Gain = W/L switch W/L load G=2.2 G=9.5 G=5.5 Note: increasing Rochester Institute of L Technology of the load is equivalent to increasing R of a resistor load, Vout high is Vdd, Gain is shown. Page 26
VTC NMOS INVERTER NMOS DEPLETION LOAD VIN +V M1 VO M2 I Vt + V - I 1/R Gain = W/L switch W/L load NMOS DEPLETION LOAD Vt V M2 is the switch and M1 is the load. The load limits the current when M2 is on. In the first quadrant the transistor approximates the resistor. M1 is always on because its threshold voltage is set to zero or slightly negative by ion implant. Note: transistor M1 symbol has solid line between D and S. Page 27
VTC NMOS INVERTER NMOS DEPLETION LOAD * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7D NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=-1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) Need a new SPICE model for the Depletion mode NMOS. New model name and negative VTH0. Using ion implant the VTH0 can be made negative. Page 28
VTC NMOS INVERTER NMOS DEPLETION LOAD D D D Gain = W/L switch W/L load G=2.2 G=9.5 G=5.5 Note: increasing L of the load is equivalent to increasing R of a resistor load, Vout high is Vdd, Gain is shown. Page 29
VIN +V CMOS PMOS VO NMOS CMOS - CALCULATION OF VTC +V First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth 0 VOUT 0 nmos off nmos sat pmos linear nmos & pmos saturation Vthn pmos sat nmos linear V-Vthp pmos off +V VIN Note: Vin Rochester = Institute Vgs, of Vout Technology = Vds, therefore Vgd = Vin-Vout Vth might be +1volt Page 30
CMOS INVERTER VOUT VIN VOUT +V Q point +V Idd Slope = Gain VIN VO CMOS 0 0 +V VIN Vinv Page 31
BIASING AT VIN = VOUT V+ Vin RG pmos nmos Vout Since no DC current flows into the gate for either MOSFET the voltage across RG is zero. DC Vin=Vout and is the Q point. RG can be large but not infinite. Page 32
Vin RS Rin AC EQUIVALENT CIRCUIT + Vgs - RG gm n Vgs gm p Vgs ro n ro p Rout Batteries are short circuits, current sources are open circuits, capacitors are shorted. Transistor is replaced by its AC equivalent circuit. NMOS and PMOS are in parallel If RG and RL is large the gain is Vo/Vin= ~(gm n +gm p ) (ro n //ro p ) RL + Vo - Example: Vo/Vin = (1.5m+1.5m)(20K//20K) =30 V/V Page 33
CMOS AMPLIFIER BIASED AT VIN=VOUT Page 34
COMPARISON OF 10u, 1u AND 100n CMOS INVERTERS VDD = 5 volts VDD = 3.3 volts VDD = 2.5 volts Imax=5.4mA Imax=100uA Imax=21uA Gain=-90 Gain=-17 Gain=-6 RITALDN3/RITALDP3 L=10u W=880u L=10u W=880u RITSUBN7/RITSUBP7 Ln=1u Wn=2u Lp=1u Wp=2u EECMOSN/EECMOSP Ln=180n Wp=200n Ln=180n Wp=200n Page 35
MULTI-STAGE CAPACITOR COUPLED MOS AMP +V DD +V DD Vin RS C1 RG RD + VGS - C2 M1 RG RD + VGS - M2 C3 VOUT RL VG VG Rs Ro1 Ro2 Rin1 + AvVin1 + Rin2 AvVin2 + + + - Vin1 - Vin2 - vs - - RL + - vo Stage 1 Stage 2 Page 36
OTHER CONFIGURATIONS Common Gate Biasing Schemes still working on these Page 37
REFERNCES 1. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13. 2. Dr. Fuller s Lecture Notes, http://people.rit.edu/lffeee Page 38
HOMEWORK MOS AMPLIFIERS 1. Derive the equation gm = µcox (W/L) Vov starting from the equation for Id in the saturation region. 2. Design a NMOS amplifier with NMOS enhancement load to give a gain of 10V/V or more. 3. How can you get higher voltage gain for the CMOS Amplifier shown in the SPICE simulation in the lecture notes? Page 39
SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015 *LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/cmos.htm * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pclm=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 40
SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 41
SPICE MODELS FOR MOSFETS *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Page 42
APPENDIX - CADENCE PARAMETER SWEEPS Select Parameters: from the special library and put on schematic. Then double click it. Select New Property. Give a Name and starting Value in Add New Property dialog box shown below. Apply. Page 43
APPENDIX - CADENCE PARAMETER SWEEPS Return to schematic and change the value of the resistor to {Rval} Including curly brackets Where this is the new property name given in the attribute editor The primary sweep is for V1, zero to 5 volts in small steps. Parameter sweep can be a list of values as shown. Page 44
APPENDIX - CADENCE PARAMETER SWEEPS 5.0V V(output) 4.0V R=1K 3.0V 2.0V 50K 10K 1.0V 0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V V(output) V_V1 Vin Page 45