Carrier Profiling of a Heterojunction Bipolar Transistor and p±i±n Photodiode Structures by Electrochemical C±V Technique

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R. Kinder et al.: Carrier Profiling of a Heterojunction Bipolar Transistor 631 phys. stat. sol. (a) 175, 631 (1999) Subject classification: 73.40.Kp; 73.61.Ey; S7.12; S7.15 Carrier Profiling of a Heterojunction Bipolar Transistor and p±i±n Photodiode Structures by Electrochemical C±V Technique R. Kinder (a), AÂ. Nemcsics (b), R. Harman (a), F. Riesz (b), and B. PeÂcz (b) (a) Slovak University of Technology, Faculty of Electrical Engineering and Information Technology, Department of Microelectronics, IlkovicÏova 3, 812 19 Bratislava, Slovakia (b) Hungarian Academy of Sciences, Research Institute for Technical Physics and Materials Science, P.O. Box 49, H-1525 Budapest, Hungary (Received May 7, 1999; in revised form July 19, 1999) Carrier profiling of GaAs/GaAlAs multilayer structures (heterojunction bipolar transistor and heterojunction p±i±n photodiode) by electrochemical capacitance±voltage technique is described. Optimum measurement parameters (electrolyte type, etching and measurement voltages, etc.) are established. The results are compared with those of spreading resistance profiling and transmission electron microscopy. Some specific problems are discussed. 1. Introduction The research and development of semiconductor devices requires reliable determination of the depth profiles of carrier concentration in the device layer structures. A variety of methods are available for this task, such as spreading resistance (SR), capacitance± voltage (C±V) and electrochemical capacitance±voltage (ECV) methods. The ECV technique is an interesting alternative to conventional C±V methods because of its capability of profiling to practically unlimited depths, not limited by the breakdown. The technique has been applied to Si, GaAs, InP and other compound semiconductors. However, successful application of this method to a given semiconductor material greatly depends on the availability of a suitable electrolyte which supports a well defined electrochemical (anodic) dissolution process and forms a nearly ideal Schottky contact to the semiconductor. The anodic dissolution behaviour of semiconductors depends on a number of factors such as the effective dissolution valence (number of electronic charges transferred per atom of material dissolved), stripping potential, illumination level, etc. [1, 2]. This paper describes the determination of carrier concentration profiles of practically important GaAs/GaAlAs multilayer structures (heterojunction bipolar transistor, HBT, and heterojunction p±i±n photodiode) by the ECV technique placing emphasis on the properties of the GaAs/electrolyte interface. Optimum measurement conditions (electrolyte type, ohmic contact, etc.) are established. The results are compared with SR and transmission electron microscopy (TEM) measurements. Some specific problems are discussed.

632 R. Kinder et al. Ta b l e 1 Layer structure of the HBT layer thickness (nm) dopant concentration (cm ±3 ) layer material cap 500 2 10 18 n + GaAs : Si emitter 190 3 10 17 n Ga 0.53 Al 0.47 As : Si spacer 1 10 undoped Ga 0.53 Al 0.47 As spacer 2 10 undoped GaAs base 80 2 10 19 p ++ GaAs : Be spacer 3 10 undoped GaAs collector 400 5 10 16 n GaAs : Si subcollector 100 2 10 18 n + GaAs : Si substrate 0.4 mm 2 10 18 n + GaAs : Si Ta b l e 2 Layer structure of the p±i±n photodiode layer thickness (mm) dopant concentration (cm ±3 ) layer material contact 0.1 3 10 19 p ++ GaAs : Be window 1.0 2 10 19 p ++ Ga 0.66 Al 0.34 As : Be spacer 0.17 undoped Ga 0.66 Al 0.34 As absorption 1.8 undoped GaAs buffer 0.88 4 10 18 n + GaAs : Si substrate 0.4 mm 1 10 18 n + GaAs : Si 2. Experimental 2.1 Sample preparation The studied layer structures were grown by molecular beam epitaxy (MBE). Both samples consist of GaAs/GaAlAs layers grown on an (100) Si-doped n + GaAs substrate. Be and Si were applied as p and n type dopants, respectively. Details on the HBT structure are shown in Table 1 [3]. The temperature of the substrate during the growth of the whole structure was 605 C. The unusually high amount of Al in the GaAlAs layers predicts that these layers may possess a high concentration of crystal defects. The other sample is a heterojunction p±i±n photodiode structure (Table 2) [4]. The growth temperature was 610 C. The diodes fabricated from the layer structure possess breakdown voltages typically 33 V but a few diodes have a breakdown voltage between 20 and 36 V. 2.2 Electrochemical profiling Analogue Polaron PN 4100 equipment connected to a personal computer was applied to the automatic measurements of the carrier profiles and of the current±voltage (I±V) and conductance/capacitance-voltage (G/C±V) curves. The measurements were conducted using carrier and modulation frequencies of 3 khz and 30 Hz for the bias voltage. The I±V and G/C ±V curves contain information about the optimum voltage magnitudes for etching (V etch ) and for measuring (V meas ). We found from the G/C±V

Carrier Profiling of a Heterojunction Bipolar Transistor 633 measurement that the N(x) profile was reproducible for V meas = 0.2 V and V etch = 0.3 V. The number of the effective dissolution valence for dissolving GaAs was taken as six for all electrolytes [1]. The profiler operates under potentiostatic control using a platinum electrode for C±V measurement. A carbon (counter-)electrode is used to complete the current circuit for etching, and a saturated calomel electrode is used as a reference against which the equilibrium (rest) and overpotential is measured. Before inserting the samples into the electrochemical cell, the samples were shortly dipped in concentrated (8%) HF, then rinsed several times in distilled water and dried. The ohmic contact between the sample and the contact of the cell was tested in different configurations: InGa eutectic alloy and a drop of 5% HCl between the sample and a brass sheet. The HCl drop gave the smallest contact resistance. Before filling up, the cell was cleaned using distilled water and dried carefully to ensure a well defined electrolyte concentration. Best results were obtained by cleaning the tested area using a blower through the hole of the pump chamber of the cell body just after filling the cell with 2 ml electrolyte and then filling the cell up with the electrolyte. (To remove the gaseous product from the sample surface generated by the anodic dissolution process the ECV equipment incorporates a pumping system.) The wetted contact area between the electrolyte and semiconductor interface was about 1 mm 2. The depth and roughness of the etched craters were studied by a Talystep surface profilometer. Different aqueous electrolytes were tested, namely 0.1 M Tiron (1.2-dihydroxybenzene-3.5 disulfonic acid, disodium salt), 0.5 M HCl in water, EDTA (0.2 M sodium hydroxide (NaOH) in deionized water. Into 250 ml of the 0.2 M NaOH solution, we add 9.3 g of disodium ethylenediamine tetraacetate (F.W. 372.24)). The best results (low roughness of the etched surface) were obtained with the 0.1M Tiron solution [6]. In general, the roughness of the etched surface is due to structural defects where the etching is faster. Uncertainties of crater flatness and roughness cause difficulties in the definition of the crater depth and, consequently, errors in the measured profile. 2.3 Spreading resistance and transmission electron microscopy measurements The SR method determines the sample resistivity by resistance measurements on a bevelled semiconductor sample surface using a pair of point contacts. The measured resistance is a function of the free carrier concentration; however, other, sometimes uncontrolled factors, such as stylus and surface conditions, stylus load, material and conductivity type etc. have a serious effect on the measured resistance. Therefore, quantitative evaluation is usually made using calibrated standards. The SR method is mainly applied to silicon; the sensitivity is limited for III±V materials. We therefore used this technique as a complementary, qualitative method only. The SR measurement was carried out in a SSM 130 apparatus. Polishing of the bevelled surface was carried out by a 1/4 mm diamond powder. The tangent of the bevel angle is 0.00534. The distance of the point contacts is 0.1 mm and the step length is 10 mm. The load on the point contacts is 0.1 N. The depth resolution depends practically on the bevel angle; resolution of 25 nm can be achieved. In addition, cross sectional TEM was applied to give exact layer thickness data and information on possible crystal defects. Samples were prepared by ion milling [5].

634 R. Kinder et al. Fig. 1. The carrier profile of the HBT structure obtained by ECV 3. Results and Discussion The profile of the HBT structure is shown in Fig. 1. The measured N(x) profile is approximately corresponding to the values listed in Table 1. Any differences of the N(x) profile will be discussed later. The difference of the part of the N(x) profile of the interface (spacer layers) between the emitter and base can be influenced by nonplanar electrolyte±semiconductor interfaces. We have found from Talystep measurements that the profile of the bottom etch crater shows roughness. This roughness of the electrolyte can make a contact to more than one of the layers in this structure. These facts and also crystal defects influenced the etching process [2]. Further, the base layer (GaAs : Be) is deep, up to 0.8 mm, instead 0.75 mm, from the surface of the HBT structure. The measured concentration of the base is about 110 18 cm 3 instead of the specified 110 19 cm 3. The width of the collector (GaAs: Si) layer approximately corresponds to the designed width of the structure. However, the depth of the whole N(x) profile down to the substrate is 1.55 mm instead 1.3 mm. From the Talystep measurements the depth of the crater is approximately 1.73 mm. The depth of the crater has been checked at three places of the measured structure. The ECV profile of the photodiode is shown in Fig. 2. In the TEM micrograph (Fig. 3), the GaAs/GaAlAs and the substrate/buffer interfaces are clearly recognizable. Fig. 2. The carrier profile of the photodiode structure obtained by ECV

Carrier Profiling of a Heterojunction Bipolar Transistor 635 Fig. 3. Cross sectional TEM micrograph of the photodiode structure (the data in mm scale) The planned (Table 2) and the realized structure are somewhat different. The TEM photograph shows the real sizes of the structures. The total thickness of the AlGaAs layers (window and spacer) is 1.3 mm instead of the planned 1.17 mm; the other thicknesses show agreement with the planned structure. The observed discrepancy may be connected with the dark band in the middle of the window layer in the TEM image, corresponding to a dip in the SR profile; this might be caused by an unknown growth defect. The ECV profile shows agreement with the structure corrected in this way. The SR measurement (Fig. 4) shows the position of the interfaces; better agreement with the thickness can be achieved if we scale down the depth axis by a factor of about 1.16. The SR profile can be influenced by an inaccurate angle of the bevelled surface and by the behaviour of the GaAs/GaAlAs interface. The ECV measurement shows the precise targeted thicknesses for GaAs layers but the GaAlAs layer is thinner than realised. This discrepancy can result from the charge transfer process at the electrochemical dissolution. This deviation at the thin GaAlAs (spacer) layer is not remarkable. Fig. 4. Spreading resistance profile of the photodiode structure

636 R. Kinder et al.: Carrier Profiling of a Heterojunction Bipolar Transistor 4. Conclusions The well known ECV technique has been presented and it was demonstrated that the determination of the complete carrier profile may require additional, complementary techniques. Optimum etching conditions were determined. The role of the roughness of the etched craters in the possible measurement errors was pointed out. We anticipate that with the development of electrolyte systems which are less sensitive to crystal defects a better crater flatness can be achieved. In spite of these limitations the ECV technique is a simple and effective tool for profiling of multilayer structures. Acknowledgments This work was supported, in part, by the Ministry of Education of the Slovak Republic (Grant No. 1/4219/99) and by the (Hungarian) National Scientific Research Fund (OTKA) (Grant No. T 030426). The photodiode sample was provided by A. Salokatve, H. Asonen and M. Pessa (Tampere University of Technology). The SR measurements were carried out at the Department of Electron Devices of the Technical University of Budapest with the assistance of G. Ve gh. References [1] T. Ambridge, J. L. Stevenson, and R. M. Redstall, J. Electrochem. Soc. 127, 222 (1980). [2] A. C. Seabugh, W. R. Frensley, R. J. Matyi, and G. E. Cabaniss, IEEE Trans. Electr. Devices 36, 309 (1989). [3] J. JakobovicÏ, J KovaÂcÏik, J. KovaÂcÏ, M. TomasÏka, J. S Ï kriniarovaâ, and A. S Ï atka, Electrical Engineering 48, 152 (1997). [4] F. Riesz, B. Szentpali, I. Mojzes, A. Salokatve, H. Asonen, and M. Pessa, Mat. Sci. Forum 69, 81 (1991). [5] AÂ. Barna, G. RadnoÂczi, and B. PeÂcz, in: Handbook of Microscopy Vol. 3, Chap. II/3, Eds. S. Amelinckx, D. van Dyck, J. van Landuyt, and G. van Tendeloob, VCH, 1997 (p. 751). [6] AÂ. Nemcsics, phys. stat. sol. (a) 173, 405 (1999).