EECS5 - Digital Design Lecture - Combinational Logic Circuits Part Feburary 26, 22 John Wawrzynek Spring 22 EECS5 - Lec-cl Page
Combinational Logic (CL) Defined y i = f i (x,...., xn-), where x, y are {,}. Y is a function of only X. If we change X, Y will change immediately (well almost!). There is an implementation dependent delay from X to Y. Spring 22 EECS5 - Lec-cl Page 2
Full-adder cell (FA) revisited: Adders a bcin FA cout s a b cin cout s cin ab ab cin cout s Spring 22 EECS5 - Lec-cl Page 3
Carry-ripple Adder Each cell: ri = ai XOR bi XOR cin cout = aicin + aibi + bicin = cin(ai + bi) + aibi 4-bit adder: Full adder cell What about subtraction? Spring 22 EECS5 - Lec-cl Page 4
A - B = A + (-B) Subtractors How do we form -B?. complement B 2. add bn- b b an- a a SUB cout n-bit adder cin sn- s s Spring 22 EECS5 - Lec-cl Page 5
Adders (cont.) Ripple Adder c7 c6 c5 c4 c3 c2 b a c FA s7 s6 Ripple adder is inherently slow because, in general s7 must wait for c7 which must wait for c6 T α n, Cost α n How do we make it faster, perhaps with more cost? c s Spring 22 EECS5 - Lec-cl Page 6
Carry Select Adder b7 a7 b6 a6 b5 a5 b4 a4 b3 a3 b2 a2 b a b a c FA c8 b7 a7 b6 a6 b5 a5 b4 a4 s3 s2 s s FA s7 s6 s5 s4 T = T ripple_adder / 2 + T MUX COST =.5 * COST ripple_adder + (n+) * COST MUX Spring 22 EECS5 - Lec-cl Page 7
Carry Select Adder Extending Carry-select to multiple blocks b5-b2 a5-a2 b-b8 a-a8 b7-b4 a7-a4 b3-b a3-a 4-bit Adder 4-bit Adder 4-bit Adder cout 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder cin What is the optimal # of blocks and # of bits/block? If # blocks too large delay dominated by total mux delay If # blocks too small delay dominated by adder delay N stages of N bits T α sqrt(n), Cost 2*ripple + muxes Spring 22 EECS5 - Lec-cl Page 8
Carry Select Adder b5-b2 a5-a2 b-b8 a-a8 b7-b4 a7-a4 b3-b a3-a 4-bit Adder 4-bit Adder 4-bit Adder cout 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder cin T total = sqrt(n) T FA assuming T FA = T MUX For ripple adder T total = N T FA Is sqrt(n) really the optimum? From right to left increase size of each block to better match delays Ex: 64-bit adder, use block sizes [3 2 9 8 7] How about recursively defined carry select? Spring 22 EECS5 - Lec-cl Page 9
Carry Look-ahead Adders In general, for n-bit addition best we can achieve is delay α log(n) How do we arrange this? (think trees) First, reformulate basic adder stage: a b c i c i+ s carry kill k i = a i b i carry propagate p i = a i b i carry generate g i = a i b i c i+ = g i + p i c i s i = p i c i Spring 22 EECS5 - Lec-cl Page
Carry Look-ahead Adders Ripple adder using p and g signals: c a b p g s = p c c = g + p c s a b p g s = p c c 2 = g + p c s a 2 b 2 p 2 g 2 s 2 = p 2 c 2 c 3 = g 2 + p 2 c 2 s 2 a 3 b 3 p 3 g 3 s 3 = p 3 c 3 c 4 = g 3 + p 3 c 3 s 3 c 4 So far, no advantage over ripple adder: T α N Spring 22 EECS5 - Lec-cl Page
Expand carries: c c = g + p c Carry Look-ahead Adders c 2 = g + p c = g + p g + p p c c 3 = g 2 + p 2 c 2 = g 2 + p 2 g + p p 2 g + p 2 p p c c 4 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g +...... Why not implement these equations directly to avoid ripple delay? Lots of gates. Redundancies (full tree for each). Gate with high # of inputs. Let s reorganize the equations. Spring 22 EECS5 - Lec-cl Page 2
Carry Look-ahead Adders Group propagate and generate signals: p i c in g i p i+ g i+ P = p i p i+ p i+k G = g i+k + p i+k g i+k- + + (p i+ p i+2 p i+k )g i p i+k g i+k c out P true if the group as a whole propagates a carry to c out G true if the group as a whole generates a carry C out = G + PC in Group P and G can be generated hierarchically. Spring 22 EECS5 - Lec-cl Page 3
a b a b a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 c a b Carry Look-ahead Adders P a G a c 3 = G a + P a c P b G b c 6 = G b + P b c 3 9-bit Example of hierarchically generated P and G signals: P = P a P b P c a 6 b 6 a 7 b 7 a 8 b 8 c P c G c c 9 = G + Pc G = G c + P c G b + P b P c G a Spring 22 EECS5 - Lec-cl Page 4
c p g s p g c = g +p c c P 8 =p p G 8 =g +p g 8-bit Carry Look-ahead Adder with 2-input gates. P c =P 8 P 9 s c 2 p g2 c 2 =G 8 +P 8 c P 9 =p 2 p 3 G c =G 9 +P 9 G 8 s 2 p 3 g3 c 3 = g 2 +p 2 c 2 G 9 =g 3 +p 3 g 2 c 4 =G c +P c c P e =P c P d s 3 c 4 p 4 g4 c 4 P a =p 4 p 5 c 8 =G e +P e c G e =G d +P d G c s 4 p 5 g5 s 5 c 5 = g 4 +p 4 c 4 G a =g 5 +p 5 g 4 c 6 =G a +P a c 4 P d =P a P b c p 6 6 g6 P b =p 6 p 7 G d =G b +P b G a s 6 p 7 g7 c 7 = g 6 +p 6 c 6 G b =g 7 +p 7 g 6 s 7 c 8 Spring 22 EECS5 - Lec-cl Page 5
Adders in FPGAs Spring 22 EECS5 - Lec-cl Page 6