Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.

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Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1

Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors Signed binary numbers Signed binary addition and subtraction Overflow Binary multiplication Chapter 5 2

Iterative Combinational Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells Chapter 5 3

Block Diagram of a 1D Iterative Array Example: n = 32 Number of inputs =? Truth table rows =? Equations with up to? input variables Equations with huge number of terms Design impractical! Iterative array takes advantage of the regularity to make design feasible Chapter 5 4

Functional Blocks: Addition Binary addition used frequently Addition Development: Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance. Chapter 5 5

Functional Block: Half-Adder A 2-input, 1-bit width binary adder that performs the following computations: X 0 0 1 1 C S 0 0 0 1 0 1 1 0 A half adder adds two bits to produce a two-bit sum The sum is expressed as a sum bit, S and a carry bit, C The half adder can be specified as a truth table for S and C + Y + 0 + 1 + 0 + 1 X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Chapter 5 6

Logic Simplification: Half-Adder The K-Map for S, C is: This is a pretty trivial map! By inspection: S Y 1 0 1 C Y 0 1 S = X Y + X Y = X Y X 1 2 3 X 2 1 3 S = (X + Y) (X + Y) and C = X Y C = ( ( X Y) ) These equations lead to several implementations. Chapter 5 7

Five Implementations: Half-Adder We can derive following sets of equations for a halfadder: (a) S = X Y + X Y C = X Y (b) S = (X + Y) (X + Y) C = X Y (c) S = ( C+ X Y) C = X Y (d) S = (X + Y) C C = (X + Y) (e) S = X Y C = X Y (a), (b), and (e) are SOP, POS, and XOR implementations for S. In (c), the C function is used as a term in the AND- NOR implementation of S, and in (d), the C function is used in a POS term for S. Chapter 5 8

Implementations: Half-Adder The most common half adder implementation is: S = X Y C = X Y X Y S C (e) A NAND only implementation is: S = (X C = ( + Y) C ) ( X Y) X C S Y Chapter 5 9

Functional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of 1: Z 0 0 0 0 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 Z 1 1 1 1 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1 Chapter 5 10

Logic Optimization: Full-Adder Full-Adder Truth Table: Full-Adder K-Map: X Y Z C S 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 S Y C Y X 1 1 0 1 3 2 1 1 4 5 7 6 X 1 0 1 3 2 1 1 1 4 5 7 6 Z Z Chapter 5 11

Equations: Full-Adder From the K-Map, we get: S = X Y Z + X Y Z + X Y Z + C = X Y + X Z + Y Z The S function is the three-bit XOR function (Odd Function): S = The Carry bit C is 1 if both X and Y are 1 or if the sum is 1 and a carry-in (Z) occurs. Thus C can be rewritten as: C = X X Y Y + (X Z Y) Z The term X Y is carry generate. X Y Z The term X Y is carry propagate. (why?) Chapter 5 12

Implementation: Full Adder Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, C i and C i+1, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for C i+1 ): C i+1 G i (G = Generate) OR (P =Propagate AND C i = Carry In) A i B i S i P i C i C i+1 = G + P i C i Chapter 5 13

Logic Diagram of Full Adder Chapter 5 14

Binary Adders To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i + 1 Description Subscript 3 2 1 0 Name Carry In 0 1 1 0 C i Augend 1 0 1 1 A i Addend 0 0 1 1 B i Sum 1 1 1 0 S i Carry out 0 0 1 1 C i+1 Chapter 5 15

4-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1-bit Full Adders: B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 FA C 3 C 2 C 1 FA FA FA C 0 C 4 S 3 S 2 S 1 S 0 Chapter 5 16

Ripple Carry Chapter 5 17

Carry Propagation & Delay One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit. The gate-level propagation path for a 4-bit ripple carry adder of the last example: A 3 B3 A 2 A 1 A 0 B 2 B 1 B 0 C 3 C 2 C 1 C 0 C 4 S 3 S 2 S 1 S 0 Note: The "long path" is from A 0 or B 0 though the circuit to S 3. Chapter 5 18

Carry Lookahead Given Stage i from a Full Adder, we know that there will be a carry generated when A i = B i = "1", whether or not there is a carry-in. A i B i Alternately, there will be G i a carry propagated if the half-sum is "1" and a carry-in, C i occurs. These two signal conditions P i are called generate, denoted as G i, and propagate, denoted as P i respectively and are identified in the circuit: C i+1 S i C i Chapter 5 19

Carry Lookahead (continued) In the ripple carry adder: Gi, Pi, and Si are local to each cell of the adder Ci is also local each cell In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells Defining the equations for the Full Adder in term of the P i and G i : P i = A B G = Ai Bi S = G + P i i i i = Pi Ci Ci+ 1 i i C i Chapter 5 20

Carry Lookahead Development C i+1 can be removed from the cells and used to derive a set of carry equations spanning multiple cells. Beginning at the cell 0 with carry in C 0 : C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 (G 1 + P 1 G 0 + P 1 P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Chapter 5 21

Carry Lookahead Adder Chapter 5 22