151 SIMULATION OF SEMICONDUCTOR DEVICES AND PROCESSES Vol. 3 Ediied by G. Baccarani, M. Rudan - Bologna (Italy) September 26-28,1988 - Tecnoprint ELECTRICAL PERFORMANCES EVALUATION OF ISOLATION STRUCTURES BY COUPLED PROCESS AND DEVICE SIMULATIONS. E. Dubois*, J.L. Coppee**, B, Baccus*, D. Collard* * Institut Superieur d'electronique du Nord 4l, Boulevard Vauban, 59046 LILLE Cedex, FRANCE ** Universite Catholique de Louvain, Laboratoire de Microelectronique, Place du Levant 3. 1348 LOUVAIN-LA-NEUVE, BELGIUM ABSTRACT Two-dimensional coupled process/device simulations have been used to characterize isolation properties of semi-recessed and fully-recessed LOCOS structures. The simulation results in excellent agreement with measurements demonstrate the sensitivity of the studied devices to the Si/SiO 2 interface shape, and thus outline the necessity of accurate simulation tools. INTRODUCTION Device isolation presents critical aspects for circuit packing density in VLSI. LOCal Oxidation of Silicon (LOCOS) is classically limited by the bird's beak extension and lateral diffusion of the channel-stop region into active transistor area. In order to evaluate new isolation processes (Hui, 1982; Sawada, 1935), numerous technological and device physics aspects have to be investigated to clarify important two dimensional (2D) parasitic effects, and so the use of coupled process/device simulations is of prime necessity. The IMPACT3 two dimensional device simulator, originally devoted to MOS transistor optimization, has been extended to isolation structure analysis (IMPACT3.2). This newly developed simulation program is automatically linked to the 2D process simulator IMPACT2 (Collard, 1986). In order to demonstrate the efficiency of this simulation system, a comparison between semi and fully-recessed isolation structures is presented and validated by experimental measurements.
152 DEVICE SIMULATION TOOL The ease in dealing with non-planar Si/Si0 2 interface and computational -time requirements constitute two important criteria for isolation modeling because of the large simulation area. Therefore, in order to take into account the typical nature of isolation structures, the following distinctive features have been developed. - Depending on bias conditions, either Poisson equation or Poisson and carriers continuity equations are solved by the finite-difference technique together with the box integration method. In the last case, the decoupled resolution strategy is used according to the low current mode of operation implied in this kind of device. - Special attention has been devoted to the formulation of discretized equations to suit an arbitrary Si/SiO 2 interface. An example of a 20 microns long meshed structure shows the consistency with the oxide shape issued from process simulation (fig. 1 ). - A non uniform mesh i ; automatically generated according to spatial key points such as field oxide boundaries, depth and lateral junctions location. - The four points discretization scheme leads to a regular filled matrix system that enables the application of an efficient and stable preconditioned conjugate gradient solver. FIO. 1-A : CONSISTENCY BETWEEN EXPERIMENTAL RESULTS, PROCESS AND DEVICE SIMULATIONS. SEM CROSS-SECTIONAL VIEW OF A BURIED SILO ISOLATION STRUCTURE
153-0.20-0.70.. -1.20-1.70-0.20-0.70-1.20-1.70-2.20-1.50-1.00-0.50 0.00 0.50 1.00 1.50-2.20 FIQ. 1-B : CONSISTENCY BETWEEN EXPERIMENTAL RESULTS, PROCESS AND DEVICE SIMULATIONS. BURIED SILO PROCESS SIMULATION AFTER THE FIELD OXIDE FORMATION. 17.00 17.30 18.0018.30 19.0019.30 20.00 FIG. 1-C : CORRESPONDING DEVICE SIMULATION. A PART OF THE 20 MICRONS LONG STRUCTURE AND A ZOOM OF THE BIRD'S BEAK REGION. THE Si/S 2 INTERFACE IS DESCRIBED BY DIAGONAL SEQMENTS BETWEEN TWO MESH POINTS.
154 APPLICATION AND VALIDATION Process description Table I outlines the main characteristics of the isolation structures that have been investigated. SEM cross-sectional views of both structures are shown in fig. 2. For each of them, two versions have been fabricated: - An aluminium gate version for which a 0.5 micron phospho-silicate-glass (PSG) layer was deposited prior the aluminium level (fig. 3). - A polysilicon gate version. In this case, the n* diffusion regions are self-aligned to the polysilicon. A 550 A' thick oxide layer of about 3 microns long exists between the field oxide mask and the edge of the poly mask (fig. 4). Semi recessed structure Fully recessed structure Field implant 2 13 cm" 2 at 25 Kev 2 13 cm" 2 at 25 Kev TABLE I Field oxidation step.000 C ->20 mn 950 C 370 mn Field oxide thickness 716 nm 735 nm n' region implant 5 15 cm" 2 at 1^0 Kev 5 15 cm" 2 at 1*»0 Kev Annealing 950 *c 45 mn 950 C ^5 mn FIG. 2 : SEM CROSS-SECTIONAL VIEW OF THE FIELD EDGE ISOLATION STRUCTURE (A) SEMI-RECESSED PROCESS (D) FULLY-RECESSED PROCESS
155 0.00.... 0.00-0.50.. ^\ 7..-0.50-1.00.. 5. -..-1.00-1.50.. 6-7 (A)..-1.50-2.00-2.00 -t- -t- +- +- -t- -1.50-1.00-0.50 0.00 0.50 1.00 1.50-2.00-1.50-1.00-0.50 0.00 0.50 1.00 1.50 2.00 FIG. 3 : ALUMINIUM GATE STRUTURES 2-D IMPURITIES EQUI-CONTOURS LINES (A) SEMI-RECESSED STRUCTURE (B) FULLY-RECESSED STRUCTURE
156-1.50-0.50 0.50 1.50 2.50 3.50-1,50-0.50 0.50 1,50 2.50 3.50 IMC. 'I : POLYSJUCON GATi; BTmiCTfHFS 2-D.1 MP'.innl F.S EQU1-CONTOURS LINK (A) sr>ij-ni-.cr.ssr.i> ST!H;CT;I:;K n<! Fu.LY-niiCF.ssF.:) STRUCTURF
157 Isolation properties The major difference between the semi-recessed and the fully-recessed structure is the bird's beak shape. The. oxide corners incorporated into the channel govern, in such a case, the current flowing in the overall structure, according to different potential barrier deformations. A more pronounced corner shape has tendency to reduce the field effect induced by the gate bias in the silicon region located under the bird's beak, and thus limits the total current. This last result explains the better isolation properties of the full-rox isolation structure compared to the semi-rox one: the ID-VG characteristics for both aluminium gate version (fig. 5) and polysilicon gate version (fig. 6) illustrate this point. An excellent agreement is found between measured and calculated drain currents that validates the simulation approach. ID (A) FULL LINES : EXPERIMENTAL RESULTS DASHED LINES : SIMULATION RESULTS VD= 0.05 VOLT VS= 0 VOLT VB= 0 VOLT VG (V) 20 25 30 35 40 45 50 55 60 FIG, 5 : ALUMINIUM GATE VERSION SIMULATED AND MEASURED ID-VG CHARACTERISTICS W/L= 0/20 -* 1(1-7 -fi -1 * r\ -5 A - -11-1? -n -M -15 ID (A) SEMI-ROX STRUCTURE FULL-ROX STRUCTURE FULL LINES : EXPERIMENTAL RESULTS DASHED LINES : SIMULATION RESULTS VD= 0,05 VOLT VS= 0 VOLT VB= 0 VOLT VG (V) 7.5 12.5 15 17.5 20 FIG. 6 : POLYSILICON GATE VERSION SIMULATED AND MEASURED ID-VG CHARACTERISTICS W/L= 0/20
158 Further simulations have been carried out on 2 and 7 microns long aluminium gate devices without the PSG layer, for a 5 volts drain bj.as condition. Characteristics plotted in fig. 7 demonstrate the sensitivity of the semi-recessed isolation structure to the n * to n * spacing (L). Byopposition, the fully-rocessed structure does not reveal this typical 1/L dependence in the subthreshold mode of operation (Goodwin, 198'-!). Indeed, the effective channel length is, in this case, reduced to the curved part of the field oxide interface and makes the whole parasitic transistor dominated by the two corner devices. -3 A -4-5 ' -fi! -7 ' -fl ' -q! - [ -11' -i?: -13 ID (A) DEVIC o 2 MIC a 7 MICRON VD=5V vs-ov VB=0V SEMI-R0X 12 CALCULATCi! ILi-VC V.. = 0 Vol I, i\'"s DEVICE LXNGHTS, = 3 Volts Sensibility to DIBL effect Simulations performed on two microns long devices have allowed to analyze the effect of Drain Induced Barrier Lowering (DIBL) combined to the corner effect. As the curved part of the interface located on the drain side requires more band bending to invert because of the drain controlled depletion region, the channel is firstly formed in the source region (fig. 8). Fig. 9 illustrates the potential distribution along the interface for gate bias varying from 0 to 15 volts. This result shows how the newly located potential barrier leads to a better immunity against the DIBL effect, for the fullv-rocessed isolation structure.
159 85 85 35 1 J #^ 6 (A) 1 2 3 4 5 6 20,9,8,,6 18» 0.00 1.00 2.00 3.00 4.00 5.00 6 A.. 0.35 0.85 i 1.35 1.85 2.35 35-1- 35 85-35- 85-2.354 0.00 (B).00 2.00 3.00.00 0.35-0.85 1.35 1.85 4 2.35 5.00 12$ 62. 124-.62. 12+ 62 12$.62, (C) 0.00.00 2.00 3.00 4.00 5.00 6.00 (D) 0.00.00 2.00 3.00 4.00 5.00 6.00 T - 0.62..1-1 -2 f - 0 1 12 12 62 12 62 12 62.12-1.62-2.12 42.62 FIG. 8 ELECTRON DENS:TY DISTRIBUTION DURING CHANNEL FORMATION SEMI-ROX STRUCTURE : ',A) VKiil<.= 5 volts, (B) VKnlc= 15.volts FULL-BOX STRUCTURE : (C) V = 5 volts, (D) V c» 15 volts
160-0.40 0.00 1.00 2.00 3.00 4.00 5.00 MICRONS) H 1 > 0.00 1.00 2.00 3.00 4.00 5.00 6.00 FIG. 9 : POTENTJA!. DIS'ITU RUT] ON ALONG THE ]NT2HFACE,t = 0 VoH, Vhll,k= O VcH, V,,, = 5 Volts, W= 0 microns (A) SEMI-n6x'ST!U;CTi:!tK (D) FULL-ROX STRUCTURE
161 CONCLUSION The use of a specialized 2D device simulator and the coupling with a 2D process simulation program has been described. The simple but efficient methods, used in this simulation approach, have proved the capabilities to investigate physics of new isolation structures. In particular, the obtained results have revealed a strong dependence of the isolation properties to the field oxide shape. Acknowledgements - E. Dubois is supported by le Centre National de la Recherche Scientifique (CNRS) and J.L. Coppee by I'Institut pour I' encouragement de la recherche scientifique dans I'Industrie et I'agriculture (IRSIA). REFERENCES Collard D. and K. Taniguchi (1986). IMPACT - a point defect based two dimensional process simulator : modeling the lateral oxidation enhanced diffusion of dopants in silicon. IEEE Transactions on Electron Devices, ED-34, 11, 2286-2290. Goodwin S.H. and J.D. Plummer (1984). Electrical performance and physics of isolation region structures for VLSI. IEEE Transactions on Electron Devices, ED-31, 7, 861-872. Hui J. and others (1982). Electrical properties of MOS devices made with SILO technology. IEDN Technical Digest, 220-223. Sawada S. and others (1985). Electrical properties of MOS LSI's fabricated using stacked oxide SWAMI technology. IEEE Transactions on Electron Devices, ED-32, 11, 2243-2248.