PINNING - TO220AB PIN CONFIGURATION SYMBOL

Similar documents
PINNING - TO220AB PIN CONFIGURATION SYMBOL

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PINNING - SOT223 PIN CONFIGURATION SYMBOL

PowerMOS transistor PINNING - SOT428 PIN CONFIGURATION SYMBOL. tab

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PINNING - SOT404 PIN CONFIGURATION SYMBOL

N-channel TrenchMOS transistor

TO220AB & SOT404 PIN CONFIGURATION SYMBOL

FEATURES SYMBOL QUICK REFERENCE DATA. V DSS = 55 V Very low on-state resistance Fast switching

PINNING - SOT223 PIN CONFIGURATION SYMBOL

FEATURES SYMBOL QUICK REFERENCE DATA

FEATURES SYMBOL QUICK REFERENCE DATA

P-channel enhancement mode MOS transistor

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Insulated Gate Bipolar Transistor (IGBT)

µtrenchmos standard level FET Low on-state resistance in a small surface mount package. DC-to-DC primary side switching.

PHD110NQ03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

PHP7NQ60E; PHX7NQ60E

PHP/PHB174NQ04LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

BUK A. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1.

PHP/PHB/PHD55N03LTA. TrenchMOS Logic Level FET

PMV40UN. 1. Product profile. 2. Pinning information. TrenchMOS ultra low level FET. 1.1 Description. 1.2 Features. 1.

PHP/PHB/PHD45N03LTA. TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

PMV56XN. 1. Product profile. 2. Pinning information. µtrenchmos extremely low level FET. 1.1 Description. 1.2 Features. 1.

N-channel µtrenchmos ultra low level FET. Top view MBK090 SOT416 (SC-75)

IRFR Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field effect transistor

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PMN40LN. 1. Description. 2. Features. 3. Applications. 4. Pinning information. TrenchMOS logic level FET

SI Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

PHM21NQ15T. TrenchMOS standard level FET

N-channel TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

TrenchMOS ultra low level FET

PHT6N06T. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

PINNING - TO220AC PIN CONFIGURATION SYMBOL. tab

PHP/PHD3055E. TrenchMOS standard level FET. Product availability: PHP3055E in SOT78 (TO-220AB) PHD3055E in SOT428 (D-PAK).

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.

PSMN004-60P/60B. PSMN004-60P in SOT78 (TO-220AB) PSMN004-60B in SOT404 (D 2 -PAK).

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PSMN002-25P; PSMN002-25B

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

BUK71/ AIE. TrenchPLUS standard level FET

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

BUK71/ AIE. TrenchPLUS standard level FET. BUK AIE in SOT426 (D 2 -PAK) BUK AIE in SOT263B (TO-220AB).

TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package.

BUK B. N-channel TrenchMOS standard level FET

PINNING - TO220AC PIN CONFIGURATION SYMBOL. tab

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

PINNING - SOT199 PIN CONFIGURATION SYMBOL. case a1

PINNING - TO220AC PIN CONFIGURATION SYMBOL. tab

PINNING - SOT93 PIN CONFIGURATION SYMBOL. tab

PINNING - SOT186 PIN CONFIGURATION SYMBOL

BUK A. N-channel TrenchMOS standard level FET

BUK9Y53-100B. N-channel TrenchMOS logic level FET. Table 1. Pinning Pin Description Simplified outline Symbol 1, 2, 3 source (S) 4 gate (G)

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17

DATA SHEET. BSN254; BSN254A N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS

N-channel TrenchMOS standard level FET

BUK71/ ATE. TrenchPLUS standard level FET. BUK ATE in SOT426 (D 2 -PAK) BUK ATE in SOT263B (TO-220AB).

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Logic level TOPFET APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PINNING - SOT404 PIN CONFIGURATION SYMBOL

PINNING - SOD100 PIN CONFIGURATION SYMBOL. case

BUK B. N-channel TrenchMOS logic level FET

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

TOPFET high side switch

N-channel TrenchMOS logic level FET

PINNING - SOT93 PIN CONFIGURATION SYMBOL. tab

FEATURES SYMBOL QUICK REFERENCE DATA GENERAL DESCRIPTION PINNING SOD59 (TO220AC)

PSMN4R5-40PS. N-channel 40 V 4.6 mω standard level MOSFET. High efficiency due to low switching and conduction losses

PSMN2R6-40YS. N-channel LFPAK 40 V 2.8 mω standard level MOSFET

PSMN8R3-40YS. N-channel LFPAK 40 V 8.6 mω standard level MOSFET

PSMN013-80YS. N-channel LFPAK 80 V 12.9 mω standard level MOSFET

BSH Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field-effect transistor

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

FEATURES SYMBOL QUICK REFERENCE DATA

N-channel TrenchMOS logic level FET

PSMN4R3-30PL. N-channel 30 V 4.3 mω logic level MOSFET. High efficiency due to low switching and conduction losses

N-channel TrenchMOS ultra low level FET. Higher operating power due to low thermal resistance Interfaces directly with low voltage gate drivers

PHB108NQ03LT. N-channel TrenchMOS logic level FET

Maximum Ratings, att j = 25 C, unless otherwise specified Parameter Symbol Value Unit Continuous drain current. IDpulse 88 E AS 90.

PHP110NQ08T. N-channel TrenchMOS standard level FET

N-channel TrenchMOS logic level FET

SMD version of BUK125-50L

Silicon Diffused Power Transistor

P-Channel Enhancement Mode Field Effect Transistor PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS

N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using

Silicon Diffused Darlington Power Transistor

Transcription:

GENERAL DESCRIPTION QUICK REFERENCE DATA Nchannel enhancement mode SYMBOL PARAMETER MAX. MAX. UNIT fieldeffect power transistor in a plastic envelope. BUK455 A B The device is intended for use in V DS Drainsource voltage V Switched Mode Power Supplies I D Drain current (DC) 41 38 A (SMPS), motor control, welding, P tot Total power dissipation 125 125 W DC/DC and AC/DC converters, and T j Junction temperature 175 175 C in automotive and general purpose switching applications. R DS(ON) Drainsource onstate resistance.38.45 Ω PINNING TO2AB PIN CONFIGURATION SYMBOL PIN 1 gate DESCRIPTION tab d 2 drain 3 source g tab drain 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drainsource voltage V V DGR Draingate voltage R GS = kω V ±V GS Gatesource voltage V A B I D Drain current (DC) T mb = 25 C 41 38 A I D Drain current (DC) T mb = C 29 27 A I DM Drain current (pulse peak value) T mb = 25 C 164 152 A P tot Total power dissipation T mb = 25 C 125 W T stg T j Storage temperature Junction Temperature 55 175 175 C C THERMAL RESISTANCES R th jmb Thermal resistance junction to mounting base 1.2 K/W R th ja Thermal resistance junction to K/W ambient April 1993 1 Rev 1.

STATIC CHARACTERISTICS V (BR)DSS Drainsource breakdown voltage V GS = V; I D =.25 ma V V GS(TO) Gate threshold voltage V DS = V GS ; I D = 1 ma 2.1 3. 4. V I DSS Zero gate voltage drain current V DS = V; V GS = V; T j = 25 C 1 µa I DSS Zero gate voltage drain current V DS = V; V GS = V; T j =125 C.1 1. ma I GSS Gate source leakage current V GS = ± V; V DS = V na R DS(ON) Drainsource onstate resistance V GS = V; I D = A BUK455A BUK455B.3.4.38.45 Ω Ω DYNAMIC CHARACTERISTICS g fs Forward transconductance V DS = 25 V; I D = A 8 13.5 S C iss Input capacitance V GS = V; V DS = 25 V; f = 1 MHz 16 pf C oss Output capacitance 5 7 pf C rss Feedback capacitance pf t d on Turnon delay time V DD = V; I D = 3 A; 25 ns t r Turnon rise time V GS = V; R GS = Ω; 9 ns t d off t f Turnoff delay time Turnoff fall time R gen = Ω 125 1 1 ns ns L d Internal drain inductance Measured from contact screw on 3.5 nh tab to centre of die L d Internal drain inductance Measured from drain lead 6 mm from package to centre of die 4.5 nh L s Internal source inductance Measured from source lead 6 mm 7.5 nh from package to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS I DR Continuous reverse drain current 41 A I DRM Pulsed reverse drain current 164 A V SD Diode forward voltage I F = 41 A ; V GS = V 1.4 2. V t rr Q rr Reverse recovery time Reverse recovery charge I F = 41 A; di F /dt = A/µs; V GS = V; V R = V. ns µc AVALANCHE LIMITING VALUE W DSS Drainsource nonrepetitive I D = 41 A ; V DD 25 V ; mj unclamped inductive turnoff V GS = V ; R GS = Ω energy April 1993 2 Rev 1.

1 1 9 PD% Normalised Power Derating 1 1 1 1 Tmb / C Fig.1. Normalised power dissipation. PD% = P D /P D 25 C = f(t mb ) 1.1.1 Zth jmb / (K/W) D =.5.2.1.5.2 BUKx55lv D = T T t.1 1E7 1E5 1E3 1E1 1E+1 t / s Fig.4. Transient thermal impedance. Z th jmb = f(t); parameter D = t p /T P D tp tp 1 1 9 ID% Normalised Current Derating 1 1 1 1 Tmb / C Fig.2. Normalised continuous drain current. ID% = I D /I D 25 C = f(t mb ); conditions: V GS V 15 VGS / V = BUK455A 4 2 4 6 8 VDS / V Fig.5. Typical output characteristics, T j = 25 C. I D = f(v DS ); parameter V GS 8 7 6 5 BUK455. RDS(ON) / Ohm 4.5 5 5.5 6 6.5 7 7.5 BUK455A RDS(ON) = VDS/ID A B tp = us us.15. 8 DC 1 1 VDS / V 1 ms ms ms Fig.3. Safe operating area. T mb = 25 C I D & I DM = f(v DS ); I DM single pulse; parameter t p.5 VGS / V = Fig.6. Typical onstate resistance, T j = 25 C. R DS(ON) = f(i D ); parameter V GS April 1993 3 Rev 1.

Tj / C = 25 BUK455A 1 4 3 VGS(TO) / V. typ. 2 min. 1 2 4 6 8 VGS / V Fig.7. Typical transfer characteristics. I D = f(v GS ) ; conditions: V DS = 25 V; parameter T j 1 1 Tj / C Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = 1 ma; V DS = V GS gfs / S BUK455A 1E1 SUBTHRESHOLD CONDUCTION 15 1E2 1E3 2 % typ 98 % 5 1E4 1E5 Fig.8. Typical transconductance, T j = 25 C. g fs = f(i D ); conditions: V DS = 25 V 1E6 1 2 3 4 VGS / V Fig.11. Subthreshold drain current. I D = f(v GS) ; conditions: T j = 25 C; V DS = V GS 2. a Normalised RDS(ON) = f(tj) C / pf BUKxy5 1.5 Ciss 1. Coss Crss.5 1 1 Tj / C Fig.9. Normalised drainsource onstate resistance. a = R DS(ON) /R DS(ON)25 C = f(t j ); I D = A; V GS = V VDS / V Fig.12. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = 1 MHz April 1993 4 Rev 1.

12 8 6 4 2 VGS / V VDS / V = BUK455 QG / nc Fig.13. Typical turnon gatecharge characteristics. V GS = f(q G ); conditions: I D = 41 A; parameter V DS 1 1 9 WDSS% 1 1 1 1 Tmb / C Fig.15. Normalised avalanche energy rating. W DSS % = f(t mb ); conditions: I D = 41 A IF / A BUK455A L + VDD Tj / C = 1 25 1 2 VSDS / V Fig.14. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j VGS VDS T.U.T. RGS ID/ R 1 shunt Fig.16. Avalanche energy test circuit. W DSS =.5 LI 2 D BV DSS /(BV DSS V DD ) April 1993 5 Rev 1.

MECHANICAL DATA Dimensions in mm Net Mass: 2 g 4,5,3 3,7 1,3 2,8 5,9 min 15,8 3, not tinned 1,3 (2x) 1 2 3 2,54 2,54 3, 13,5 min,9 (3x),6 2,4 Fig.17. TO2AB; pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostaticdischarge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for TO2 envelopes. 3. Epoxy meets UL94 V at 1/8". April 1993 6 Rev 1.

DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1993 7 Rev 1.