Hierarchical Bayesian Macromodeling for QA ircuits Saket Srivastava and Sanjukta Bhanja Department of Electrical Engineering University of South Florida, Tampa, USA (ssrivast, bhanja)@eng.usf.edu Abstract With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QA) circuits, we suggest a novel, theoretically sound, method for abstracting the behavior of circuit components in QA circuit using probabilistic macromodels. Standard QA circuit elements such as majority logic, lines, wire-taps, cross-overs, inverters, and corners are represented using conditional probability distributions defined over the output states given the input states. The probabilistic macromodels allow us to model QA circuits at an abstract level above the current practice of layout level; we term this higher level as the circuit level. The full circuit level model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate how this macromodel based circuit level representation can be used to infer ground state logic probabilities (cell polarizations). This can be used to study thermal behavior of QA circuits. We also show that the circuit level model is orders of magnitude faster and requires less space than the layout level models, making the design and testing of large QA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Introduction In recent years, there has been a surge in research on device level issues and characterization of nano-electronic components (beyond 6 2nm) based on scaled-mos gates, NTs, and QAs. Quantum-dot ellular Automata (QA) is an emerging technology that offers a revolutionary approach to computing at nano-level []. What sets it apart is that it tries to exploit, rather than treat as nuisance properties, the inevitable nano-level issue of device to device interaction to perform computing. Each cell consists of one or more electrons that can exists in two or more dots, with two ground states configurations that can be taken to represent the logic states of zero or one. Two or more cells interact by oulombic interaction, with an arrangement of cells settling to the lowest energy state. Since there is no flow of electrons involved, there is no need for traditional interconnects, and it has potential for extremely low-power computing, even below the traditional kt [2]. Both individual QAs cell (semi-conductor and metallic) and multiple QA arrangement have been fabricated and tested [3, 4]. Significant progress is also being made in using molecules to implement QAs [5, 6], which will make it possible to operate in room temperature, possibly alleviating the initial criticisms of this technology. It will also connect the areas of molecular computing and QAs. Time is ripe to look beyond just device level research in emerging devices and explore circuit level issues so as to scope out the types of circuits that can be built [7, 8, 9, ]. Hierarchical design at multiple levels of abstraction, such as architectural, circuit, layout, and device levels, has been a successful paradigm for the design of complex MOS circuits. It is only natural to seek to build a similar design structure for emerging technology []. It is not sufficient just to abstract an QA circuit in terms of - boolean logic based majority gates and other logic components, we have to also represent the probabilistic nature of the operations. Thus, for each logic variable X, we have to assign the probabilities associated with the logic values, i.e. P (X = ) or P (X = ). In the parlance of QA, the specific design variable is the polarization of cell, which is P (X = ) P (X = ). These probabilities (or polarizations), which are governed by quantum mechanics, are dependent on temperature, which is an important design variable for QAs that needs to be represented at upper design levels. Another need for probabilistic representations arise due to the nature of the QA operations. QA circuits are designed so that the intended logic is mapped to the lowest-energy (ground state) of the cell arrangement. So, it is important that the circuit be kept near ground state during operations, us-
ing mechanisms such as four-phased clocking. Logical errors in QA circuits can arise due to the failure to the settle to the ground state. We show that in this macromodel implementation of QA logic circuit the ground state polarization probabilities closely match with the the same obtained from a full layout level implementation for output nodes as well as the intermediate nodes in the circuit. We use this macromodel based circuit implementation to infer the ground state polarizations. Based on the above inference we demostrate the thermal behaviour of a QA logic circuit. There are several approximate simulators available at the layout level, such as the bistable simulation engine and the nonlinear approximation [2, 3, 4], however, these methods are iterative and do not produce steady state polarization estimates. In other words, they estimate just state assignments and not the probabilities of being in these states. The coherence vector based method [5, 4] does explicitly estimate the polarizations, but it is appropriate when one needs full temporal dynamics simulation (Bloch equation), and hence is extremely slow; for a full adder design with about 5 cells it takes about 5 seconds for 8 input vectors. Perhaps, the only approach that can estimate polarization for QA cells, without full quantum-mechanical simulation is the thermodynamic model proposed in [6], but it is based on semi-classical Ising approximation. In [7], it was shown that layout-level QA cell probabilities can be modeled using Bayesian probabilistic networks, much like those used for MOS-VLSI design to model switching [8]. We are not aware of any circuit-level modeling tools for QAs. In the next section, we summarize the quantummechanical nature of the probabilities associated with the QA cells. In Section 3, we show arrangements of QA cells can be modeled by a joint probability function, represented as a Bayesian network. Section 4 presents the theory behind the macromodels. We demonstrate how using these macromodels we can conduct (i) thermal studies (Section 5)and (ii) model full circuits (Section 6). We comment on the computational advantage of the circuit level representation over the layout level one in Section 7 and we conclude with Section 8. 2 Quantum Mechanical Probabilities In this section, we summarize how the state probabilities of a QA cell is dependent on the state probabilities of its layout neighbors, distance to the neighbors, and temperature. Each cell has 2 electrons that can occupy 4 possible dots. Among all the possible occupancy configurations, there are two lowest energy configurations corresponding to the diagonal occupancy of the cells. These represent the two logical states, or. So, following Tougaw and Lent [9] and other subsequent works on QA, we use the two-state approximate model of a single QA cell. We denote the two possible, orthogonal, eigenstates of a cell by and. The state at time t, which is referred to as the wave-function and denoted by Ψ(t), is a linear combination of these two states, i.e. Ψ(t) = c (t) + c 2 (t). Note that the coefficients are function of time. The expected value of any observable, Â(t), can be expressed in terms of the wave function as  = Ψ(t) Â(t) Ψ(t) or equivalently as Tr[Â(t) Ψ (t) Ψ(t) ], where Tr denotes the trace operation, Tr[ ] = +. The term Ψ(t) Ψ(t) is known as the density operator, ˆρ(t). Expected value of any observable of a quantum system can be computed if ˆρ(t) is known. A 2 by 2 matrix representation of the density operator, in which entries denoted by ρ ij (t) can be arrived at by considering the projections on the two eigenstates of the cell, i.e. ρ ij (t) = i ˆρ(t) j. This can be simplified further. ρ ij (t) = i ˆρ(t) j = i Ψ(t) Ψ(t) j = ( i Ψ(t) )( j Ψ(t) ) = c i (t)c j (t) () The density operator is a function of time and using Loiuville equations we can capture the temporal evaluation of ρ(t) in Eq. 2. i h tρ(t) = Hρ(t) ρ(t)h (2) where H is a 2 by 2 matrix representing the Hamiltonian of the cell and using Hartree approximation. Expression of Hamiltonian is shown in Eq. 3 [9]. H = = [ 2 i E kp i f i γ 2 γ i E kp i f i [ 2 E P ] (3) k γ γ 2 E P k where the sums are over the cells in the local neighborhood. E k is the kink energy or the energy cost of two neighboring cells having opposite polarizations. f i is the geometric factor capturing electrostatic fall off with distance between cells. P i is the polarization of the i-th cell. And, γ is the tunneling energy between two cell states, which is controlled by the clocking mechanism. The notation can be further simplified by using P to denote the weighted sum of the neighborhood polarizations i P if i. Using this Hamiltonian the steady state polar- ] 2
b c A B MAJ (a) (b) (c) Figure. Majority logic (a) QA cell layout (b) Bayesian network model (c) Macromodel ization is given by P ss = = Eq. 4 can be written as λ ss 3 = ρss ρ ss E E k P 2 P tanh( E 2 P k 2 /4+γ 2 k 2 +4γ 2 kt ) Out (4) P ss = E tanh( ) (5) Ω where E =.5 i E kp i f i, the total kink energy, Ω = Ek 2 P 2 /4 + γ 2, the Rabi frequency, and = Ω kt is the thermal ratio. We use the above equation to arrive at the probabilities of observing (upon making a measurement) the system in each of the two states. Specifically, P (X = ) = ρ ss =.5( + P ss ) and P (X = ) = ρ ss =.5( P ss ), where we made use of the fact that ρ ss + ρ ss =. 3 Level Model of ell Arrangements To enable us to form macromodels of various cell arrangement, we need to represent the joint state probabilities of a collection of cells at the layout level. In this section, we summarize how this joint probability can be efficiently represented using Bayesian networks, as shown in [7]. We will use the majority logic arrangement of QA cells in Fig. (a) to illustrate the process. Each cell is represented by a random variable, taking on two possible values. We represent the joint probability among these random variables as a a Bayesian network[2], which is a probability distribution defined over a Directed Acyclic Graph (DAG). The nodes of the DAG represent the cell states and a set of directed links connecting pairs of these nodes. The links represent causal dependencies among the variables. An example is shown in Fig. (b). For QA circuits these cause-effect directions would be determined by direction of propagation of quantum-mechanical information propagation with change in input. locks determine the causal order between cells. Within each clock zone, ordering is determined by the direction of propagation of the wave function [9]. For our (unclocked) majority logic, information would first reach cell M, followed by cell, resulting in the link directions shown. Since the oulombic interaction between cells fall off faster than the fifth power of the distance between them, we need to consider links between cells that are within a small neighborhood of each other, typically 2 cell distance. Each node has a conditional probability table (PT) capturing the probabilities of that node, given the states of the parent (cause) nodes. For example, the node M, will be associated with the conditional probability P (m a, b, c). The product of these PTs determine the joint probability distribution over all the variables in the network. Thus, the joint probability P (a, b, c, m, o) = P (m a, b, c)p (o m, a, b, c). The polarization of the output cell O is a function of the remaining four cells in the layout. The center cell M is actually the one which gets polarized based on the majority of inputs. The output cell depicted here receives the polarization of the central cell M and also the three inputs, A, B, and. The interaction between the output cell and the central cell will be much more than the inputs. This is because the kink energy (which determines the amount of interaction between two neighboring cells), decays as the fifth power of distance. In general, a Bayesian network encodes the joint probability function as a set of factored conditional probabilities, of minimal representational complexity. Proof of minimality can be found in standard Bayesian network texts such as [2]. P (x,, x n ) = m P (x k pa(x k )) (6) k= In the conditional probability term P (x pa(x)), pa(x) represents the values taken on by the parent set, P a(x). For a given set of possible parent node assignments, the conditional probability values are computed using the Hartree-Fock approximation, applied locally. The parent states are constrained to be as specified in the required conditional probability. We fix the children states (or polarization) so as to maximize Ω = Ek 2 P 2 /4 + γ 2, which would minimize the ground state energy over all possible ground states of the cell. Thus, the chosen chil- We use lowercase to indicate value of a random variable. i.e. P (x) denotes the probability of the event X = x or P (X = x) 3
dren states are ch (X) = arg max Ω = arg max ch(x) ch(x) i (P a(x) h(x)) E k P (7) The steady state density matrix diagonal entries (Eq. 5 with these children state assignments are used to decide upon the conditional probabilities in the Bayesian network (BN). P (X = pa(x)) = ρ ss (pa(x), ch (X)) P (X = pa(x)) = ρ ss (pa(x), ch (X)) (8) Probability of orrect Output orner orner 2 rossbar Invertertap(y) Invertertap(z) HF-SA BN Line(B) Majority(,,) Majority(,,) Majority(,,) Majority(,,) Majority(,,) Majority(,,) Majority(,,) Majority(,,) Wiretap 4 ircuit Level Macromodels The underlying premise of the macromodeling is that if the joint probability distribution function P (x,, x n ) over all the n cells in the layout is available, using the process outlined in the Section 3, then we can always obtain the exact distribution over subset of cells by marginalizing the probabilities over rest of the variables. For instance, the joint probability over just three cells, x i, x j, and x k, can be obtained by P (x i, x j, x k ) = x m,m i,j,k P (x,, x n ) (9) The macromodels of different circuit elements are the conditional probability of output cells given the values of the input cells. We compute this by marginalizing over the internal cells. For example, the majority logic macromodel is given by P (o a, b, c), which we can compute by m P (m, o a, b, c). Given the joint probability specification P (X = x,, X n = x n ), as captured by the Bayesian network (BN) representation, we need to compute: What is the expected polarization of a cell, X k, given the polarization of input cells, X,, X r? For this, we need to compute P (x k x,, x r ). This can be done using averaged likelihood propagation in the BN, discussed later in this section. The expected polarization would simply be the difference of the conditional probability of the two states of X k. To compute the marginal probability, we adopt the cluster based exact inference scheme [2, 7]. In this scheme, the original DAG is first transformed into a junction tree of cliques and then marginal probabilities are computed by local message passing between the neighboring cliques. Figure 2. Validation of the Bayesian network modeling of QA circuits with Hartree-Fock approximation based coherence vectorbased quantum mechanical simulation of same circuit. Probabilities of correct output are compared for basic circuit elements. In Fig. 2 we present validation of the Bayesian net model against the quantum-mechanical Hartree-Fock, Self onsistent Analysis (HF-SA) based estimates, which is the current computational gold standard for basic QA circuit elements, such as corners, cross-bars, wiretaps, and inverter taps, in addition to wires (9-cell line) and majority gate. We see that the estimates agree with each other very well. 5 Thermal Studies with Macromodels As the goal of this work is to present a macromodel based circuit design in QA that closely matches the polarization probabilities at the output and the intermediate nodes of the circuit at all temperatures, we present some thermal studies of the macromodel to illustrate the kinds of computations we can perform with them. Fig. 3(d) shows the thermal study plots for the majority gate in Fig.. The macromodel probability distribution is defined over the output and the 3 input nodes. At a temperature of K, if inputs are, and then the probability of output node is at state is.999963. As the temperature is increased, this probability decreases. We also notice that the thermal behavior is dependent on the input values. Note that, for correct operation, the probability of correct output should be greater than.5. In the rest of this section, we present results for two other building blocks: clocked majority gate and inverter. A locked majority gate, shown in Fig. 4(a), consists of two clocking zones. The input and output cells are placed 4
Input A B M Out Pout Input Input Input B (a) (b) (c) 2 3 4 5 6 7 8 9 Figure 3. Probability of the correct output value for a 5 cell majority gate shown in Fig. at different temperatures and for different inputs. Pout Input Input Input Input in a different clock zone unlike a simple majority gate. A clocked majority gate is the building block for most QA layout structures, since it has been seen that the circuits are most reliable when majority gates are clocked separately from the outputs. This is done in order to synchronize all the input signals reaching the majority gate irrespective of the path length they had to traverse to reach the majority gate. We also see from the graph shown in Fig. 4(d) that at lower temperatures the probability of the output being at state or state are almost the same as a simple majority gate. But at a higher temperatures, there is a greater drop in Pout values of a clocked majority gate compared to a simple majority gate, for the same set of inputs. This is because of the larger number of cells involved, increasing the overall uncertainty. Inverter shown in Fig. 5(a) is another basic building block of QA architecture. We have modeled the inverter in a single clock zone. It consists of an input and an output. The thermal variation is shown in Fig. 5(d). As we can see in this graph the output probability of an inverter falls rapidly with rise in temperature. This can account for a large drop in probability of large circuits that contain a large number of inverters. 6 ircuit Level Modeling One fairly well studied QA circuit is a full adder, for which many designs have been proposed [2]. In this section, we present the comparison and results of two different types of adder designs that we modeled using our macromodel design blocks. Apart from the basic building blocks presented before, we also used macromodels for crossovers and wire-taps in these designs. Table 2 3 4 5 6 7 8 9 (d) Figure 4. locked majority gate. (a) QA (b) level Bayesian net model (c) Macromodel (d) Thermal variation of the probability of the correct output for different inputs. lists all the symbols used for macromodel design blocks that we have used in designing both the Adders. We model the circuit level QA network also as Bayesian Networks, where each line in the circuit shown in Fig. 6b are nodes in the Bayesian Networks. Each signal (node) can be either an primary input, or an output cell of a macroblock like line, inverter etc. The links are directed from the input to the output and are quanitied by the device macromodels. Thus, we arrive at directed acyclic graph easily from the circuit model (Fig.??). Fig. 6(a) shows the QA layout of one full adder architecture (Adder-). It consists of consists five majority gates with no inverters. Fig. 6(b) shows the corresponding circuit level macromodel using the basic building blocks that we have discussed in the previous section. Fig. 7 shows the probability of correct output of the sum and carryout lines at different temperatures, for different input, as computed by the layout and circuit level models. We can see the excellent match in the computed probabilities. We also see that there is a gradual decline in the output node probabilities of both layout model and the 5
macromodel with temperature. Input In INV Out Fig. 8(a) shows a second adder architecture (Adder-2), consisting of three majority gates and two inverters [2]. As can be seen from graphs in Fig. 9, that the difference in probability of correct output node in our macro model design is very low. We also see that in both layout and circuit levels designs, the probability of the output node is dependent on the input vector set. (a) (b) (c) 7 Experimental Results Pout 2 3 4 5 6 7 8 9 (d) Input = / Figure 5. Inverter (a) QA (b) level Bayesian net model (c) Macromodel (d) Thermal variation of the probability of the correct output for different inputs. Table. Abbreviations used in QA macromodel architecture of Adder- and Adder-2 shown in Fig. 6(c) and 8(c) Symbol Maj M Inv Line O I OT B Macromodel Simple Majority Gate locked Majority Gate Inverter Line Segment orner Inverter hain Odd Tap Even Tap rossover As we can see from the Table 3, the simulation time required to evaluate a circuit is orders of magnitude lower than that in QADesigner tool. Moreover, we see that the simulation timing for bayesian macromodels of the adder circuit are much lower than bayesian full layout model. The graphs depicted in Fig. 7 and Fig. 9 present the crux of this work. The drooping characteristic of output node polarization with rise in temperature is a universally known fact. What we have shown in this work (as depicted in these graphs) is that the polarization of the output node in our macromodel design is showing the same drooping characteristics and is almost the same as that of the full layout. We quantify the computational advantage of a circuit level macromodel with a layout level model, we consider the complexity of the inference based on the Bayesian net models for each of them. As we mentioned earlier, in the cluster-based inference scheme, the Bayesian Network is converted into a junction tree of cliques and the probabilistic inference is performed on the junction tree by local computation between the neighboring cliques of the junction tree by local message passing [2, 7]. Space complexity of Bayesian inference is O(n.2 max ) where n is the number of variables, max is the number of variables in the largest clique. Time complexity is O(p.2 max ), where p is the number of cliques in the junction tree. We tabulate the complexity terms for the two adder designs in Table 2, along with the corresponding values for n, p and max. We can see that macromodel is order of magnitude faster specially due to the reduction in max which would be important in synthesizing larger networks of QA cells. Another observation is that Adder 2 is less expensive in terms of computation even though polarization drops are more due to the presence of inverters. 8 onclusion We proposed an efficient Bayesian Network based probabilistic macromodeling strategy for QA circuit that can estimate cell polarizations, ground state probability, and 6
A B arry In A B in I I B M LINE out B B OT B B I B M O LINE I B B M MAJ I OT B I B B M O LINE B arry Out I I OT (a) (b) (c) Figure 6. A QA Full Adder circuit Adder- (a)qa cell layout(b) Macromodel representation(c)macromodel Bayesian network Table 2. and macromodel time (T c ) and space (T s )complexities. Please see text for an explanation max, n, and p. 7452 4592 9834 96 9954 6384 28 88 Adder Adder 2 Parameters Macromodel model Macromodel max 5 8 5 p 25 57 96 3 n 278 64 25 34 T c = p.2 max T s = n.2 max lowest-energy error state probability, without the need for computationally expensive quantum-mechanical computations. We showed that the polarization estimates at layout and circuit levels are in good agreement. The Bayesian macromodel should be useful for vetting circuit designs at higher levels of abstraction in terms of not only the ground state, but also polarization, thermal dependence, and error. We illustrated two full adder designs. We have excellent results available for larger circuits using our macromodel design approach. Some of the circuits that we have modelled are 4x multiplexer, 8x multiplexer, 2x2 multiplier and 4-bit adder. One possible future direction of this work involves the extension of the BN model to handle sequential logic. This is possible using an extension called the dynamic Bayesian networks, which have been used to model switching in MOS sequential logic [22]. Table 3. omparison between simulation timing of a Full Adder circuit in QADesigner(QD) and Genie Bayesian Network(BN) Tool for Full and Macromodel Simulation Time Adder- Adder-2 278 cells 25 cells QD oherence Vector 566 253 QD Bistable Approx. 5 3 QD Nonlinear Approx. 3.5 2 BN Full model 4.3 BN Macromodel.. References []. Lent and P. Tougaw, A device architecture for computing with quantum dots, in Proceeding of the IEEE, vol. 85-4, pp. 54 557, April 997. [2] J. Timler and. Lent, Maxwell s demon and quantum-dot cellular automata, Journal of Applied Physics, vol. 94, pp. 5 6, July 23. [3] A. Orlov, R. Kummamuru, R. Ramasubramaniam,. Lent, G. Bernstein, and G. Snider, locked quantum-dot cellular automata shift register, Surface Science, vol. 532, pp. 93 98, 23. 7
Ooutput Probability 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 out out (a) (b) 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 (c) out (d) out Figure 7. Probability of correct output for sum and carry of Adder- based on the layout-level Bayesian net model and the circuit level macromodel, at different temperatures, for different inputs (a) (,,) (b) (,,) (c) (,,) (d) (,,). 8
A B arry In A B A B G2 G4 I I B O MAJ LINE out A2 G B2 B3 G5 G G3 2 3 4 S B B B O MAJ INV MAJ G3 G6 G4 5 G9 G5 6 I INV G8 G2 I I LINE O G G7 A B in G6 G8 G7 G9 G2 (a) (b) (c) Figure 8. A QA Full Adder circuit Adder-2 (a)qa Fulladder cell layout (b)macromodel representation(c)macromodel Bayesian network [4] R. Kummamuru, A. Orlov, R. Ramasubramaniam,. Lent, G. Bernstein, and G. Snider, Operation of a quantum-dot cellular automata (qca) shift register and analysis of errors, IEEE Transactions on Apllied Physics, vol. 5, pp. 96 93, September 23. [5]. Lent, B. Isaksen, and M. Lieberman, Molecular quantum-dot cellular automata, Journal of American hemical Society, vol. 25, pp. 56 63, 23. [6] W. Hu, K. Sarveswaran, M. Lieberman, and G. H. Bernstein, High-resolution electron beam lithography and dna nano-patterning for molecular qca, IEEE Transactions on Nanotechnology, vol. 4, pp. 32 36, May 25. [7] M. Niemier, R. Ravichandran, and P. Kogge, Using circuits and systems-level research to drive nanotechnology, in IEEE International onference on omputer Design, pp. 32 39, 24. [8] R. Zhang, P. Gupta, L. Zhong, and N. Jha, Synthesis and optimization of threshold logic networks with application to nanotechnologies, in Design, Automation and Test in Europe onference and Exhibition, vol. 2, pp. 94 99, 24. [9] K. Walus, G. Schhof, Z. R., G. Jullien, and W. Wang, ircuit design based on majority gates for applications with quantum-dot cellular automata, opyright IEEE Asimolar onference on Signals, Systems, and omputers, 24. [] R. Zhang, P. Gupta, and N. Jha, Synthesis of majority networks for qca-based logical devices, International onference on VLSI Design, pp. 229 234, 25. [] S. Henderson, E. Johnson, J. Janulis, and P. Tougaw, Incorporating standard cmos design process methodologies into the QA logic design process, IEEE Transactions on Nanotechnology, vol. 3, pp. 2 9, March 24. [2] G. Toth and. Lent, Role of correlation in the operation of quantum-dot cellular automata, Journal of Applied Physics, vol. 89, pp. 7943 7953, June 2. [3] I. Amlani, A. Orlov, G. Snider,. Lent, W. Porod, and G. Bernstein, Experimental demonstration of electron switching in a quantum-dot cellular automata (qca) cell, Superlattices and Microstructures, vol. 25, no. /2, pp. 273 278, 999. [4] K. Walus, T. Dysart, G. Jullien, and R. Budiman, QADesigner: A rapid design and simulation tool for quantum-dot cellular automata, IEEE Trans. on Nanotechnology, vol. 3, pp. 26 29, March 24. [5] J. Timler and. Lent, Power gain and dissipation in quantum-dot cellular automata, Journal of Applied Physics, vol. 9, pp. 823 83, January 22. [6] Y. Wang and M. Lieberman, Thermodynamic behavior of molecular-scale quantum-dot cellular automata (QA) wires and logic devices, IEEE 9
2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 out out (a) (b) 2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 out out (c) (d) Figure 9. Probability of correct output for sum and carry of Adder-2 based on the layout-level Bayesian net model and the circuit level macromodel, at different temperatures, for different inputs (a) (,,) (b) (,,) (c) (,,) (d) (,,).
Transactions on Nanotechnology, vol. 3, pp. 368 376, Sept. 24. [7] S. Bhanja and S. Srivastava, Bayesian modeling of quantum-dot-cellular-automata circuits, NSTI Nanotech onference, May 25. [8] S. Bhanja and N. Ranganathan, Switching activity estimation of vlsi circuits using bayesian networks, IEEE Transactions on VLSI Systems, pp. 558 567, February 23. [9] P. Douglas Tougaw and. S. Lent, Dynamic behavior of quantum cellular automata, Journal of Applied Physics, vol. 8, pp. 4722 4736, Oct 996. [2] J. Pearl, Probabilistic Reasoning in Intelligent Systems: Network of Plausible Inference. Morgan Kaufmann, 988. [2] W. Wang, K. Walus, and G. Jullien, Quantum-dot cellular automata adders, in IEEE onference on Nanotechnology, vol., pp. 46 464, 23. [22] S. Bhanja, K. Lingasubramanian, and N. Ranganathan, Estimation of switching activity in sequential circuits using dynamic bayesian networks, Accepted for publication in International onference in VLSI Design, January 25.