ALU, Latches and Flip-Flops - PDF Free Download

CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing

Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades posted Excellent work!!! Regrade requests possible for 24hrs after grades are released Submit request via gradescope If not satisfied after the regrade, email me Deadlines coming up: HW assigned, due Monday at the beginning of the class 4 problems, 2 graded Zybook due at the beginning of the class Reminders Discussion session on Friday

Midterm 1 Results Average: 84.7 Median: 86.5 Standard Deviation: 16.3 Max: 18 Min: 37

3 Zero Extend 2 1 1 Arithmetic Logic Unit Example 2 A N N N B N F 2 A N ALU N Y B N 3 F F 2: Function A & B 1 A B 1 A + B 11 Not used 1 A & ~B 11 A ~B C out + [N-1] S 11 A - B 111 Not used N N N N 2 F 1: Y N

CSE14: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops Tajana Simunic Rosing

What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory Memory / Time steps x i s i y i Clock y i =f i (S t,x) s i t+1 =g i (S t,x) 6

Why do we need circuits with memory? Circuits with memory can be used to store data Systems have circuits that run a sequence of tasks Memory Hierarchy Registers Cache Main Memory Hard disk

Simplest memory element "remember" "data" "load" "stored value" 8

Flight attendant call button Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Logic circuit to implement this? Call button Cancel button Bit Storage Blue light 1. Call button pressed light turns on SR latch implementation Call=1 : sets to 1 and keeps it at 1 Cancel=1 : resets to Call button Cancel button Bit Storage Blue light 2. Call button released light stays on a Call button S Call button Cancel button Bit Storage Blue light Cancel button R Blue light 3. Cancel button pressed light turns off 9

SR Latch Analysis S = 1, R = : then = 1 and = R N1 1 S 1 N2 S =, R = 1: then = 1 and = R 1 1 N1 S N2 1

SR Latch Analysis S =, R = : prev = prev = 1 then = prev Memory! R N1 R N1 S N2 S N2 S = 1, R = 1: then =, = Invalid State NOT R S 1 1 N1 N2

What if a kid presses both call and cancel Call but ton Cancel but ton & then releases them? S R If S=1 and R=1 at the same time and then released, =? Can also occur also due to different delays of different paths may oscillate and eventually settle to 1 or due to diff. path delay 12 Blue light S R hold 1 1 1 1 1 not allowed S R t 1 1 1 1

SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R =, = 1) Reset: Make the output (S =, R = 1, = ) Hold: Keep data stored (S =, R =, = previous ) SR Latch Symbol R S

SR Latch Characteristic Equation To analyze, break the feedback path SR Latch Symbol R (t) R S ' S R (t+ ) S S R (t) (t+ ) 1 1 1 1 1 1 1 1 1 1 hold reset set 1 1 X not allowed 1 1 1 X (t) 1 R S X 1 X 1 characteristic equation (t+ ) = S + R (t) 1 1 1 1 11 State Diagram 11 11 1 1 1 1 11 1 11 14 1 SR

Avoiding S=R=1 Part 1: Level-Sensitive SR Latch Add input C Change C to 1 only after S and R are stable C is usually a clock () S Level-sensitive SR latch S1 C R R1

Clocks Freq 1 GHz 1 GHz 1 GHz 1 MHz 1 MHz Period.1 ns.1 ns 1 ns 1 ns 1 ns Clock -- Pulsing signal for enabling latches; ticks like a clock Synchronous circuit: sequential circuit with a clock Clock period: time between pulse starts Above signal: period = 2 ns Clock cycle: one such time interval Above signal shows 3.5 clock cycles Clock duty cycle: time clock is high 5% in this case Clock frequency: 1/period Above : freq = 1 / 2ns = 5MHz; 16

Clock question The clock shown in the waveform below has: 1ns A. Clock period of 4ns with 25MHz frequency B. Clock duty cycle 75% C. Clock period of 1ns with 1GHz frequency D. A. & B. E. None of the above 17

Avoiding S=R=1 Part 2: Level-Sensitive D Latch D C 1 1 D S D latch S 1 C R 1 1 R SR latch requires careful design so SR=11 never occurs D latch helps by inserting the inverter between S & R inputs Inserted inverter ensures R is always the opposite of S when C=1 18

D Latch Truth Table D R R D S S D X 1 1 1 D X 1 S R prev 1 1 1 1 prev

D Latch Summary Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (transparent) When =, holds its previous value (opaque) (Mostly) avoids invalid case = D Latch Symbol D

Level-Sensitive D Latches Assume that data in all latches is initially. Input Y=1 and Clk transitions from ->1. When Clk= again, the stored values in latches are: Y D1 1 D2 2 D3 3 D4 4 C1 C2 C3 C4 Clk Clk_A Clk_B A. 1=1, 2=, 3=, 4= for both clock A & B B. 1=1, 2=1, 3=1, 4=1 for clock A 1=1, 2=, 3=, 4= for clock B C. 1=1, 2=1, 3=1, 4=1 for both clocks D. More information is needed to determine the answer E. None of the above 21

D Flip-Flop Design & Timing Diagram D flip-flop D Dm D latch m Ds D latch s Cm Cs s master servant Clk Flip-flop: Bit storage that stores on the clock edge, not level Master-slave design: master loads when Clk=, then slave when Clk=1 22

D Flip-Flop: Characteristic Equation D Id D (t) (t+1) 1 1 2 1 1 3 1 1 1 Characteristic Equation (t+1) = D(t)

Bit Storage Overview SR latch S (set) R (reset) Level-sensitive SR latch S S1 C R R1 D C S R D latch D Clk D latch Dmm Cm master D flip-flop D latch Ds s Cs s servant S=1 sets to 1, R=1 resets to. Problem: SR=11 yield undefined. S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. SR can t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. Only loads D value present at rising clock edge, so values can t propagate to other flipflops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR but gate count is less of an issue today. 24

Comparison of latches and flip-flops D positive edge-triggered flip-flop D FF D G level-sensitive latch latch 25

D Flip-Flops Assume that the data in all D-FFs is initially. Input Y=1. When Clk goes from ->1, the stored values in D-FFs are: Y D1 1 D2 2 D3 3 D4 4 Two latches inside each flip-flop Clk Clk_A Clk_B A. 1=1, 2=, 3=, 4= for both clock A & B B. 1=1, 2=1, 3=1, 4=1 for clock A 1=1, 2=, 3=, 4= for clock B C. 1=1, 2=1, 3=1, 4=1 for both clocks D. More information is needed to determine the answer E. None of the above 26

Rising vs. Falling Edge D Flip-Flop The triangle means clock input, edge triggered D Symbol for rising-edge triggered D flip-flop rising edges Clk D Symbol for falling-edge triggered D flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 27

Enabled D-FFs Inputs:, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = : the flip-flop retains its previous state EN Internal Circuit Symbol D 1 D D EN

Additional D-FF Features Reset (set state to ) R synchronous: Dnew = R' Dold (when next clock edge arrives) asynchronous: doesn't wait for clock Preset or set (set state to 1) S (or sometimes P) synchronous: Dnew = Dold + S (when next clock edge arrives) asynchronous: doesn't wait for clock Both reset and preset Dnew = R' Dold + S (set-dominant) Dnew = R' Dold + R'S (reset-dominant) Selective input capability (input enable or load) LD or EN multiplexor at input: Dnew = LD' + LD Dold load may or may not override reset/set (usually R/S have priority) Complementary outputs and ' 29

Registers and Counters 3

Building blocks with FFs: Basic Register OUT1 OUT2 OUT3 OUT4 D D D D IN1 IN2 IN3 IN4 I3 I2 I1 I reg(4) 3 2 1 31

Shift register Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 IN D D D D 32

Pattern Recognizer Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 IN D D D D 33

Design of a Universal Shift Register left_in left_out clear s s1 output input right_out right_in clock clear s s1 new value 1 output 1 output value of FF to left (shift right) 1 output value of FF to right (shift left) 1 1 input Nth cell to N-1th cell D to N+1th cell CLEAR 1 2 3 s and s1 control mux [N-1] (left) Input[N] [N+1] (right)

Counters Sequences through a fixed set of patterns OUT1 OUT2 OUT3 OUT4 IN D D D D 35

General Counters Default operation: count up A-D counter output A-D parallel load data LOAD enables data load RCO ripple carry out CLR clears data EN counter enable "1" "" "1" "1" "" "" EN RCO D D C C B B A A LOAD CLR "1" "" "" "" "" EN RCO D D C C B B A A LOAD CLR 36

Finite State Machines 37

Circuit Specifications Combinational Logic Truth tables, Boolean equations, logic diagrams (no feedback) Sequential Networks: State Diagram (Memory) State and Excitation Tables Characteristic Expression Logic Diagram (FFs and feedback loops) Y A B C D Combinational X RTL: Register-Transfer Level Description 38

Finite State Machines: Two Bit Counter Example Symbol/ Circuit Current state Next State 2 bit Counter S S 1 S 1 S 2 S 2 S 3 S 3 S S 1 (t) (t) 1 (t+1) (t+1) S 3 S 1 S 2 State Diagram State Table

Circuit with 2 flip flops Circuit with one flip flop Which is the most likely circuit realization of the two bit counter? State Table 1 (t) (t) 1 (t+1) (t+1) 1 1 1 1 1 1 1 1 A. Combinational circuit Circuit with no flip flops B. C. (t) Combinational circuit 1 (t) D D (t) 1 (t) Combinational circuit D

Two Bit Counter Circuit State Table 1 (t) (t) 1 (t+1) (t+1) 1 1 1 1 1 1 1 1 (t) 1 (t) D D We store the current state using D-flip flops so that: Inputs to the combinational circuit don t change while the next output is computed The transition to the next state only occurs at the rising edge of the clock D (t) = (t) D 1 (t) = (t) 1 (t) + (t) 1 (t) Implementation of 2-bit counter

FSM Definition FSM consists of Set of states Set of inputs, set of outputs Initial state I a b A B Set of transitions Only one can be true at a time FSM representations: State diagram State table 42

FSM Example Wait u= s s ar ab ag ar Inputs: s,r,g,b,a; Outputs: u Is this FSM fully defined? A. Yes B. No Start a u= ar Red1 u= ab Blue ag Green ar Red2 a u= a u= a u=1 u= s Wait s Watch for transition properties! (note that more transitions need to be added) Start u= ar Red1 u= a ab ag ar Blue Green Red2 a a a u= u= u=1

FSM Controller Design Process with a 1. State Diagram 2. State Table 3. State Assignments 4. Excitation Table Three Bit Counter Example (present state, inputs; next state, outputs) 5. Circuit Excitation Table with Assigned State Patterns C3 C2 C1 N3 N2 N1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 1 3-bit up-counter FSM 11 Circuit 11 11 D D D 1 OUT1 OUT2 OUT3 44

Mealy and Moore Machines Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) x(t) C1 C2 y(t) x(t) C1 C2 y(t) Mealy Machine S(t) Moore Machine S(t)

This Counter Design Is: A. Moore machine 1 1 11 B. Mealy machine 3-bit up-counter 1 C. None of the above 111 11 11 OUT1 OUT2 OUT3 D D D 1

Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 1 from its life detection sensors, it means that the it has detected life on Mars and the output y(t) = 1, otherwise y(t) = (no life on Mars ). This pattern recognizer should have A.One state because it has one output B.One state because it has one input C.Two states because the input can be or 1 D.More than two states because. E.None of the above 47

Mars Life Recognizer FSM Which of the following diagrams is a correct Mealy solution for the 1 pattern recognizer on the Mars rover? 1/1 A. 1/ S / S1 / S2 / 1/ B. 1/ / S / S1 1/1 S2 1/ C. Both A and B are correct / D. None of the above 48

Mars Life Recognizer FFs Pattern Recognizer 1 1/ S / 1/ 1/1 S1 / S2 / x(t) C1 Mealy Machine What does state table need to show to design controls of C1? A.(current input x(t), current state S(t) vs. next state, S(t+1)) B.(current input, current state vs. current output y(t)) C.(current input, current state vs. current output, next state) D.None of the above C2 S(t) 49 y(t)

5 State Diagram => State Table with State Assignment 1/1 x(t) 1/ S / 1/ S1 / S2 / C1 C2 S(t) Mealy Machine y(t) S(t)\x 1 S S1, S, S1 S2, S, S2 S2, S,1 State Assignment S: S1: 1 S2: 1 S(t)\x 1 1,, 1 1,, 1 1,,1 1 (t+1) (t+1), y

State Diagram => State Table => Excitation Table => Circuit 1 (t) (t)\x 1 1,, 1 1,, 1 1,,1 x(t) C1 C2 S(t) Mealy Machine y(t) id 1 x D 1 D y 1 1 1 2 1 1 3 11 4 1 1 5 11 1 6 11 X X X 7 111 X X X 51

State Diagram => State Table => Excitation Table => Circuit id 1 x D 1 D y 1 1 1 2 1 1 3 11 4 1 1 5 11 1 6 11 X X X 7 111 X X X D1(t): x(t) 2 6 4 1 X 1 1 3 7 5 X D1(t) = x + x 1 D (t)= 1 x y= 1 x 1 52

State Diagram => State Table => Excitation Table => Circuit 1 x x D D1 D D 1 y 1 x x(t) D1(t) = x + x 1 D (t)= 1 x y= 1 x C1 C2 S(t) Mealy Machine y(t) 53

Moore FSM for the Mars Life Recognizer Which of the following diagrams is a correct Moore solution to the 1 pattern recognizer? 1/1 A. 1/ S / S1 / S2 / B. 1 S 1/ S1 1 S2 1 S3 1 1 C. Both A and B are correct D. None of the above 54

Moore Mars Life Recognizer: FF Input Specs Pattern Recognizer 1 1 S 1 S1 1 S2 1 S3 1 x(t) C1 C2 S(t) Moore Machine y(t) What does state table need to show to design controls of C2? A.(current input x(t), current state S(t) vs. next state, S(t+1)) B.(current input, current state vs. current output y(t)) C.(current state vs. current output y(t) and next state) D.(current state vs. current output y(t) ) E.None of the above 55

Moore Mars Life Recognizer: State Table 1 S S1 1 S2 1 S3 1 1 S(t)\x 1 S S1, S, S1 S2, S, S2 S2, S3, S3 S1,1 S,1 1 \x 1 1,, 1 1,, 1 1, 11, 11 1,1,1 1 (t+1) (t+1), y ID 1 x D 1 D y 1 1 1 2 1 1 3 11 4 1 1 5 11 1 1 6 11 1 1 7 111 1

Mars Life Recognizer: Combinational Circuit Design id 1 x D 1 D y 1 1 1 2 1 1 3 11 4 1 1 5 11 1 1 6 11 1 1 7 111 1 D1(t): D(t): y(t): x(t) x(t) x(t) 2 6 4 1 1 1 3 7 5 1 1 2 6 4 1 1 1 3 7 5 1 1 2 6 4 1 1 3 7 5 1 Sources: TSR, Katz, 1 Boriello & Vahid

Mars Life Recognizer Circuit Implementation State Diagram => State Table => Excitation Table => Circuit D D1 D D 1 y x(t) C1 C2 y(t) S(t) Moore Machine 58

15 cents for candy! Watch out no change! Moore machine outputs associated with state Reset N D + Reset Mealy machine outputs associated with transitions Reset/ (N D + Reset)/ [] N D N D / N N/ D 5 [] N D D/ 5 N D / N N/ D 1 [] N D D/1 1 N D / N+D N+D/1 15 [1] Reset 15 Reset /1 59

Example: Moore implementation D1 D Encode states and map to logic 1 D 1 Open 1 1 1 1 1 1 1 1 1 1 1 1 1 N N N X X 1 X X X 1 X X X 1 X D D 1 1 1 1 1 1 1 1 present state inputs next state output 1 D N D1 D open 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6

Example: Mealy implementation Reset/ Reset/ N/ D/ 5 N/ D/1 1 N+D/1 15 N D / N D / N D / Reset /1 Open 1 1 1 1 D X X 1 X 1 1 1 N present state inputs next state output 1 D N D1 D open 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 61

FSM design: Multiple input counter Given FSM of a multiple input counter, design the circuit implementing its functionality 1 11 S S2 1 1,1 1 11 1 S1 S3 1, 11 11 1 present next state output state 1 1 11 S S S1 S2 S3 1 S1 S S3 S1 S3 S3 S1 S S S3 S2 S1 S3 S2 S 1 State 1 11 1 Input 1 1 1 1 11 11 11 11 11 11 1 1 1 1 Inputs 1 11 1 State 1 11 1 62

Multiple input counter: Logic for D-FF Derive logic equations for inputs of State D-FF 1 11 1 Input 1 1 1 1 11 11 11 11 11 11 1 1 1 1 D1 1 11 1 I1I 1 11 1 D 1 11 1 I1I 1 11 1 63

New FF Design 64

FSM Design 1 a D 1 D y 1 1 1 1 1 1 1 1 1 1 1 1 65

Design FSM with Minimum Number of States If two inputs are equal during any four consecutive clock cycles, w 1 =w 2, the circuit produces output z=1; else, z=. 66

FSM Analysis 1A 1(t+1) (t+1) Y 1 1 11 1 11 11 111 67

Counter Design 68

Minimum POS of Decoder-Mux Circuit 69

Timing Constraints in Sequential Designs 7

Timing Constraints in Sequential Circuit Designs Combinational Our seemingly logically correct design can go wrong signals don t travel in zero time We next look at timing constraints for combinational and sequential logic.

Combinational Logic Timing I. Min delay of a gate, also called contamination delay: t cd Minimum time from when an input changes until the output starts to change II. Max delay of a gate, also called propagation delay: t pd Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing) 72

Combinational Logic: Output Timing Constraints A B C D Y Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both D. Neither 73

Combinational Logic: Output Timing Constraints A B C D Y Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A. Blue path B. Red path C. Both D. Neither 74

D-FF Input Constraints: Setup and Hold Times D S D latch D C D R D S D latch t setup t hold C t a R I. Setup time: t setup Time before the clock edge that data must be stable (i.e. not change) II. Hold time: t hold Time after the clock edge that data must be stable Aperture time: t a Time around clock edge that data must be stable (t a = t setup + t hold ) 75

Output Timing Constraints D t ccq t pcq I. Min delay of FF, also called contamination delay or min to delay: t ccq Time after clock edge that might be unstable (i.e., starts changing) II. Max delay of FF, also called propagation delay or maximum to delay: t pcq Time after clock edge that the output is guaranteed to be stable (i.e. stops changing) 76

The timing of which of the following signals can cause a setup-time violation? A. The input signal D(t) B. The output signal (t) C. Both of the above D. None of the above Comb Logic D(t) D (t) 77

Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) R1 1 C L T c D2 R2 Which of the following violations occurs if max delay of R1 is zero & max delay of the combinational circuit is equal to the clock period? 1 D2 (b) A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1 D. Setup violation for R1 E. None of the above

Setup Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay 1 C L D2 (a) R1 R2 Setup time constraint: 1 D2 (b) T c T c t setup + max delay(ff) + max delay(combinational) T c t pcq + t pd + t setup

Causes of Timing Issues in Sequential Circuits Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay (a) R1 1 C L D2 R2 Which of the violations would occur if the min delay of R1 was zero and the combinational circuit was just a wire? 1 D2 (b) T c A. Hold time violation for R2 B. Setup violation for R2 C. Hold time violation for R1 D. Setup violation for R1 E. None of the above

Hold Time Constraint Input to a FF comes from the output of another FF through a combinational circuit The FF and combinational circuit have a min & max delay 1 C L D2 (a) R1 R2 Hold time constraint: T c t hold < min delay(ff) + min delay(combinational) 1 t hold < t ccq + t cd D2 (b)

FF Timing Parameters Once a flip flop has been built, its timing characteristics stay fixed: t setup, t hold, t ccq, t pcq D1 1 D2 R1 Combinational R2 What about the clock? Does the clock edge arrive at the same time to all the D-FFs on the chip? 82

Clock Skew The clock doesn t arrive at all registers at the same time Skew: difference between the two clock edges Perform the worst case analysis delay 1 2 1 C L D2 R1 R2 t skew 1 2

Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 t pcq is max delay through FF, t pd is max delay through logic 1 2 1 C L D2 1 2 1 D2 R1 T c R2 T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) t pcq t pd t setup t skew

Hold Time Constraint with Skew In the worst case, 2 is later than 1 t ccq is min delay through FF, t cd is min delay through logic 1 1 C L D2 2 1 2 R1 R2 t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq 1 D2 t ccq t cd t skew t hold

Timing Analysis Example A B C X' X Timing Characteristics t ccq t pcq t setup t hold = 3 ps = 5 ps = 6 ps = 7 ps D t pd = 3 x 35 ps = 15 ps t cd = 25 ps Setup time constraint: T c (5 + 15 + 6) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? (3 + 25) ps > 7 ps? No!

Timing Analysis Example Add buffers to the short paths: A B C X' X Timing Characteristics t ccq t pcq t setup t hold = 3 ps = 5 ps = 6 ps = 7 ps D t pd = 3 x 35 ps = 15 ps t cd = 2 x 25 ps = 5 ps Setup time constraint: T c (5 + 15 + 6) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? (3 + 5) ps > 7 ps? Yes!

Sequential Circuit Design Summary SRAM memory, SR Latch, D Latch, D-FF Design procedure for FSMs 1. Capture FSM 2. Create state table 3. Assign the states 4. Excitation table 5. Implement the combinational logic Mealy vs. Moore FSM Non-ideal properties of FFs Setup/hold time constraints Maximum operating frequency Clock skew 88

MORE FSM EXAMPLES 89

FSM design: Multiple input counter Given FSM of a multiple input counter, design the circuit implementing its functionality 1 11 S S2 1 1,1 1 11 1 S1 S3 11 1 present next state output state 1 1 11 S S S1 S2 S3 1 S1 S S3 S1 S3 S3 S1 S S S3 S2 S1 S3 S2 S 1 State 1 11 1 Input 1 1 1 1 11 11 11 11 11 11 1 1 1 1 Inputs 1 11 1 State 1 11 1 93

Multiple input counter: Logic for D-FF Derive logic equations for inputs of State D-FF 1 11 1 Input 1 1 1 1 11 11 11 11 11 11 1 1 1 1 D1 1 11 1 I1I 1 11 1 D 1 11 1 I1I 1 11 1 94