UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours + 10 minutes for reading INSTRUCTIONS TO CANDIDATES 1. The total marks for this exam is 100 marks. 2. There are THREE (3) SECTIONS to this paper: Section A, Section B and Section C. 3. Answer ALL questions in the answer booklet provided. DO NOT OPEN THIS QUESTION PAPER UNTIL YOU ARE INSTRUCTED TO DO SO THIS QUESTION PAPER CONSISTS OF 9 PRINTED PAGES INCLUDING THIS PAGE
SECTION A: OBJECTIVE QUESTIONS (10 QUESTIONS, 10 MARKS) INSTRUCTION: Answer all questions 1. Convert the binary number 1001.0010 to decimal. A. 90.125 B. 9.125 C. 125 D. 12.5 2. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n): A. XNOR gate B. OR gate C. XOR gate D. NAND gate 3. Parity systems are defined as either or and will add an extra to the digital information being transmitted. A. positive, negative, byte B. upper, lower, digit C. on, off, decimal D. odd, even, bit 4. Which of the following is an important feature of the sum-of-products (SOP) form of expression? A. All logic circuits are reduced to nothing more than simple AND and OR gates. B. The delay times are greatly reduced over other forms. C. No signal must pass through more than two gates, not including inverters. D. The maximum number of gates that any signal must pass through is reduced by a factor of two. 5. Simplify the expression ((AB) + C) using DeMorgan's theorems. A. ((AB) ) + C B. ABC C. AB + C Page 2 of 9
D. (A + B) C 6. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output? A. 4 3 2 1 = 0111, C out = 0 B. 4 3 2 1 = 1111, C out = 1 C. 4 3 2 1 = 1011, C out = 1 D. 4 3 2 1 = 1100, C out = 1 7. Given the expression AB + CDE. Which of the following is the possible implementation? 8. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the outputs? A. A > B = 1, A < B = 0, A < B = 1 B. A > B = 0, A < B = 1, A = B = 0 C. A > B = 1, A < B = 0, A = B = 0 D. A > B = 0, A < B = 1, A = B = 1 9. What is the major difference between half-adders and full-adders? A. Nothing basically; full-adders are made up of two half-adders. B. Full adders can handle double-digit numbers. C. Full adders have a carry input capability. D. Half adders can handle only single-digit numbers. 10. If an active-high S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be. A. SET B. RESET C. clear D. invalid Page 3 of 9
SECTION B: TRUE/FALSE QUESTIONS (10 QUESTIONS, 10 MARKS) Instruction: Answer all TEN (10) questions by making a circle around T if the statement is TRUE or F if the statement is FALSE. 1. The octal number system consists of eight digits, 0 through 7. 2. An exclusive-or gate output is HIGH when the inputs are unequal. 3. A parity checker is constructed in the same way as a parity generator, except that in a 4-bit system there must be five inputs, and the output is used as the error indicator. 4. The product-of-sums (POS) is basically the ORing of ANDed terms. 5. A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. 6. The NAND gate is an example of combinational logic. 7. The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0 8. It is not necessary to have the same number of bits when adding or subtracting signed binary numbers in the 2's-complement system. 9. In a multiplexer, the data select control inputs are responsible for determining which data input is selected to be transmitted to the data output line. 10. A sequential circuit consists of a combinational circuit with storage elements that stores binary information which defines the state of the sequential circuit at that time. Page 4 of 9
SECTION C: SUBJECTIVE QUESTIONS (5 QUESTIONS, 80 MARKS) Instruction: Answer ONLY FIVE (5) questions out of the SIX (6) questions. Questions 1 a) Perform the following conversions: i. 1001101 2 to Hexadecimal ii. DEF 16 to Decimal iii. 65 8 to Hexadecimal [6 marks] b) Convert 27.315 10 to binary. c) Find the 10s complement of 99. d) Show the subtraction process of 5610 8 3410 8 performed using 2 s complement. [6 marks] Questions 2 For the Boolean expression X = A B C + A BC + A BC + ABC : a) Write down the truth table. b) Draw the circuit diagram. c) Find the Sum of Product expression. Page 5 of 9
d) Using Karnaugh Maps find the minimized expression. e) Draw the circuit diagram of the minimized expression. [3 marks] f) Implement the circuit using only NAND gates Questions 3 For the following Circuit diagrams [3 marks] a) Find the Boolean expression for F and G. b) Find the minimized expressions for the two. c) Draw the circuits of the minimized expressions. d) Draw the circuits of the minimized expressions using only NAND gates. Page 6 of 9
Questions 4 A Boolean circuit has two control inputs (C1, C2), two data inputs (X1, X2) and one output (Z). The network performs one of the logic operations AND, OR, EQU, or XOR (exclusive- OR) on the two data inputs. The function performed depends on the control inputs as follows: C1 C2 Function performed by network 0 0 AND 0 1 OR 1 0 EQU 1 1 XOR a) Derive a truth table for Z and find the Boolean expression for Z. [8 marks] b) Use a Karnaugh map to minimize the expression and draw the final logic circuit for Z. [8 marks] Questions 5 a) Derive the Boolean expressions of a half adder. b) Draw the circuit diagram of a half adder. c) Derive the minimized Boolean expressions for a full adder. [3 marks] d) Draw the circuit diagram for a full adder using the half adders. [3 marks] e) For building a multiplier with 4 bit multiplier x 3 bit multiplicand, how many AND gates and 4-bit adders are needed and how many resulting bits are the output of the multiplier. Page 7 of 9 [6 marks]
Questions 6 a) What is meant by sequential circuit? What is the difference between sequential & combinational circuit? b) Explain the operation of the following circuit? c) Design clocked S-R FF using NAND gate and write the truth table. d) Explain a general method for conversion from one type of FF to another type. Page 8 of 9
APPENDIX Theorems and Postulates of Boolean Algebra 1. Postulate 1 (a) x + 0 = x (b) x.1 = x 2. Postulate 2 (a) x + x' = 1 (b) x.x' = 0 3. Theorem 1 (a) x + x = x (b) x. x = x 4. Theorem 2 (a) x + 1 = 1 (b) x. 0 = 0 5. Theorem 3, involution (a) (x')' = x 6. Postulate 3, commutative (a) x + y = y + x (b) xy = yx 7. Theorem 4, associative (a) x + (y + z) = (x + y) + z (b) x(yz) = (xy)z 8. Postulate 4, distributive (a) x(y + z) = xy + xz (b) x + yz = (x + y)(x + z) 9. Theorem 5, De Morgan (a) (x + y)' = x'y' (b) (xy)' = x' + y' 10. Theorem 6, Absorption (a) x + xy = x (b) x(x + y) = x Page 9 of 9