Data Sheet August FN8. General Purpose NPN Transistor Array The consists of five general-purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the are well suited to a wide variety of applications in low-power systems at frequencies from DC to MHz. They may be used as discrete transistors in conventional circuits. However, they also provide the very significant inherent advantages unique to integrated circuits, such as compactness, ease of physical handling and thermal matching. Ordering Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. DWG. # - to Ld PDIP E. M9 (8) - to Ld SOIC Tape and Reel M. Applications Power Applications from DC to MHz General-Purpose Use in Signal Processing Systems Operating in the DC to 9MHz Range Temperature Compensated Amplifiers See Application Note, AN9 Application of the CA8 Integrated-Circuit Transistor Array for Suggested Applications Pinout (PDIP, SOIC) TOP VIEW Q Q Q Q SUBSTRATE 7 Q 9 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -7-7 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Absolute Maximum Ratings The following ratings apply for each transistor in the device: Collector-to-Emitter Voltage, V CEO.....................V Collector-to-Base Voltage, V CBO.......................V Collector-to-Substrate Voltage, V CIO (Note ).............V Emitter-to-Base Voltage, V EBO.........................V Collector Current, I C............................... ma Operating Conditions Temperature Range......................... - o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package................... N/A SOIC Package................... N/A Maximum Power Dissipation (Any one transistor).........mw Maximum Junction Temperature (Plastic Package)........ o C Maximum Storage Temperature Range......... - o C to o C Maximum Lead Temperature (Soldering s)............ o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. The collector of each transistor in the is isolated from the substrate by an integral diode. The substrate (Terminal ) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid undesirable coupling between transistors, the substrate (Terminal ) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = o C, For Equipment Design PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Collector-to-Base Breakdown Voltage V (BR)CBO l C = µa, I E = - V Collector-to-Emitter Breakdown Voltage V (BR)CEO I C = ma, I B = - V Collector-to-Substrate Breakdown Voltage V (BR)ClO I C = µa, I CI = - V Emitter-to-Base Breakdown Voltage V (BR)EBO I E = µa, I C = 7 - V Collector-Cutoff Current (Figure ) I CBO V CB = V, I E =, -. na Collector-Cutoff Current (Figure ) I CEO V CE = V, I B =, - (Figure ) µa DC Forward-Current Transfer Ratio (Figure ) h FE V CE = V, I C = ma - Electrical Specifications T A = o C, Typical Values Intended Only for Design Guidance PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS DC Forward-Current Transfer Ratio (Figure ) h FE V CE = V I C = ma I C = µa Base-to-Emitter Voltage (Figure ) V BE V CE = V I E = ma.7 V I E = ma.8 V V BE Temperature Coefficient (Figure ) V BE / T V CE = V, l C = ma -.9 mv/ o C Collector-to-Emitter Saturation Voltage V CE SAT I B = ma, I C = ma. V Noise Figure (Low Frequency) NF f = khz, V CE = V, I C = µa, R S = kω. db
Electrical Specifications T A = o C, Typical Values Intended Only for Design Guidance (Continued) PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS Low-Frequency, Small-Signal Equivalent- Circuit Characteristics: Forward Current-Transfer Ratio (Figure ) Short-Circuit Input Impedance (Figure ) Open-Circuit Output Impedance (Figure ) Open-Circuit Reverse-Voltage Transfer Ratio (Figure ) Admittance Characteristics: Forward Transfer Admittance (Figure 7) f = khz,v CE = V, I C = ma h FE - h IE. kω h OE. µs h RE.8 X - - f = MHz,V CE = V, l C = ma y FE - j. ms Input Admittance (Figure 8) y IE. + j. ms Output Admittance (Figure 9) y OE. + j. ms Reverse Transfer Admittance (Figure ) y RE See Figure - Gain-Bandwidth Product (Figure ) f T V CE = V, I C = ma MHz Emitter-to-Base Capacitance C EBO V EB = V, I E =. pf Collector-to-Base Capacitance C CBO V CB = V, I C =.8 pf Collector-to-Substrate Capacitance C ClO V C l = V, I C =.8 pf Typical Performance Curves COLLECTOR CUTOFF CURRENT (na) - - - I E = V CB = V V CB = V V CB = V - 7 TEMPERATURE ( o C) FIGURE. I CBO vs TEMPERATURE COLLECTOR CUTOFF CURRENT (na) - - - I B = V CE = V V CE = V 7 TEMPERATURE ( o C) FIGURE. I CEO vs TEMPERATURE
Typical Performance Curves (Continued) STATIC FORWARD CURRENT TRANSFER RATIO (h FE ) 9 8 7 V CE = V T A = o C h FE BASE-TO-EMITTER VOLTAGE (V).8.7.. V CE = V T A = o C V BE.. EMITTER CURRENT (ma) FIGURE. h FE vs I E.... EMITTER CURRENT (ma) FIGURE. V BE vs I E BASE-TO-EMITTER VOLTAGE (V) V CB = V.9.8.7 I E = ma. I E = ma I. E =.ma. -7 - - 7 TEMPERATURE ( o C) FIGURE. V BE vs TEMPERATURE NORMALIZED h PARAMETERS. V CE = V f = khz T A = o C h RE h IE h FE = h IE =.kω h RE =.88 x - h OE =.µs AT ma FIGURE. NORMALIZED h FE, h IE, h RE, h OE vs I C h OE h FE h RE h IE.... COLLECTOR CURRENT (ma) FORWARD TRANSFER CONDUCTANCE (g FE ) AND SUSCEPTANCE (b FE ) (ms) - COMMON T A = o EMITTER CIRCUIT, BASE INPUT C, V CE = V, I C = ma b FE g FE -. INPUT CONDUCTANCE (g IE ) AND SUSCEPTANCE (b IE ) (ms) COMMON EMITTER CIRCUIT, BASE INPUT T A = o C, V CE = V, I C = ma b IE g IE. FIGURE 7. y FE vs FREQUENCY FIGURE 8. y IE vs FREQUENCY
Typical Performance Curves (Continued) OUTPUT CONDUCTANCE (g OE ) AND SUSCEPTANCE (b OE ) (ms) COMMON EMITTER CIRCUIT, BASE INPUT T A = o C, V CE = V, I C = ma b OE. g OE REVERSE TRANSFER CONDUCTANCE (g RE ) AND SUSCEPTANCE (b RE ) (ms) -. -. -. COMMON EMITTER CIRCUIT, BASE INPUT T A = o C, V CE = V, I C = ma g RE IS SMALL AT FREQUENCIES LESS THAN MHz b RE -. FIGURE 9. y OE vs FREQUENCY FIGURE. y RE vs FREQUENCY GAIN BANDWIDTH PRODUCT (MHz) V CE = V T A = o C 9 8 7 7 8 9 COLLECTOR CURRENT (ma) FIGURE. f T vs I C
Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8., E., E8., E8., E. will have a B dimension of. -. inch (.7 -.mm). -B- A. (.) M C A A L B S A e C E C L e A C e B E. (JEDEC MS--AA ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -. -. A. -.9 - A..9.9.9 - B....8 - B..7..77 8 C.8... - D.7.77 8. 9.8 D. -. - E.. 7. 8. E..8. 7. e. BSC. BSC - e A. BSC 7. BSC e B -. -.9 7 L...9.8 N 9 Rev. /9
Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H A.(.) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ.(.) M B α L M h x o C M. (JEDEC MS--AB ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A..88..7 - A..98.. - B.... 9 C.7.98.9. - D.7. 8. 8.7 E.97.7.8. e. BSC.7 BSC - H.8..8. - h.99.9.. L....7 N 7 α o 8 o o 8 o - Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7