Politecnico di Torino - ICT School Analog and Telecommunication Electronics B6 - Non-linear circuits» Nonlinear circuits taxonomy» Log amplifiers: Error sources» Ratiometric, bipolar circuits» Saturating amplifier chain, RSSI» Circuit example AY 2015-16 07/03/2016-1 ATLCE - B6-2016 DDC 2016 DDC 1
Lesson B6: Nonlinear circuits Nonlinear circuits taxonomy Logarithmic amplifiers Parameters of a logarithmic transfer function Circuits: Error sources, Design procedure Exponential, ratiometric, bipolar circuits Saturating amplifier chain RSSI circuits References Elettronica per Telecom.: 2.2.3 Amplif logaritm. ed espon. Design with Op Amp : 13.1 - Log and antilog amplifiers 07/03/2016-2 ATLCE - B6-2016 DDC 2016 DDC 2
Nonlinear circuits Approximation of nonlinear transfer function Errors offset, gain nonlinearity : deviation from the designed behaviour Piecewise approximation Amplifiers with gain and offset related with specific input voltage Vi ranges» Active diode» Wave shaper» RSSI circuits Continuous approximation Need for a nonlinear element» Multipliers: squaring, root, polynomial function» Semiconductor junction: log or exponential function 07/03/2016-3 ATLCE - B6-2016 DDC 2016 DDC 3
Logarithmic amplifier: transfer function Generic log transfer function V o = k 1 log(k 2 (V i +k 4 )) + k 3 V i + X log X + V o k 4 k 2 k 1 k 3 k 2 and k 3 represent the same parameter Two degrees of freedom + one distortion Input offset k 4 Input slope k 2 Distortion: k 1 and k 3 07/03/2016-4 ATLCE - B6-2016 DDC 2016 DDC 4
Log amplifier: transfer diagram (linear) V o = k 1 log(k 2 (V i +k 4 )) + k 3 Representation on linear plot X axis: Vi; Y axis: Vo = log Vi Fixed ratio on Vi fixed shift on Vo Vi = 0?? Hard to see effects of k 4 Vo 5 4 3 2 1 1 2 4 8 16 Vi 07/03/2016-5 ATLCE - B6-2016 DDC 2016 DDC 5
Log amplif.: transfer diagram (half-log) V o = k 1 log(k 2 (V i +k 4 )) + k 3 Representation on semilog plot X axis: log k 2 V i Straight line: y = k 1 x + k 3 Changing k 1 modifies the slope (rotation) Changing k 3 (or k 2 ) causes a shift (translation) Changing k 4 causes nonlinearity for low Vi Vo k 1 k 2 k 3 V o = k 1 log(k 2 (V i +k 4 )) + k 3 k 4 log k 2 Vi 07/03/2016-6 ATLCE - B6-2016 DDC 2016 DDC 6
Effects of input offset k4 Input additive constant input offset The same offset (Δk4) corresponds to different shifts on the logvi axis The effect on output depends on the actual value of Vi Vo k4 k4 k4 logvi 07/03/2016-7 ATLCE - B6-2016 DDC 2016 DDC 7
Logarithmic element Functional specification: Vu = K log Vi» Wide dynamic» Low errors» Wide band». Exploit the V(I) relation in a PN junction Set the current I Read the voltage V V D = I V 07/03/2016-8 ATLCE - B6-2016 DDC 2016 DDC 8
Logarithmic amplifier: circuit Use transconductance Op. Amp. circuit Set the current»i = I 2 = I 1 = Vi / R R Read the voltage»v U = -V D Control the parameters»v I conversion at the input: k2 (and k3) I 2 V i I 1 I- V D - V d + D AO 1 V O V D =» Output gain: k1 (negative) Correct temperature-related errors:» Is: cancel with reference junction, constant current» Vt: correct with temperature-dependent gain element (NTC) 07/03/2016-9 ATLCE - B6-2016 DDC 2016 DDC 9
Basic circuit for logarithmic amplifiers Logarithmic junction Reference junction 07/03/2016-10 ATLCE - B6-2016 DDC 2016 DDC 10
Error sources Low input values: Low V across R1 Op. Amp. Offset (Voffset) Low I in the log junction Ioff and Ibias High input values: High currents Additional voltage drop on junction intrinsic resistance r BB Vo logvi 07/03/2016-11 ATLCE - B6-2016 DDC 2016 DDC 11
Total errors Overall transfer function (inverting) Errors caused by Ib, Ioff, Voff Error caused by r BB [mv] 07/03/2016-12 ATLCE - B6-2016 DDC 2016 DDC 12
Ratiometric logarithmic amplifier Log of voltage ratio log (x) log (y) = log (x/y) 07/03/2016-13 ATLCE - B6-2016 DDC 2016 DDC 13
Bipolar logarithmic amplifier Twin junctions to handle bipolar Vi (bidirectional current) Compression transcaracteristic If R diodes expander transcaracteristic 07/03/2016-14 ATLCE - B6-2016 DDC 2016 DDC 14
Applications of log amplifiers DC amplifiers: lin-log conversion (db, bode diagrams, ) (Analog computation ) After AM demodulation» Level measurement (IF chain, RSSI ),» Gain control (AGC) AC and bipolar amplifiers: Dynamic range compression AC-DC log converters Sequence of saturating stages Wide dynamic range level measurement 07/03/2016-15 ATLCE - B6-2016 DDC 2016 DDC 15
AC-DC log converters Piecewise approximation Sequence of amplifiers with breakpoint; two types A/1amplifiers:» Gain A for Vi < E; 1 for Vi > E» Direct output from last stage Vo A/0amplifiers:» Gain A for Vi < E; 0 (Vu = S = E*A) for Vi > E» output = sum of input + single amplifier outputs E Vi Obtained with saturating amplifiers Usually differential stages, with summation of currents As the level increases, the number of saturated stages increases 07/03/2016-16 ATLCE - B6-2016 DDC 2016 DDC 16
Saturating chain Eeach stage has Gain = 2, and saturates at Vo = S Stage 1 with gain for Vi < S/2; saturated for: Vo = 2 Vi, Stage 2 with gain for Vi < S/4; saturated for: Vo = 4 Vi, Stage 3 with gain for Vi < S/8; saturated for: Vo = 8 Vi, Stage 4 with gain for Vi < S/16; saturated for: Vo = 16 Vi, Total gain 0<Vi<S/8 active: 1, 2, 3, 4 G = 2 4 = 16 S/8<Vi<S/4 active: 1, 2, 3 saturated: 4 G = 2 3 = 8 S/4<Vi<S/2 active: 1, 2 sat.: 3, 4 G = 2 2 = 4 S/2<Vi<S active: 1 sat.: 2, 3, 4 G = 2 1 = 2 Saturation = gain 0: sum of the outputs 07/03/2016-17 ATLCE - B6-2016 DDC 2016 DDC 17
Chain with saturation Vi 1 2 3 4 Σ Vo Low Vi : all stages have gain High Vi: only first stages have gain Higher gain for lower Vi: 16, 8, 4, 2, 1 Vo Compression Vi 07/03/2016-18 ATLCE - B6-2016 DDC 2016 DDC 18
Saturating logarithmic amplifiers Good for AC, can provide wide band and wide dynamic AC-DC conversion on each stage Reduced dynamic on the single converter Applications: RF power measurement AGC for LNA and IF amplifiers Power control for PA RSSI (Received Signal Strength Indicator) output Carrier detection RF signal level Squelch control 07/03/2016-19 ATLCE - B6-2016 DDC 2016 DDC 19
Example of saturation log circuit 07/03/2016-20 ATLCE - B6-2016 DDC 2016 DDC 20
Limiting amplifier + RSSI 07/03/2016-21 ATLCE - B6-2016 DDC 2016 DDC 21
Log amplifiers Lab exercise: Design a log amplifier from the assigned specs Evaluate errors Verify with simulation Verify with measurements Specs: Provided each year in the lesson Design procedure: Sect 2, 2.P2 Lab experience: Sect 2, 2.L2 07/03/2016-22 ATLCE - B6-2016 DDC 2016 DDC 22
Design procedure Selection of circuit configuration Definition of current dynamic range Evaluation of error at upper range limit»r BB, maximum current Evaluation of errors at lower range limit» Op. Amp (Ib), minimum current Selection of Op. Amp. Current range selected to get balanced error at the dynamic range extremes Positioning input & output constants and parameters Gain and translation of Vu = log Vi Temperature compensation (if required) 07/03/2016-23 ATLCE - B6-2016 DDC 2016 DDC 23
: -: Lesson B6 final test Which are the techniques to obtain nonlinear transfer functions? How can Op Amp be used to get nonlinear transfer functions? How many parameters describe a log transfer function? Describe an application for logarithmic amplifiers Draw the diagram of a basic log amplifier. Which are the main error sources at low end of input range? - Which are the main error sources at high end of input range? Describe how to get nonlinear transfer functions using saturating amplifiers. Which is the meaning of the acronym RSSI? 07/03/2016-24 ATLCE - B6-2016 DDC 2016 DDC 24