Chapter 6 Frequency response of circuits. Stability

Similar documents
ESE319 Introduction to Microelectronics. Feedback Basics

Electronics II. Final Examination

CE/CS Amplifier Response at High Frequencies

ESE319 Introduction to Microelectronics. Feedback Basics

ECEN 326 Electronic Circuits

Feedback design for the Buck Converter

Electronics II. Midterm II

Stability of Operational amplifiers

H(s) = 2(s+10)(s+100) (s+1)(s+1000)

Electronics II. Final Examination

55:041 Electronic Circuits The University of Iowa Fall Exam 2

Chapter 10 Feedback. PART C: Stability and Compensation

ECEN 607 (ESS) Op-Amps Stability and Frequency Compensation Techniques. Analog & Mixed-Signal Center Texas A&M University

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Analysis and Design of Analog Integrated Circuits Lecture 12. Feedback

ELECTRONIC SYSTEMS. Basic operational amplifier circuits. Electronic Systems - C3 13/05/ DDC Storey 1

ECEN 325 Electronics

ECEN 325 Electronics

Designing Information Devices and Systems II Fall 2018 Elad Alon and Miki Lustig Discussion 5A

Operational Amplifiers

Refinements to Incremental Transistor Model

Homework Assignment 11

Steady State Frequency Response Using Bode Plots

FEEDBACK AND STABILITY

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

Frequency Response Analysis

I. Frequency Response of Voltage Amplifiers

EC Control Systems- Question bank

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ELECTRONICS & COMMUNICATIONS DEP. 3rd YEAR, 2010/2011 CONTROL ENGINEERING SHEET 5 Lead-Lag Compensation Techniques

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs

Systematic Design of Operational Amplifiers

Electric Circuits I Final Examination

Electronics II. Midterm #2

Frequency Dependent Aspects of Op-amps

Single-Time-Constant (STC) Circuits This lecture is given as a background that will be needed to determine the frequency response of the amplifiers.

Automatic Control (MSc in Mechanical Engineering) Lecturer: Andrea Zanchettin Date: Student ID number... Signature...

ECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF

As an example of the parameter sweeping capabilities of LTSPICE, consider the following elementary high-pass filter circuit:

Frequency response. Pavel Máša - XE31EO2. XE31EO2 Lecture11. Pavel Máša - XE31EO2 - Frequency response

Electronics II. Midterm II

The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A =

(b) A unity feedback system is characterized by the transfer function. Design a suitable compensator to meet the following specifications:

Chapter 2 Switched-Capacitor Circuits

Circuits Practice Websheet 18.1

University of Pennsylvania Department of Electrical and Systems Engineering ESE 319 Microelectronic Circuits. Final Exam 10Dec08 SOLUTIONS

R a) Compare open loop and closed loop control systems. b) Clearly bring out, from basics, Force-current and Force-Voltage analogies.

Solution: K m = R 1 = 10. From the original circuit, Z L1 = jωl 1 = j10 Ω. For the scaled circuit, L 1 = jk m ωl 1 = j10 10 = j100 Ω, Z L

R10 JNTUWORLD B 1 M 1 K 2 M 2. f(t) Figure 1

EE221 Circuits II. Chapter 14 Frequency Response

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

CURRENT SOURCES EXAMPLE 1 Find the source voltage Vs and the current I1 for the circuit shown below SOURCE CONVERSIONS

EE221 Circuits II. Chapter 14 Frequency Response

Sample-and-Holds David Johns and Ken Martin University of Toronto

University of Illinois at Chicago Spring ECE 412 Introduction to Filter Synthesis Homework #4 Solutions

ECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 1-19 in the exam: please make sure all are there.

Microwave Oscillators Design

Lecture 46 Bode Plots of Transfer Functions:II A. Low Q Approximation for Two Poles w o

OPERATIONAL AMPLIFIER APPLICATIONS

Problem Set 5 Solutions

Frequency Response. Re ve jφ e jωt ( ) where v is the amplitude and φ is the phase of the sinusoidal signal v(t). ve jφ

Stability and Frequency Compensation

Second-order filters. EE 230 second-order filters 1

Multistage Amplifier Frequency Response

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

LECTURE 21: Butterworh & Chebeyshev BP Filters. Part 1: Series and Parallel RLC Circuits On NOT Again

Chapter 8: Converter Transfer Functions

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

6.302 Feedback Systems

Electronics II. Midterm #2

EECS 105: FALL 06 FINAL

ECE3050 Assignment 7

CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Miller Pole Splitting and Zero

Homework Assignment 09

Homework Assignment 08

University of Toronto. Final Exam

Homework 7 - Solutions

Solution: Based on the slope of q(t): 20 A for 0 t 1 s dt = 0 for 3 t 4 s. 20 A for 4 t 5 s 0 for t 5 s 20 C. t (s) 20 C. i (A) Fig. P1.

Analog Circuits Prof. Jayanta Mukherjee Department of Electrical Engineering Indian Institute of Technology - Bombay

Boise State University Department of Electrical Engineering ECE461 Control Systems. Control System Design in the Frequency Domain

2nd-order filters. EE 230 second-order filters 1

Homework 6 Solutions and Rubric

Lecture 25 ANNOUNCEMENTS. Reminder: Prof. Liu s office hour is cancelled on Tuesday 12/4 OUTLINE. General considerations Benefits of negative feedback

Exercise s = 1. cos 60 ± j sin 60 = 0.5 ± j 3/2. = s 2 + s + 1. (s + 1)(s 2 + s + 1) T(jω) = (1 + ω2 )(1 ω 2 ) 2 + ω 2 (1 + ω 2 )

Chapter 9: Controller design

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE Branch GATE Paper The order of the differential equation + + = is (A) 1 (B) 2

Fig. 2.0: SPICE Loop Gain Test

Conventional Paper-I Part A. 1. (a) Define intrinsic wave impedance for a medium and derive the equation for intrinsic vy

Module 2. DC Circuit. Version 2 EE IIT, Kharagpur

ESE319 Introduction to Microelectronics Bode Plot Review High Frequency BJT Model

EKT 119 ELECTRIC CIRCUIT II. Chapter 3: Frequency Response of AC Circuit Sem2 2015/2016 Dr. Mohd Rashidi Che Beson

Chapter 3 Output stages

EE 16B Final, December 13, Name: SID #:

Unit 21 Capacitance in AC Circuits

ECEN 326 Electronic Circuits

Voltage AmpliÞer Frequency Response

Transcription:

Chapter 6 Frequency response of circuits. Stability

6.. The frequency response of elementary functions

6... The frequency bandwidth

6... The frequency bandwidth /A/(dB ) A 0 3dB min max

6... The frequency response of elementary functions

6... The frequency response of elementary functions A constant /A 0 / (db) 0 lg(a 0 ) lg A 0 ct. ϕ (A 0 ) lg

A simple zero /A / (db) 0dB/dec A j 0 0 ϕ (A ) 90 o 45 o 0 /0 0 0 0 45 o /dec lg lg A 0 lg 0 << 0 A 0 >> 0 A 0 lg 0 ϕ 0 ( A ) arctg

A simple pole -0 ϕ (A ) /A / (db) 0 /0 0 0 0-0dB/dec lg lg A A 0 lg << j 0 A 0 0 >> 0 A 0 lg 0 0-45 o -90 o -45 o /dec ϕ 0 ( A ) arctg

A simple zero in origin /A 3 / (db) 0 0dB/dec A 3 j 0 ϕ (A 3 ) 90 o 0 lg A 3 0 lg 0 45 o lg ϕ o ( A ) 3 90

A simple pole in origin /A 4 / (db) lg A 4 j 0-0 ϕ (A 4 ) 0-0dB/dec A 4 0 lg 0-45 o lg ϕ o ( A ) 4 90-90 o

A multiple zero in origin /A 5 / (db) 0n 0n db/dec A 5 j 0 n ϕ (A 5 ) 90n o 45n o 0 lg lg A5 0 nlg 0 ϕ o ( A ) n 5 90

A multiple pole in origin /A 6 / (db) lg A 6 j 0 n -0n 0 ϕ (A 6 ) -0n db/dec A6 0 nlg 0-45n o lg ϕ o ( A ) n 6 90-90n o

A multiple zero /A 7 / (db) 0n db/dec A 7 j 0 n 0n ϕ (A 7 ) 90n o 45n o 0 /0 0 0 0 45n o /dec lg lg A 0 nlg 7 >> << 0 A 7 0 0 0 0 A7 n lg 0 ϕ 7 arctg 0 ( A ) n

A multiple pole 0n ϕ (A 8 ) -45n o -90n o /A 8 / (db) 0 /0 0 0 0-45n o /dec lg -0n db/dec lg A A 8 0 nlg 8 << j 0 0 A 8 n 0 >> 0 A8 0 n ϕ 0 lg 0 0 ( A ) n 8 arctg

Example /A/ (db) 80 60 40 A ( j) 0 4 j j 0 j 0 0 4 0 0-0 -40-60 ϕ (A) 80 o 35 o 90 o 45 o -45 o -90 o -35 o -80 o 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0

Example /A/ (db) 80 60 40 A ( j ) 0 3 j 4 0 j j 0 3 0 0 0-0 -40-60 ϕ (A) 80 o 35 o 90 o 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 45 o -45 o -90 o -35 o -80 o 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0

(a) (b) Z v a Z v v i Z v a Z v a v Z v v i v v v ) ( ) ( v Z v a Z v i Z v i Z Z Z -a v v i v v i -a v v i v v i 6..3. Miller theorem Z a a Z Z Z a Z Z v v v << << << << ;

6..3. Miller theorem

6.. Amplifiers with reaction

6... The block diagram of the amplifier with reaction

6... The block diagram of the amplifier with reaction X - X F F Y Y F XF X Y X F X X X F XF X Y X, Y are currents/voltages The global gain: Y X F F

6... Types of reaction - Positive reaction: > F F < - Negative reaction: < F > F Particular case: strong negative reaction X Defining loop transmission: T F >> X F it results T >> F ( << ) F - independent on amplifier F Conclusion: for strong negative reaction, the gain with reaction is function only on reaction

6... Types of reaction

6.3. eaction effects

6.3.. Amplifier de-sensitivity

6.3.. Amplifier de-sensitivity F F F F F d d d d ) ( F F F F F d F d d T F F (reaction factor)

6.3.. Distortion reduction

6.3.. Distortion reduction The reaction reduces the effect of distortions.

6.3.3. The improving of frequency response

6.3.3. The improving of frequency response For min Supposing that the direct amplifier is characterized by a first-order function: ( j) F min and that we have a constant negative reaction 0, it results: ( ) ( ) F j j j F F 0 j F min j F ( ) 0 / F / F0 /(db) Fmin 0dB/dec -0dB/dec lg resulting: ( j) j F min F 0 j F min F 0 0 j F min

equivalent with: ( j) F 0 F 0 0 j F min j F min ( ) F 0 ( ) F 0 0 0 It is possible to find the following form of (j): where: ( j) 0 j min j min 0 F 0 F 0 0 min F min F 0 0

Conclusion: The amplifier bandwidth is increased with the same factor of the gain decreasing. // 0 /(db) 0dB/dec min lg -0dB/dec

6.3.3. The improving of frequency response For max Supposing that the direct amplifier is characterized by a first-order function: F ( j ) F 0 j F max / F / F0 /(db) and that we have a constant negative reaction 0, it results: ( j ) F F ( j) ( j) 0 Fmax -0dB/dec lg resulting: ( j) F 0 F 0 0 j F max

equivalent with: ( j) F 0 F 0 0 F max F 0 j ( ) F 0 0 It is possible to find the following form of (j): where: 0 F 0 F 0 0 ( j ) 0 j max ( ) max F max F 0 0

Conclusion: The amplifier bandwidth is increased with the same factor of the gain decreasing. // 0 /(db) max lg -0dB/dec

6.3.3. The improving of frequency response / F (j)/ (db) /(j)/ (db) Conclusion: F0 / F (j)/ 0 lg ( F0 0 ) 0 /(j)/ min Fmin Fmax max lg

6.3.4. The impact on input/output resistances

6.3.4. The impact on input/output resistances The reaction changes input/output resistances in such a way that the amplifier with reaction simulates better an ideal amplifier. ( T ) i ' i for series reactions i ' i ( T ) for parallel reactions ( T ) o ' o for series reactions o ' o( T ) for parallel reactions

6.4. Circuits stability

6.4.. Algorithm for evaluating the stability of a circuit

6.4.. Algorithm for evaluating the stability of a circuit. Annulate the input voltage. Split the reaction loop in an arbitrary point 3. Apply a test voltage in this point, V test 4. Calculate the return voltage in the same point, V tr 5. Compute the eturn atio T V tr /V test 6. epresent the Bode diagrams for T 7. epresent an horizontal line at 80 o A. If the horizontal does not intersect the phase graphic, the circuit is stable B. If the horizontal intersects the phase graphic in a point A, from A represent a vertical axis which intersects the module diagram in point B a. if /T/ B > 0, the circuit is not stable b. if /T/ B 0 0, the circuit at the stability limit c. if /T/ B < 0, the circuit is stable. In this case it is possible to determine the phase margin: mark with C the point in which /T/ 0, represent a vertical axis from this point, which will intersect the phase diagram in point D. The phase margin is ϕ 80 o ϕ(d)

6.4.. Example

6.4.. Example Evaluate the stability of the following circuit v i C µf kω 0kΩ - 3 90kΩ v O a ( j ) 5 0 j 0 v 3 90kΩ V t kω 0kΩ a v V tr C µf

( ) ( ) ( ) ( ) ( ) ( ) ( ) [ ] 3 4 3 3 3 3 C C t t tr 0 j 0 j 0 j 0 T // C j C j a C j C j C j C j a T X // X // a V v a V V T

/A/ (db) 80 60 40 0 0-0 -40-60 ϕ (A) 80 o 35 o 90 o 45 o -45 o -90 o -35 o -80 o 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 The horizontal line does not intersect the phase diagram, so the circuit is stable.

6.4.3. Example

6.4.3. Example Evaluate the stability of the following circuit v i kω - 90kΩ C nf 3 9kΩ v O a ( j ) 5 0 j 0 v kω 90kΩ C nf 3 9kΩ V t a v V tr

( ) [ ] 3 3 3 3 3 C 3 t t tr 0 j 0 j 0 j 0 T // C j C j a C j a T X // a V v a V V T

/A/ (db) 80 60 40 0 0-0 -40-60 ϕ (A) 80 o 35 o 90 o 45 o -45 o -90 o -35 o -80 o 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 The horizontal line does not intersect the phase diagram, so the circuit is stable.

6.4.4. Exemple 3

6.4.4. Exemple 3 Evaluate the stability of the following circuit v i kω - 90kΩ C nf 3 9kΩ v O a ( j ) 5 0 j 0 j 5 0 v kω 90kΩ C nf 3 9kΩ V t a v V tr

( ) [ ] 5 3 3 3 3 3 C 3 t t tr 0 j 0 j 0 j 0 j 0 T // C j C j a C j a T X // a V v a V V T

/T/ (db) 80 60 40 0 0-0 -40-60 ϕ (T) 80 o 35 o 90 o 45 o -45 o -90 o -35 o -80 o -5 o -70 o B 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 ϕ 0 o A C D The horizontal line at 80 O intersects the phase diagram in A point, /T B / 0, so the circuit is at the stability limit ( ϕ 0).