Analytical Delay Models for VLSI Interconnects Under Ramp Input

Analytical Delay Models for VLSI Interconnects Under amp Input Andrew B. Kahng, Kei Masuko, and Sudhakar Muddu UCLA Computer Science Department, Los Angeles, CA 995-596 USA Cadence Design Systems, Inc., San Jose CA 9534 Silicon Graphics, Inc., Mountain View, CA 9439 abk@cs.ucla.edu, masuko@cs.ucla.edu, sudhakar@cs.ucla.edu Abstract Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical LC interconnections with ramp input, Elmore delay can deviate by up to % or more from SPICEcomputed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4% of SPICE-computed delay, and models based on both first and second moments are within 2:3% of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees. ply different input rise times, and obtain delay estimates from SPICE, Elmore delay and the proposed analytical delay model. Over our range of test cases, Elmore delay estimates can vary by as much as % from SPICE-computed delays. As the input rise time increases, Elmore delay deviates even further from SPICE-computed delays. In contrast, our single-pole delay estimates are within 4% of SPICE delays and our twopole delay estimates are within 2:3% of SPICE delays. Since our analytical models have the same time complexity of evaluation as the Elmore model, we believe that they are very useful for performance-driven routing methodologies. The organization of our paper is as follows. In Section 2 we discuss delay models which have been previously proposed for interconnect lines under step input. Section 3 presents a new analytical delay definition for interconnect lines under ramp input. Section 4 discusses various threshold delay models for single-pole approximation of the interconnecttransfer function; Section 5 gives various threshold delay models for two-pole approximation; and Section 6 extends our delay modeling approach to interconnection trees. Section 7 concludes with experimental results for various combinations of input rise times and interconnect parameters. Introduction Accurate calculation of propagation delay in VLSI interconnects is critical to the design of high speed systems, and transmission line effects now play an important role in determining interconnect delays and system performance. Existing techniques are based on either simulation or 2 Previous Delay Models Under Step Input (closed-form) analytical formulas. Simulation methods such as SPICE The transfer function of an LC interconnect line with source and load give the most accurate insight into arbitrary interconnect structures, but impedance (Figure ) can be obtained using ABCD parameters [] as are computationally expensive. Faster methodsbased on moment matching techniques are proposed in [2, 3, 4, 7], but are still too expensive to be used during layout optimization. Thus, Elmore delay [2], a H(s) = h i cosh(θh)+ ZS Z sinh(θh) + Z T [Z sinh(θh)+z S cosh(θh)] used delay model in the performance-driven synthesis of clock distribution and Steiner global routing topologies. However, Elmore delay = cannot be applied to estimate the delay for interconnect lines with ramp + b s + b 2 s 2 +:::+ b k s k () +::: first orderapproximation ofdelayunderstep input, is still the most widely input source; this inaccuracy is harmful to current performance-driven p q routing methods which try to determine optimal interconnect segment where θ = (r + sl)sc is the propagation constant and Z +sl = sc lengths and widths (as well as driver sizes). Previous moment-based approaches [2, 4, 7] can compute a response for interconnects under ramp input within a simulation-based methodology, but no previous ductance, and capacitance per unit length and h is the length of the line. is the characteristic impedance; r = h ;l = L h ;c = C h are resistance, in- work has given analytical delay estimation models based on the first few The variables b k are called the coefficients of the transfer function and moments. are directly related to the moments of the transfer function [8]. Expanding the transfer function into a Maclaurin series of s around s = leads ecently, [3] presented lower and upper bounds for the ramp input response; their delay model is the same as the Elmore model for ramp to an infinite series, and to compute the response the series is truncated input (we refer to this model as analytical ramp input model (T AD )in to desired order. The method of Padé approximation has been widely this paper). Delay estimates for the analytical ramp input model are off used to compute the response from the transfer function [, 2]. For by as much as 5% from SPICE-computed delays for 5% threshold the case of resistive source ( S ) and capacitive load (C L ) impedances, voltage, and the analytical ramp input model cannot be used to obtain the coefficient of s in the transfer function can be obtained as [8] b = threshold delay for various threshold voltages. The authors of [5] used S C + S C L + C 2 + C L. Elmore delay as an upper bound on the 5% threshold delay for C interconnection lines under arbitrary input waveforms. However, we find by considering a single interconnect line with resistive source and ca- Efficient delay estimates for interconnect lines are typically derived that Elmore delay is not at all close to SPICE-computed 5% threshold delay and, depending on the input slew time and driver resistance, from recursive application of the formula for a single line. Elmore delay pacitive load impedances; delay formulas for an interconnecttree come can be either greater or less than SPICE-computed delay (see Section 7 [2] is a first order delay estimate for interconnect lines under step input. below). This paper gives a new and accurate analytical delay estimate It is equal to the first moment of the system impulse response, i.e., the for distributed LC interconnects under ramp input. To experimentally coefficient of s or the first moment in the system transfer function H(s). validate our analysis and delay formula, we model VLSI interconnect Applying this definition to H(s) in Equation (), we see that the Elmore lines having various combinations of source, and load parameters, ap- delay is equal to the coefficient b. Principal author, to whom correspondence should be addressed: Sudhakar Muddu (muddu@mti.sgi.com). Andrew B. Kahng is currently on Sabbatical leave at Cadence Design Systems, ak@cadence.com. We use threshold delay to refer to delay measured from the point when the input signal is zero. To compute delay relative to the input signal, subtract the corresponding threshold delay of the inputsignal (e.g., for 5% threshold voltage, the delay for the inputramp is 2 ).

ZS Distributed LC line We now give two distinct derivations of an analytical ramp delay estimate. v (t) i (t) v (t) i (t) i (t) v (t) 2 2 Z T Elmore Definition. Applying Elmore s original definition of delay for step input [2] yields an analytical delay T AD for ramp input, i.e., Figure : 2-port model of a distributed LC line with source impedance Z S and load impedance Z T. By considering only one pole in the transfer function, i.e, approximating the denominator polynomial to only the first moment, the single pole response can be obtained as in [4, 5]. The single pole of the transfer function is equal to the inverse of the Elmore delay T ED. Hence, the delay at arbitrary thresholds of the single pole response can be directly related to Elmore delay (Elmore delay actually correspondsto the 63:2% threshold voltage of the single pole response). For example, delay at 5% threshold voltage is :69b, and delay at 9% threshold voltage is 2:3b. Although Elmore delay has been widely used for interconnect timing analysis, it cannot accurately estimate the delay for LC interconnect lines, which are the appropriate representation for interconnects whose inductive impedance cannot be neglected [6]. 2 More critically, Elmore delay cannot estimate delays when the input signal is a ramp. 3 Analytical amp Delay Definitions In practice, the input at any gate or root of a tree is a ramp with finite rise (or fall) time, and there are no published analytical delay models for ramp input. We now propose various ramp delay definitions and also compute analytical delay expressionsusing the first one or two moments of the transfer function. We discuss delay models for rising ramp input only, since our analyses can be easily extended for falling ramp input [9]. Voltage (a) Time Voltage Figure 2: A ramp input function: (a) finite ramp with rise time, and (b) finite ramp decomposed into two shifted infinite ramps. ising amp Input The finite rising ramp input shown in Figure 2 can be expressed in the time domain as v in (t) = [tu(t), (t, T )U(t, )] for all t where U(t) denotes the step function. The finite ramp input in the transform domain is V in (s)= [,e s,st ]. In the transform domain, the 2 output response is (b) V out (s)=v in (s)h(s)= s 2 [, e,st ]H(s) : 2 ecently, [8] have developeda more accurate analytical delay model consideringinductive effects based on the first and second momentsof the transfer function. Their modelgives accurate estimates compared to SPICE-computed delays, but is valid only for step inputs. Time Z T AD = tv out (t)dt (2) where v out (t) is the derivative of the output response under finite ramp input. Taking the Laplace transform of v out Z (t), Z Vout (s)= v out (t)dt, s tv out (t)dt +::: Equation (2) then implies that the analytical ramp input delay T AD in the time domain is equal to the first moment of the derivative of the response. In the transform domain, T AD is equal to the first moment (or coefficient of s) of the function V out(s), which is equal to s Vout(s).The derivative of the response in the transform domain is out (s) = (, s 2 +:::) + a s + a 2 s 2 +:::: + b s + b 2 s 2 +:::: Therefore, the analytical ramp input delay is T AD = 2 + b, a = 2 + T ED (3) where T ED is the Elmore delay for a step input (i.e., the first moment of the transfer function). Another definition of delay based on the formula given in [] yields the same result of Equation (3) [9]. Group Delay Definition. The concept of group delay was initially defined for step input by Vlach et al. [8]. We now give a group delay definition for computing ramp input delay similar to that in [8], and show that it converges to the same analytical expression of Equation (3). ecall that group delay is definedas the negative of the rate of change of the phase characteristic φ of the output responsev out (ω) with respect to frequency, at zero frequency, i.e., T GD = lim ω!, φ ω. To compute the phase characteristic of the output response, we first compute the output responsev out (s) in the transform domain and then substitute for the Laplace variable s = jω, i.e., V out (ω) =, ω 2 (, e, jωt ) H(ω) " # =, ω ( ωt2 2, ω3 T 4 +:::)+ j(, ω2 T 3 +:::) 3! 3! =, ω [M + jm 2 ] H(ω) H(ω) where M and M 2 are the real and imaginary parts of the input ramp function. Writing the transfer function in terms of numerator and denominator polynomials, H(ω) = (, a 2ω 2 +:::)+ j(a ω, a 3 ω 3 +:::) (, b 2 ω 2 +:::)+ j(b ω, b 3 ω 3 +:::) = N + jn 2 D + jd 2 Then, the phase characteristic of the output response is φ = tan, M 2 M + tan, N 2 N, tan, D 2 D. We obtain the group delay as T GD = lim ω!, φ ω = 2 + b, a

4 Single-Pole Analysis If we approximate the systemtransfer function up to the first moment (or coefficient of s), H(s) +sb. Then, the output response under infinite ramp is 3 U V out (s)= s 2 = + sb s 2, b b s + (s + =b ) with corresponding time-domain response u V h i out (t) =,b T +t + b e,t b The time-domain response for a finite ramp is therefore (4) 4.2 Threshold Delay Models Condition for Computing Threshold Delay Using Finite or Infinite amp esponse. The ramp input delay at any threshold voltage can be computed using the infinite ramp response in Equation (4) if the ramp delay is less than the rise time, or using the finite ramp response in Equation (5) if the ramp delay is greater than. For example, the delay at threshold Th in Figure 3 is computed using the infinite ramp response, and the delay at threshold Th2 is computed using the finite ramp response. To determine when the infinite ramp response should be used, we write the threshold voltage corresponding to the rise-time in terms of interconnect and rise time parameters: Voltage v out (t) = u out (t), u out (t, ) = + b e,t b, b e,(t, ) b (5) Th2 Note that as t!, v out (t) tends to a final value of as expected. [6] used a similar single-pole analysis to compute delay and transition times solving the above response equations by applying Newton-aphson iteration. 4. Analytical Delay Model It turns out that using the analytical ramp delay computed using the definition in Section 3 and the output responsegiven in Equations (4) and (5) leads to the same result: Z T T Z AD = tu out V (t)dt + tv out V (t)dt = 2 + b Threshold Voltage Corresponding To Analytical amp Delay. Section 3 gave two different methods for computing an analytical ramp input delay from the output response. The threshold voltage corresponding to this analytical delay is not known, and must be computed by substituting T AD for time in either the infinite or the finite ramp responses. Computing the threshold voltage for the infinite ramp response in Equation (4) for b T 2,weget u out (t = T V AD )= 2b + e,(+ 2b = ) : 2 In the limit as 2b! the threshold voltage reduces to u out (t = T AD )= 2. Hence, for large rise-times or small first moment of the transfer function the analytical delay T AD correspondsto 5% threshold voltage. When b T 2, using the finite ramp response in Equation (5) gives v out (t = T AD )= 2b + (e, 2b = 2b, e = ) : 2e In the limit as 2b! the threshold voltage reduces to v out (t = T AD )= (, =e) =:632. Hence, for small rise-times or large first moment of the transfer function the analytical delay T AD corresponds to 63:2% threshold voltage. We see that for any choice of and b the threshold voltage corresponding to the analytical delay T AD will be between 5% and 63:2%. 3 In the transform and time domains, we respectively use U(x;s) and u(x;t) to indicate the response for infinite ramp input, and V(x;s) and v(x;t) to indicate the response for finite ramp input. Th Figure 3: amp input delay at various threshold voltages. Time v T =, b (, e, b = ) (6) Here, v T is the threshold voltage at which the delay through the interconnect is equal to.letv th be the threshold voltage of interest for the finite ramp response, expressed as a fraction of the steady state voltage.ifv th v T, delay is calculated using Equation (4), and if v th > v T, delay is calculated using Equation (5). v th..95.9.85.8.75.7.65.6.55.5.45.4.35.3.25.2.5..5.. 2. 4. 6. 8.. b / T Figure 4: Variation of threshold voltage at delay equal to rise-time with respect to the factor b. Observe that Equation (6) can be rearranged to obtain a condition on b for any given threshold voltage v th : the condition for delay calculation using infinite ramp response is b (, e, b = ) (, v T th ) and the condition for delay calculation using finite ramp response is b (, e, b = ) (, vth )

Figure 4 shows the variation of v T with respect to the factor b. At b = the threshold voltage v T is :368, i.e., 36:8%. Since most sub-micron interconnect networks have small rise-times and large propagation delays, the delays at threshold voltages of interest (5% or 9%) will likely be computed by considering the finite ramp response as developed in Equation (9) below. 4 Threshold Delay Using Infinite amp esponse. Model. For the infinite ramp response of Equation (4), the threshold delay is,d b D + b e = u th + b where u th is the threshold voltage of interest for the infinite ramp response. We can solve such a recursive equation in less than iterations of simple back-substitution (with T AD as the starting value) for all the interconnect configurations we considered. To obtain a closed-form delay formula, we approximate D in the exponential term with some f (T AD ), which yields D = u th + b (, e, f(t AD ) b ) : (7) Here, f (T AD ) dependson the threshold voltage and T AD. 5 The above delay estimate can be improved by expressing D as u th +τ D,since the threshold delay for the infinite ramp responsed is greater than the threshold delay for the infinite ramp input u th. Making this change in delay variable in Equation (4), we get,b + τ D + b e, u th +τ D b = where the factor F = b (e b =, ) can vary between and. With such a large variation in F, it is very difficult to fit the threshold delay D2 against the corresponding SPICE delay. Model 3. Since the threshold delay computed from the finite ramp response is greater than, an alternative formula for the threshold delay can be obtained by expressing D3 as D3 = + τ D3. Substituting into Equation (5) yields v th = T + b e, b,τ D3 e b, b e,τ D3 b : Therefore, the delay is F2 D3 = + b ln () (, v th ) The factor F 2 = b (, e, b = ) varies between and : asshownin Figure 5. For b = this factor is F 2 = :632. For b > we can find a good approximation for F 2 by fitting against SPICE-computed delays, since the variation in F 2 values is very small. However, for the range of interconnect configurations studied both Model 2 and Model 3 gave essentially identical results and hence Section 7 reports results from Model 2 only. F 2 x 95. 85. 75. -3 Expanding e, τ D b terms yields as a Taylor series and considering only the first three 65. 55. 45. τ 2 D + 2b (e u th b, )τ D, 2b 2 (e u th b, ) = Solving for τ D in the above equation, the threshold delay can be expressed as D = u th + b q!, e u th b + e 2u th b, Using this D value for f (T AD ) in the exponentialterm of the Equation (7), we obtain delay values that are very close to the values obtained by solving the equation through iteration. Threshold Delay Using Finite amp esponse. Model 2. For the finite ramp response of Equation (5), v,d2,(d2, ) b th = T + b e b, b e : Collecting the threshold delay D2 terms, we obtain D2 = b ln @ b (e (, v th ) b =, ) A = b ln F (, v th ) (8) (9) 4 At 5% threshold, the condition for delay calculation using infinite ramp response is b T :625, with delay calculated using finite ramp response otherwise. Similarly, at 9% threshold, the condition for delay calculation using infinite ramp response is b T :. 5 In [9] the function f(t AD) is approximatedby f(t AD)=T AD ln(,u ), which is threshold delay for the system with analytical delay as the time constant. The delay estimates using th this approximation are reasonably close to SPICE-computed delays. 35. 25. 5. 5.. b /. 2. 4. 6. 8.. Figure 5: Variation of factor F 2 = b (, e, b = ) with respect to b. 5 Two-PoleAnalysis The two-pole methodology for interconnect response computation under step input has been discussed in [4, 7, 2]. For interconnect trees (or lines) the transfer function has a special form in which the numerator polynomial is a constant, i.e., approximating to s 2 term yields H(s) +sb +s 2 b 2. For the case of resistive source ( S ) and capacitive load (C L ) impedances, the transfer function coefficients are given by [8] b = S C + S C C L + 2 + C L b SC 2 SCC L 2 = + + (C)2 6 2 24 + 2 CC L LC + 6 2 + LC L () For this form of the transfer function, the output response under infinite ramp input is U out (s) = s 2 + sb + s 2 b 2 V,b = s + s 2, + b s 2 s, s 2 s, s + + b s s, s 2 s, s 2

and the corresponding time-domain response is u V out (t) =,b T +t + + b s 2 e s + b t s + e s 2t U(t) (2) s 2, s s, s 2 where U(t) is the unit step function. The time-domain response for a finite ramp is v out (t) = u out (t), u out (t, ) " = T ( + + b s 2 )(e st, e s (t,) ) (s 2, s ) # ( + + b s )(e s2t, e s 2(t,) ) U(t) (3) (s, s 2 ) Note that the first and second moments of the transfer function can be obtained from the coefficients b and b 2, i.e., M = b and M 2 = b 2,b 2. We use the coefficient notation b ;b 2 and the moment notation M ;M 2 interchangeably according to the simplicity of the expression. 5. Threshold Delay Models Depending on the sign of b 2, 4b 2, the poles of the transfer function can be either real or complex. However, for most cases of interest the poles turn out to be real, and we now discuss delay models for the case of real poles. The condition for the poles to be real is (b 2, 4b 2 )= (4M 2,3M 2 ). Since the magnitude js 2j is greater than js j, the second term in the time-domain responsedecreasesrapidly compared to the first term. Hence, the two-pole infinite ramp response can be approximated as u out (t) V,b T +t + + b s 2 e s t (4) s 2, s and the finite ramp response as v out (t) V + + b s 2 s 2, s e s t, e s (t,) : (5) Note that the residue k = +b s 2 s 2,s is a positive quantity, and that the pole s has to be negative in value for the response to converge. Threshold Delay for Infinite amp esponse. Model 4. The delay D4 at threshold voltage u th can be obtained as D4 + + b s 2 s 2, s e s D4 = u th + b Again, we can solve such a recursive equation in less than iterations of simple back-substitution (with T AD as the starting value) for all the interconnect configurationswe considered. Another way to evaluate the above iterative equation is by substituting some f (T AD ) for D4 in the exponential term, which yields D4 = u th + b, + b s 2 s 2, s e s f(t AD) (6) where f (T AD ) depends on the threshold voltage and T AD. For example, for 5% threshold voltage f (T AD )=T AD and for 9% threshold voltage f (T AD )=2:3T AD. We found that the delay values using Equation (6) are close to the values obtained by solving the equation through iteration. Similar to the analysis of Model, a better approximation for the f (T AD ) term can be obtained by expressing D4 as u th + τ D4, since D4 is greater than the threshold delay for the infinite ramp input (u th ). Threshold Delay for Finite amp esponse. Model 5. The delay D5 at threshold voltage v th can be obtained from the response as v th =, + b s 2 s 2, s (e,s, )e s D5 : Since the value of the pole s is negative, the quantity (e,s, ) is positive and the residue +b s 2 s 2,s is also positive. Thus, the delay expression reduces to T D5 = js j ln F3 (7) (, v th ) where the factor F 3 = (+b s 2 )(e js j,) can vary widely. (s 2,s ) Model 6. Since the threshold delay computed from the finite ramp response is greater than, an alternative formula for the threshold delay can be obtained by assuming the form D6 = + τ D6. Substituting into Equation (5) yields v th =, + b s 2 (, e s )e s τ D6 : s 2, s Therefore, the delay is D6 = T + js j ln F4 : (8) (, v th ) where the factor F 4 = (+b s 2 )(,e,js j) (s 2,s ) varies over only a small range. For the range of interconnect configurations studied both Model 5 and Model 6 gave essentially identical results, and hence Section 7 reports results from Model 5 only. [9] gives a detailed discussion of two-pole models for the case of complex poles. 6 Interconnection Trees Finally, we describe how to extend our analytical models to estimate delays in arbitrary interconnect trees. An LC network is called an LC tree if it does not contain a closed path of resistors and inductors, i.e., all resistors and inductors are floating with respectto ground, and all capacitors are connectedto ground. Consider an LC interconnect tree with root (or source) S and set of sinks (or leaves) f;2;:::;ng. The unique path from root S to the sink node i is denoted by p(i) and is referred to as the main path. The edges/nodes not on the main path are referred to as the off-path edges/nodes. We model each edge on the main path of the tree using a lumped LC segment, e.g., an L, T, orπ model. 6 We approximate the off-path subtree rooted at node i with its admittance. At any node i, the admittance Y i is equal to (i) the capacitance of node i (C i ) if there is no subtree at node i, or (ii) to the sum of the capacitance of node i (C i ) and the subtree admittance Y T(i) otherwise. In other words, Y i = sc i if node i has no off-path subtree = sc i +Y T(i) if node i has an off-path subtree With this approximation, the main path reduces to an LY equivalent circuit. Only two admittance moments need to be computed for an exact transfer function moment computation for the main path. The k th 6 Our model is not limited to traditional segment models, and accuracy of our results would likely improve if we use non-uniform segment models [7, 9] designed to perfectly match the low-order moments of the distributed LC line.

L S S V V N+ N N N Y N Figure 6: epresentation of the main path in the tree, where each distributed line is modeled using LC segments. Y i indicates the off-path subtree admittance at node i. coefficient b k of the transfer function for the general LY circuit of Figure 6 can be obtained using the recursive equation given in [7]. The first and second coefficients of the transfer function are b SL N N = S Y ; j + N ; j + b j= j=y N b SL N 2 = S ; j b j=y j N N + S 2; j + N Y ; j b j=y j j= V 2 L Y V L C L N N + N 2; j j=y + L N Y ; j + bn 2 (9) j= The first and second moments are expressed in terms of coefficients as M = b and M 2 = b 2, b 2. For any given source-sink pair the coefficients b and b 2 can be computed in linear time by traversing the main path and using Equation (9) to obtain transfer function coefficients. 7 Experimental esults We evaluate the above models by simulating various LC interconnect lines with different source/loadimpedancesand different input rise times. We consider typical interconnect parameters encountered in single-chip interconnects [8], with the length of the interconnect being 2 µm. The source resistance is varied between to Ω and the load capacitance is varied from :to: pf. We also consider ps and 5 ps rise times for the input ramp. For all our experiments, we compute exact 5% and 9% delays from the response at the load using the SPICE3e simulator. The step input delay is computed using the Elmore delay formula and then multiplying it with the appropriate constant for the given threshold voltage. For example, Elmore delay at 5% threshold voltage is :69b and at 9% threshold voltage is 2:3b. Unlike [5], we find that Elmore delay is not at all close to SPICE-computed 5% threshold delays and, depending on the rise time of the signal and driver resistance, can be either greater or less than SPICE-computed delays (e.g., when the rise time is 5 ps the Elmore delay is for most cases less than the SPICE-computed delays). Also, increased rise time of the input signal causes the Elmore delay to deviate further from SPICE-computed delays (see Tables and 3). For comparison, we also present delay estimates using the analytical ramp delay model T AD. When the rise time of the ramp input is increased from ps to 5 ps the SPICE delays at 5% threshold are increased by approximately 2 ps, which suggests that delay at 5% threshold voltage is proportional to T 2. This effect of the rise time is well modeled in the analytical ramp delay model T AD. To compute ramp input delays using the single-pole methodology we use either the Model or Model 2, depending on the value of the first moment b and the threshold voltage of interest. Similarly, to compute ramp input delays using the two-pole methodology we use either Model 4 or Model 5, again depending on the value of b and the threshold voltage of interest. (If the delay is computed using the infinite ramp response then we mark those delays in the Table with ( ).) Tables and 2 give 5% and 9% delay estimates for ramp input with ps rise time. Tables 3 and 4 give 5% and 9% delay estimates for ramp input with 5 ps rise time. Over our range of test cases, Elmore delay estimates can be as much as % away from the SPICE-computed delays. In contrast, our single-pole delay estimates are within 4% of SPICE delays and the two-pole delay estimates are within 2:3% of SPICE delays. 8 Conclusions Fast delay estimation methods, as opposedto simulation techniques,are needed for incremental performance-driven layout synthesis. Estimation methods based on Elmore delay for a step input, although efficient, cannot accurately estimate the delay for LC interconnect lines. We have obtained new analytical delay models under ramp input, based on the first and secondmoments of LC interconnection lines. The resulting delay estimates are significantly more accurate than Elmore delay estimates. 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para. es. Cap. Delay Delay Pole Pole r;l;c S C T :693b T AD :5 Ω :76 ff. 83 25 87 83* 84* :246 ph 5. 78 26 232 78 78. 32 25 43 32 33. 9 32 96 9 92 5. 29 57 277 29 29. 364 34 53 365 365 5 96 89 49 5 5 522 47 73 522 522 989 939 46 99 99 :5 Ω :76 ff. 87 29 92 87* 88* :246 ph 5. 8 29 237 82 82. 35 255 48 36 37. 96 37 3 96 97 5. 24 62 284 24 25. 369 39 5 37 37 72 8 22 7 73 5 543 493 76 544 545 96 437 2 3 Table : The length of the interconnect line in these experiments is always h = 2 µm. The rise time of the input ramp is ps. For single-pole delay estimates we use Model or 2 and for two-pole estimates we use Model 4 or 5, depending on whether the delay point falls into the infinite ramp response range or the finite ramp response range. The delay estimates refer to 5% threshold voltage. ( )indicates that the delay is computed using the infinite ramp response models. para. es. Cap. Delay Delay Pole Pole r;l;c S C T :693b T AD :5 Ω :76 ff. 287 25 287 287* 287* :246 ph 5. 43 26 432 45* 45*. 529 25 63 53 53. 296 32 296 296 296 5. 445 57 477 445 449. 586 34 73 587 587 38 96 389 38 38 5 736 47 93 736 737 97 939 66 97 98 :5 Ω :76 ff. 29 29 292 292* 292* :246 ph 5. 46 29 437 49* 49*. 532 255 68 533 534. 33 37 33 33 33 5. 45 62 484 455 455. 59 39 7 59 592 45 8 42 46 48 5 757 493 96 758 759 27 96 637 29 22 Table 3: The length of the interconnect line in these experiments is always h = 2 µm. The rise time of the input ramp is 5 ps. The delay estimates refer to 5% threshold voltage. ( ) indicates that the delay is computed using infinite ramp response models. para. es. Cap. Delay Delay Pole Pole r;l;c S C T :693b T AD :5 Ω :76 ff. 4 85 87 45 43 :246 ph 5. 468 48 232 47 469. 882 835 43 886 885. 6 6 96 65 6 5. 572 522 277 574 573. 9 42 53 94 93 366 39 89 372 366 5 62 563 73 65 64 367 38 46 372 37 :5 Ω :76 ff. 5 96 92 56 5 :246 ph 5. 476 43 237 482 479. 889 846 48 898 895. 74 23 3 8 75 5. 583 539 284 59 587. 59 5 7 429 392 22 445 435 5 668 636 76 688 682 328 39 437 3245 3238 Table 2: The length of the interconnect line in these experiments is always h = 2 µm. The rise time of the input ramp is ps. The delay estimates refer to 9% threshold voltage. para. es. Cap. Delay Delay Pole Pole r;l;c S C T :693b T AD :5 Ω :76 ff. 487 85 287 487* 487* :246 ph 5. 72 48 432 722 72. 835 63 3 3. 496 6 296 496 496 5. 84 522 477 86 86. 32 42 73 35 35 633 39 389 638 634 5 826 563 93 83 828 3374 38 66 3379 3378 :5 Ω :76 ff. 49 96 292 492* 492* :246 ph 5. 727 43 437 732 73. 6 846 68 24 22. 53 23 33 54 54 5. 825 539 484 832 833. 322 59 7 332 329 687 392 42 7 692 5 882 636 96 92 896 3425 39 637 3452 3446 Table 4: The length of the interconnect line in these experiments is always h = 2 µm. The rise time of the input ramp is 5 ps. The delay estimates refer to 9% threshold voltage.