Universiy of California College of Engineering Deparmen of Elecrical Engineering and Compuer Science J. M. Rabaey TuTh9:30-11am ee141@eecs EECS 141: FALL 00 MIDTERM 2 For all problems, you can assume he following ransisor parameers (unless oherwise menioned): NMOS: V Tn = 0.4, k n = 115 µa/v 2, V DSAT = 0.6V, λ = 0, γ = 0.4 V 1/2, 2Φ F = -0.6V PMOS: V Tp = -0.4V, k p = -30 µa/v 2, V DSAT = -1V, λ = 0, γ = -0.4 V 1/2, 2Φ F = 0.6V NAME Las Firs GRAD/UNDERGRAD Problem 1: Problem 2: Problem 3: Toal EECS 141: FALL 00 MIDTERM 2 1
PROBLEM 1: Inducance Consider he simple circui of FIG. 1, where he inverer is implemened using complimenary V ou CMOS. Assume ha he V in ransisors in he inverer GND can be modeled as consan linear resisors FIG. 1 Large Capaciance Driver (when on). = 2.5 V. C L = 25 pf.. a. Assuming a 1->0 ransiion a he inpu, deermine he ransisor resisances ha will resul in a 0 o 90% ransiion on he oupu of 5 nsec.. R NMOS = R PMOS = b. Draw he curren drawn from he supply as a funcion of ime during his low-o-high ransiion, and derive he appropriae equaions ha describe ha behavior. Assume ha he inpu signal has a very seep slope, and ha he ransisors swich insananeously. i VDD EECS 141: FALL 00 MIDTERM 2 2
c. The supply rails of he driver ( and GND) are conneced o an exernal off-chip supply wih a value of 2.5 V hrough bonding pads and wires wih a oal inducance of 7.5 nh. Draw he and GND signals as a funcion of ime for he ransiion described above, and annoae some meaningful values. You may assume ha he inroduced inducances do NOT impac he resuls of par b. GND d. Faced wih he emerging problem, rank-order he following remedies in order of poenial effeciveness. 1 being he mos effecive, 4 he leas - Inroduce a capaciance of 25 pf beween and GND. - Increase he 0-90% rise/fall imes a he oupu wih a facor of 2 by reducing he ransisor sizes. - Slow down he inpu signal o a fall ime of 1 nsec. - Use copper insead of aluminum for he supply disribuion nework. EECS 141: FALL 00 MIDTERM 2 3
Problem 2: Logic and Energy Jari Tukkola, a cellular phone designer a Nokia, has come up wih a bus-driving approach ha he believes is going o boh decrease energy consumpion and increase performance. To deliver he high performance, he has sared from a dynamic bus approach as shown in FIG. 2 for bi i. is se a 2.5 V. V bi In i C Li FIG. 2 Dynamic bus archiecure (bi i) a. Draw a iming diagram explaining he operaion of he circui (for he clock and inpu signals shown below). 0 V ini 0 V bi b. The swiching hreshold of he bus fanou inverers INV has been opimized for opimal performance. Explain wha Jari did o achieve his, and why. EECS 141: FALL 00 MIDTERM 2 4
c. For a bus widh of N=4, deermine he average energy dissipaed per clock cycle for he whole bus, assuming ha each inpu bi has a 50% chance of being a zero or a one. You may assume ha he capaciive load of he bus wire C Li = 10 pf dominaes all oher capaciances (including he clock capaciance, and he driver inverer). E ave = d. Jari believes ha he could reduce he average energy dissipaion of he bus if he would modify he circui along he lines of FIG. 3, which replaces he driving inverer by a NEXOR. The logic block F oupus a 1 if he number of 0 bis in he inpu word is larger han he number of 1 bis. For insance, F = 1, if In = 0010; F = 0, if In = 0011 or In = 1110. Explain why his idea of Jari migh no be a bad one afer all. V bi FIG. 3 Modified dynamic bus archiecure (bi i) F In i C Li In 0... In 3 EECS 141: FALL 00 MIDTERM 2 5
e. Design he gae ha implemens he logic block F. Derive firs he required logic funcion, and consequenly implemen he gae in saic complimenary CMOS. Make sure o size he ransisors appropriaely (his is, ake ino accoun he 3 imes lower driving capabiliy of he PMOS devices compared o NMOS, and assume ha he gae has o have a driving capabiliy equal o a minimum-sized NMOS inverer). F= e. Sill assuming ha each inpu bi has a 50% chance of being eiher a zero or a one, deermine again he average energy dissipaed per clock cycle. (WARNING - THIS MIGHT TAKE TIME TO FIGURE OUT. RESERVE THIS FOR DESSERT). E ave = EECS 141: FALL 00 MIDTERM 2 6
PROBLEM 3: Dynamic Logic Consider a convenional 4-sage Domino logic circui as shown in Figure 6 in which all precharge and evaluae devices are clocked using a common clock. For his enire problem, assume ha he pulldown nework is simply a single NMOS device (i.e., each Domino sage consiss of a dynamic inverer followed by a saic inverer). Assume ha each gae has a propagaion delay of T/2 (wih T a ime uni). Hence, he precharge ime of he dynamic gae is T/2, he evaluae ime of he dynamic gae is T/2 and he inverer lowo-high and high-o-low ransiions are each T/2. Assume ha he ransiions are ideal (zero rise/fall imes). IN Nework Ou 1 Nework Ou 2 Nework Ou 3 Nework Ou 4 Domino Sage FIG. 4 Convenional Domino Dynamic Logic. Assume he pulldown nework is a single NMOS device (i.e., each Domino sage consiss of a dynamic inverer followed by a saic inverer) (a) Complee he iming diagram for signals Ou 1, Ou 2, Ou 3 and Ou 4. IN Ou 1 Ou 2 Ou 3 Ou 4 T EECS 141: FALL 00 MIDTERM 2 7
Now consider he following variaion of he circui where he evaluae swich of he laer sages have been removed. IN Nework Ou 1 Nework Ou 2 Nework Ou 3 Nework Ou 4 Domino Gae FIG. 5 Convenional Domino Dynamic Logic wih he evaluae swiches removed in he laer sages. (b) Assume ha he clock is iniially in he precharge sae (=0 wih all nodes seled o he correc precharge saes), and he block eners he evaluae period (=1). Does he removal of he evaluae swiches help or hur he evaluaion. Explain. (c)assume ha he clock is iniially in he evaluae sae (=1), and he block eners he precharge sae ( = 0). Does he removal of he evaluae swiches help or hur he precharge. Explain. EECS 141: FALL 00 MIDTERM 2 8