lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI HEER Lineout Master/Slave Power PG. External Power Jacks Onboard Power LO External V in lock iagram - -Pin QFN, x Package ocument Number SGTL Evaluation Platform ate: Monday, March, Sheet of
Feature Set ision:. JP to setect SYS_MLK. JP to select on-board MI or external MI_IN. JP~JP to setect between external and on-board power supply ) - Initial Release Feature Set ocument Number SGTL Evaluation Platform ate: Monday, March, Sheet of
V is used when connecting an external V, otherwise it is a nopop.uf TRL_LK TRL_T,, TRL_R_S, TRL_MOE HP_R HP_VGN HP_L V U GN HP_R GN HP_VGN V HP_L GN N TRL_MOE TRL_R_S V TRL_LK N TRL_T IS_IN IS_OUT IS_SLK IS_LRLK N SYS_MLK VIO N PFILT N TP IS_IN IS_OUT IS_SLK IS_LRLK SYS_MLK VIO.uF.uF SGTL_QFN TP N VG LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MI MI_IS GN Solder Pad to GN.uF MI_IS MI.uF LINE_OUT_R LINE_OUT_L uf uf uf uf LINE_IN_L LINE_IN_R SGTL ocument Number SGTL Evaluation Platform ate: Tuesday, March, Sheet of
Line-In TP RJ- RX LINE_IN_R LINE_IN_L TP J MI Microphone input with MI_IS derived internally. TP X MI.uF JP HEER X MI MI_IS.uF R.k R R J udio Jack.mm udio Jack nalog Inputs ocument Number SGTL Evaluation Platform ate: Monday, March, Sheet of
Line-Out RJ- RX TP LINE_OUT_R J LINE_OUT_L TP R k pf R k pf Headphone Out J udio Jack R R HP_JK_GROUN R uf R TP TP HP_R Headphone output with population option for PLESS design with virtual ground or output using series P and board ground. Test filters shown on output. Ohm resistors to HP_JK_GROUN can be used to minimize input to output coupling without power applied. R R HP_JK_GROUN R R uf HP_JK_GROUN.uF R.uF R.uF R HP_L HP_VGN Test filters - not populated nalog Outputs ocument Number SGTL Evaluation Platform ate: Tuesday, March, Sheet of
US Jack J US-TYPE- VUS - + GN USM USP US_V L /.uf.uf uf US_V_L R.uF.uF.uF V_US R.uF.K R.K R.K GREEN LE US_V V_US pf U S V SK N IN ORG GN OUT T k R R R pf. uf pf MHz XTL pf FTI_RST# V_US.k R Y R.k EES EESK EET V VOUT USM USP RSTOUT# XTIN XTOUT RESET# EES EESK EET TEST GN V V VIO VIO GN GN GN GN U US US US US US US US US US US US US SI/WU US US US US US US US US US US US US SI/WU PWREN# FT R R k R R R R k R.K R.K V_US VIO FTI_LK FTI_T TRL_T, FTI_S R.K MSTER SLVE TRL_MOE, UF_IR FTI Reset V_US MP FTI_RST# RST GN V U.uF ommunication ocument Number SGTL Evaluation Platform ate: Tuesday, March, Sheet of
igital Header J HEER_X TP TP TP TP TP TP TP TP Jumper settings - I_LK - I_T - IS_OUT - IS_LRLK - IS_SLK - IS_IN - IS_MLK TRL_LK TRL_T, TRL_R_S, IS_OUT IS_LRLK IS_SLK IS_IN IS_MLK P PSI Header J HEER_X P_TX_LRLK P_TX_SLK P_RX_LRLK P_RX_SLK TP TP TP TP TP TP TP TP Jumper settings - P_TX_T IS_IN - P_TX_LRLK - P_TX_SLK - P_TX_MLK IS_MLK - P_RX_T IS_OUT - P_RX_LRLK - P_RX_SLK - P_RX_MLK IS_MLK Master/Slave modes P PSI level must match VIO setting VIO VIO VIO VIO SLVE MSTER VIO VIO.uF.uF R.K.uF P_TX_LRLK P_RX_LRLK IS_LRLK P_RX_LRLK FTI_T TRL_T, IS_LRLK P_TX_LRLK FTI_LK TRL_LK P_TX_SLK P_RX_SLK IS_SLK P_RX_SLK OS_MLK OS_MLK_UF UF_IR IS_SLK P_TX_SLK FTI_S TRL_R_S, U LV U LV U LV IS Signals ocument Number SGTL Evaluation Platform ate: Tuesday, March, Sheet of
EXTERNL POWER: +V.mm Power Jack V_IN J SW F FUSE amp XF RE LE Replace Fuse LE TP R.k uf V Select either External Power by tying Pins and together, or Internal Power by tying Pins and together on JP,,. EXT_POWER_JK V + uf V R LO Regulator for.v V(. -.V) LO Regulator for.v V(. -.V) J POWER_JK VIO TP R + uf V VIO LO Regulator for.v VIO(. -.V) LO Regulator for OS (.V onstant) To use internal regulator, jumper pins,, and do NOT supply power to J V TP V J POWER_JK TP TP R k LUE LE +V + uf V TP TP J POWER_JK JP HEER X V +V U V IN OUT EN R GN J k PUJZ-R.uF.uF +V U V IN OUT EN R GN J k PUJZ-R.uF.uF TP JP HEER X R k R k J POWER_JK +V U VIO +V U V_OS IN OUT IN OUT EN R EN R GN J k GN J k PUJZ-R PUJZ-R.uF.uF.uF.uF TP + uf V R JP HEER X R.k R.k TP TP TP SREW H-N SREW SREW H-N SREW STNOFF K-N STNOFF MH.mmIxmmO MH.mmIxmmO MH.mmIxmmO MH.mmIxmmO H-N SREW H-N SREW K-N STNOFF H-N SREW H-N H-N SREW H-N K-N STNOFF K-N GN Power ocument Number SGTL Evaluation Platform ate: Monday, March, Sheet of
U N V.uF V_OS GNOUT.M R OS_MLK J GN GN ON SM GN GN OS_MLK_UF EXT_MLK Jumpers to select SYS_MLK efault Pin&Pin connected JP HEER X SYS_MLK IS_MLK VIO VIO When TRL_MOE = GN (I), TRL_R can be pulled up or down to set the LS of the I address. When TRL_MOE = VIO (SPI), TRIL_R_S is the SPI chip select. R.K R.K R.K R.K TRL_MOE, TRL_R_S, locks and ddressing ocument Number SGTL Evaluation Platform ate: Tuesday, March, Sheet of