.0UF_BYP_AX.0UF_BYP_AX C C 0FS FS ADCDATA DATA 0S R 0K0 D N D N U DS U0 RST 0MHZ_OSC UA debug port 0 R 0K0 RD- WR- DS- PS- X/Y- DIN/AIN- IR- 0IR- MODC LS0 J R0 K00 dsck dr dsi dso R 0K0 0K0 R UA A/B G A B A B 0 A B A B UB LS0 SCI_RXD SCI_TXD SCI_ TFS TSCK DOUT Y Y Y Y HC S HA0 HA HA H0 H H H H H H H HR/W HACK 0 HRE HEN 0 DSCK/OS DSO DSI/OS0 DR MODA/IRA 0 MODB/IRB MODC/NMI RXD TXD S SC0 SC SC SCK STD SRD RESET XTAL EXTAL PINT 0 PLOCK P CKP CKOUT UA DSP_00 D0 D D D 0 D D D D D D 00 D0 0 D 0 D 0 D 0 D 0 D 0 D 0 D D D D0 D D D 0 A0 A A A A A A A A A A0 A A 0 A A A RD WR DS PS X/Y BG BR WT BN BS TIO NC 0 NC NC DS- BN- L/R- L/R- ERF 0L/R- L/R- BN- DATA[00:] DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA0 DATA DATA DATA ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD ADD ADD ADD ADD R0 0K0 ADD ADD[00:] DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD0 ADD ADD ADD ADD ADD ADD0 ADD0 ADD0 0IR- PS- REG 0 A0 A A A A A A A A A A0 A A A A A OE/VPP 0 CE A B C GA GB G UA D0 D D D D D D D C UA Y0 Y Y Y Y Y Y Y HC OE D0 D D D D D D D 0 UA HC 0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 EEPROM SCI_ SCI_TXD 0 REG DIS_LD L/RSET UA CS DO SK DI NC NC NMC0N ARG // SCI_RXD LTR KEN- KEN- MCK/ DIN/AIN- CMODE 0PD EEPROM IR- REVISION RECORD REVISIONS DONE OR ECO NUMBER: DATE: CHANGED GA- OF U FROM X/Y- TO BN-.// C WAS BACKWARDS MODC DATA[00:] DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA0 DATA DATA DATA TH AVE WEST LYNNWOOD, WA 0 0 : DSP 00 OF 0 0 0 0K_SIP R 0K_SIP R 0K_SIP R
LYNNWOOD, WA 0 TH AVE WEST OF 0 : Display 00 ARG // D D D D D D D D0 D D D D D D D D D D D D D LED_CYL_RED D D D D D D D D D D D D D0 D D D D D D D D LED_CYL_RED D D D D D D D LED_CYL_RED SW SW SW SW D N D N D N D N DIG0 DIG DIG DIG 0 DIG DIG DIG DIG SEGA SEGB 0 SEGC SEGD SEGE SEGF SEGG SEGDP DIN LOAD ISET V DOUT U MAX R K C.uF C.0UF_CER_AX VIN U 0CT C.uF/0V D0 N D N J- J- J- J- J- J- J- J- J- J- J- J- J- J- J- J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP J- SIPP D D D0 D D D0 D D0 D C / (axial) LEDROW[0:] LEDROW0 LEDROW LEDROW LEDROW LEDROW LEDROW LEDROW LEDROW LEDCOL[0:] LEDCOL0 LEDCOL LEDCOL LEDCOL LEDCOL LEDCOL LEDCOL PB[0:] PB0 PB PB PB LEDCOL[0:] LEDROW[0:] LEDCOL0 LEDCOL LEDCOL LEDCOL LEDCOL LEDCOL LEDCOL LEDCOL LEDROW DISD DIS DISLD PB0 PB PB PB DISD DIS DISLD DATA[00:] DATA0 DATA0 DATA0 SCI_TXD SCI_ DIS_LD LEDCOL 0V LEDROW0 LEDROW LEDROW LEDROW LEDROW LEDROW LEDROW
U VA A -V C.uF C.uF C 0UF/t C 0UF/t VIN 0CT VIN 0CT U VA- A -VA D0 C0 N./t A A N D0./t A C A C.uF A C.uF A C.uF A C.uF C.uF A VA-VA VREF R. OHM C C C.uF.uF.uF VL VD SDATA C.uF A A ADCDATA C.uF C.uF C.uF C.uF VSS U.MHZ C.uF U R OUT.MHZ.MHZ MCK.MHZ S0 S U0A OE I0 I Y I I Y 0 OE I0 I I I ACT MCK/ UD ACT00 UA S D R HCT AINL AINL- AINR AINR- CMODE 0PD C 00/ UA ACT00 UB A ACT00 C 00/ 0 A UC ACT00 A.R.G // MCK C.uF VREF- TSTO TSTO AINL AINL- CMODE 0 DPD APD ACAL DCAL L A U CS0 A TH AVE WEST LYNNWOOD, WA 0 0 : Clock and A/D 00 R IA OD AINR AINR- FSYNC L/R- S SMODE ID D 0 MCK KEN- KEN- R 0FS 0L/R- 0S MASTER MODE OF
C.00UF_CER_AX Right Channel J /" TRS JACK J XLR-FEMALE C 00PF_CER_AX CH C L IN OUT L IN OUT 00PF_CER_AX L IN OUT R 0K0 R 00K0 R 00K0 R 0K0 R 0K0 C 00PF_CER_AX R A C 00PF_CER_AX R0A 0 SWD R K R K R0B 0KB DUAL SWB R K - - UA OPP C PF_CER_AX C PF_CER_AX - R 0K0 R0 0K0 UB OPP UA OPP R OHM VA- R OHM R OHM D0 BAT- D0 BAT- D00 BAT- D0 BAT- VA C.00 AINR AINR- AINL C.00UF_CER_AX Left Channel J /" TRS JACK J XLR-FEMALE C 00PF_CER_AX CH Note: CH attaches directly to chassis through a standoff. C L IN OUT L IN OUT L IN OUT 00PF_CER_AX R 00K0 C 00PF_CER_AX R 00K0 R 0K0 R A C 00PF_CER_AX RA SWC R K R K RB 0KB DUAL SWA R K A.R.G R 0K0 C PF_CER_AX C0 PF_CER_AX R 0K0 UB - OPP // VA- R0 OHM D0 BAT- D0 BAT- D0 BAT- D0 BAT- TH AVE WEST LYNNWOOD, WA 0 0 Analog Inputs C0.00 VA AINL- 00 OF
S/PDIF INPUT SHELL J PIN RCA_JACK D0 N SWB DATA0 C.uF R C.u* AES INPUT J C.uF CH C.uF XLR-FEMALE C.0uF ADD0 R K00 SDATA FSYNC SCK A/FCK MCK ERF VD VA D A 0 FILTER T 00 U CS ERF MCK S FS DATA SWA R R DATA[00:] WR- 0 0IR- DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 ADD[00:] DATA0 ADD0 ADD0 ADD0 WR- IR- DATA[00:] ADD[00:] ADD0 ADD0 ADD0 ADD0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DOUT TSCK TFS MCK TX- RX 0 RX- D0 D D D D D D D A0 A A A R/W CS INT U SDATA SCK FSYNC MCK D0 D D D D D D D A0 A 0 A A A R/W CS INT CS0 TX 0 VDD VSS R D N R OHM R OHM C.uF SWB AES/SPDIF SELECT SWA T 00 DATA0 AES/EBU OUT XLR-MALE J CH J PIN SHELL RCA_JACK S/PDIF OUT L/RSET FS 0 UB S D R L/R- HCT TH AVE WEST LYNNWOOD, WA 0 ARG // 0 : Digital Inputs and Outputs 00 OF
SWB none U 0V MAINS (IEC) J FUSE_CLIP_INTL J0. amp (V).amp Slo-Blo (0V) SWA none R C.UF/0V C0 EMI_FILT_AC SW VAC 0 VAC 00 T 0 000 C 00/0 C EMI_FILT_AC C.0UF_BYP_AX U C 000/ V 000 C 000/ -V A.R.G. // TH AVE WEST LYNNWOOD, WA 0 00 0 : Power Supply OF
V C.u VIN U M C.u C u R D0 N00 R 0V L0 BEAD HS_0 U IN OUT LM0CT-0 C.u C 0/ C.u Z.V R C.u C.u A -V C.u OPP C.u UC C.u C.u -V C.u A VIN U M UC OPP C0.u UG LS0 C u D N00 C.u R H -V UC HCT UE ACT00 C.u C.u UB HC UB HC C.u C.u UB UB C 0 0 HC C.u C.u UB NMC0N C.u C0.u C.u C0.u U0B ACT C.u C.u C0.u 0 0 H S C N N N D 0 D D CL P H H H H S S C N N 0 N N N D D D 0 D 0 D D CL P UB UC UE DSP_00 LS0 UD LS0 0 LS0 UF LS0 A.R.G // TH AVE WEST LYNNWOOD, WA 0 0 Power Supply 000 OF