Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies Hans Tuinhout, The Netherlands
motivation: from deep submicron digital ULSI parametric spread and fluctuation specs give rise to an everlasting battle between process technology development and system designers ULSI memories (sense amplifiers & cell stability) memories critical path (timing variations) small feature sizes & low supply voltages increase the impact of variation of transistor properties on chip or system performance
...to mixed signal SoC integration (embedded analogue blocks) many ANALOGUE circuit applications are based on pairs or multiples of supposedly identical components current mirrors D/A & A/D converters, PLLs bandgap voltage references switched capacitor circuits / filtering amplifiers, opamps comparators differential pairs small feature sizes & low supply voltages increase the impact of variation of transistor properties on chip or system performance
theme parametric mismatch fluctuations hamper the performance and yield of deep-submicron CMOS ULSI systems and it will most likely get worse in the future...
outline Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies introduction (spread and fluctuation) the analogue angle ( matching ) the digital angle ( fluctuations ) threshold voltage mismatch fluctuations a historical perspective there is more than dopant fluctuations it pays to work on fluctuations an ITRS-based outlook there s more than threshold voltage mismatch other fluctuating quantities the ultimate challenge: back to analogue conclusions
spread G S D Physical variations: - Critical Dimensions CD - layer thickness t - furnace Temperatures T - uniformity of chemicals C electrical variations incl. wafer-to-wafer & lot-to-lot 100-300 mm currents: ~ 5-30 % voltages: 10-100 mv
mismatch fluctuation matched pair 10-100 µm e.g. memory cell, bandgap, opamp, etc. electrical differences: ~ 0.1-2% 200 µv - 2 mv for large devices - 100 mv for small devices spacing small enough to have negligible spatial parametric variation differences caused by STOCHASTIC (random) effects related to microscopic device architecture fluctuations
example: threshold voltage is affected by dopant fluctuations S gate D n+ n+ p-type substrate The threshold voltage determined by - oxide thickness - dopant concentration of the depleted (substrate) channel region The number of (fixed) charges in the depletion layer has a random component due to the random nature of the ion implantation and diffusion processes.
example 90 nm CMOS node transistor W L Y depl L 40 nm (effective) W 60 nm (effective) Y depl 25 nm N a 2 x 10 18 /cm 3 n act ~ 1300 atoms Poisson statistics 1 σ fluctuation n act ~ 40 atoms
Poisson statistics requirements - random matching is caused by many single events of a mismatch generating process (ion implantation, diffusion, grains). - the effect of a single event on a parameter is so small that the contributions of events can be summed. - the effects have a correlation distance that is much smaller than the active area of the components. Occurrences of these events are mutually independent. (Poisson statistics applicable) σ P A = P W L σ VT = A VT (WxL)
mismatch fluctuation characterisation Determination of the statistical distribution of electrical differences between closely spaced identical components Count µ σ 30 20 10 0-4.0-2.0 0.0 2.0 4.0 P (%) σ standard deviation: mismatch fluctuation µ ( 0) median or average: offset or systematic mismatch
physical mismatch causes stochastic effects systematic & environmental effects -ion implantation - dopant diffusion - dopant clustering - interface states - fixed charges - edge roughness - poly-si grain effects - dimensional errors - photo-mask size differences - lens aberrations - photo-resist thickness variations - topography related - mechanical strain variation - strained CVD layers - circuit topography, STI, LOCOS -metallisation
an example (0.18 µm n-channels) 8 σ VT 6 (mv) 10/10 10/1 10/0.25 0.2/4 2/0.18 2/10 0.4/10 2/1 0.4/1 A VT 3.4 mvµm 4 2 N-channel MOSFETs T ox = 3.3 nm 1/ WxL (1/µm) Observations: - 1/square-root area law seems applicable - large device match better 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 σ VT = A VT (WxL) - short channel transistors with halo-implants (higher dope) and narrow channel devices (STI edge channel) may give enhanced mismatch
another example (figure 2) V T mismatch fluctuation for 0.12 µm p-mosfets? 100. 10.0 σ VT 1.00 (mv) 0.10 3 mvµm 0.01 0.01 1.00 10.0 100. Observations: WL (µm 2 ) - σ VT ranges from 300 µv for W/L = 10/10 to 20 mv for W/L = 0.15/0.13-1/square-root area law seems applicable over 4 decades geometry range - well behaved technology from a mismatch fluctuation point of view! A VT but look where minimum transistors in the next generation technology will be: (effective area 0.0024 um 2 )
90 nm CMOS node threshold voltage fluctuation W L Y depl L 40 nm (effective) W 60 nm (effective) Y depl 25 nm N a 2 x 10 18 /cm 3 n act ~ 1300 atoms Poisson statistics 1 σ fluctuation n act ~ 40 atoms A V T 2.1 mvµm σ VT 43 mv!!!
in a multi Mb (embedded) SRAM a V T mismatch fluctuation standard deviation of over 40 mv means that there will be cells for which the threshold voltage difference between two IDENTICAL transistors in ONE CELL is more than 250 mv Note that: - this is independent of (worst case) process spread! - these occurences are randomly distributed (defect related yield signature) - this is for a well constructed microscopic process architecture (there s more than dopant fluctuations alone...)
a historical perspective of V T mismatch fluctuation A VT (mvµm) 30 20 10 Process generation 0.6 0.8 1.0 1.2 2.0 2.5 10 20 30 40 50 T ox (nm) PMOSTs Philips data NMOSTs Philips data a heuristic figure of merit for MOSFET V T mismatch fluctuation performance (benchmark) 1 mvµm per nm gate oxide thickness seems to follow the theory...
dopant fluctuation theory Stochastic Dopant Fluctuation Theory: 4 σ VT = C T ox N a (WxL) Refined by F. Widdershoven [Stolk et al.] : σ VT 2 4 (4q 3 ε Si ϕ B ) ( ) [ 3 k B T q 1 (4qε Si ϕ B N A ) 4 N A T OX + ] ε OX (W L) theoretical (1-D) limit for conventional technology (poly-gate, bulk CMOS)
the analogue angle on V T mismatch fluctuation scaling S gate D S gate D n+ n+ n+ n+ p-type substrate p-type substrate σ VT T ox 2 4 (4q 3 ε Si ϕ B ) ( ) [ 3 k B T q 1 (4qε Si ϕ B N A ) 4 N A T OX + ] ε OX (W L) 4 hence: V T mismatch fluctuation improves N for more advanced technologies... gives more flexibility to trade-off speed / power / accuracy
mismatch fluctuation factors for some technologies 1 um 0.18 0.25 0.5 1.0 20 0.35 0.7 A VT 15 measured on large n-mosts (mvµm) 10 5 calculated A VT using effective N A (body effect) and known T ox 0 0 5 10 15 20 T ox (nm) conclusions - dopant fluctuations alone cannot explain the observed A VT s - the 1 mvµm/nm benchmark cannot be maintained - this is bad for analogue but disastrous for digital!!!
the digital perspective: fluctuations V T fluctuations are due to the same mechanisms at this distance scale, 1-20 mm Transistor variations: ~ 1-5 % (2-100 mv) spatial parametric non-uniformities can usually be neglected as V T mismatch fluctuations σ V T σ VT / 2
the digital perspective σ VT 2 4 (4q 3 ε Si ϕ B ) ( ) [ 3 k B T q 1 (4qε Si ϕ B N A ) 4 N A T OX + ] ε OX (W L) T ox 4 N (W L) while control of process spread improves! V T fluctuations dominate over spread for small devices in advanced technologies dominated by dopant fluctuations [Mizuno et al.] S gate D S gate D n+ n+ n+ n+ p-type substrate p-type substrate
same graph... 0.18 0.25 0.5 1.0 20 0.35 0.7 A VT 15 (mvµm) 10 5 0 0 5 10 15 20 (nm) T ox let s look at this from a digital perspective:
threshold voltage mismatch for 1.5 L min2 device pairs historic target level σ VT = 40 (mv) 35 30 25 20 15 10 A VT (1.5L min2 ) oops... pmost nmost V T fluctuations run away??? (SRAM yield problems!!!) 5 1.0 0.8 0.5.35.25.18 Technology Node (µm) V T mismatch fluctuations due to dopant fluctuations become larger!
work on mismatch fluctuation improvement different flavours of the same process (mainstream CMOS vs. 2 BiCMOS versions) no improvement but within benchmark... 20 A VT 15 10 (mv µm) 5 0.18 initial results 0.25 0.5 1.0 0.35 0.7 0 0 5 10 T ox (nm) process improvements (see later this session) 15 20
other factors may affect V T mismatch fluctuation parametric mismatch fluctuations are due to stochastic microscopic device property fluctuations - interface states - (gate oxide roughness) - oxide charges - channel length roughness -... hence their contributions to the variance (σ 2 ) add quadratically A 2 V T = A 2 Na + A2 IT + A2 Tox + A2 Qox + A2 other microscopic fluctuations in the transistor architecture can also prove devastating for the matching...
gate morphology can affect V T mismatch fluctuation major improvements were achieved by controling the fluctuation contributions caused by the poly silicon gate local gate depletion local gate penetration of implantations
yield impact on SRAMs Static Noise Margin SRAM cell [V] I II Vin I Vout II SNM Static Noise Margin: size of eye defines robustness Vin I Vout II [V] SNM: µ 3σ 80 (mv) 60 40 20 0-20 0.18 µm process 0.1 µm process good control of A V T becomes 0 2 4 6 8 10 A (mvµm) VT a yield issue!!!
warning: there is more than threshold voltage fluctuation V T mismatch fluctuation is not the only fluctuating electrical parameter in a MOSFET - current factor (β or K ) - body effect (substrate effect on V T ) - subthreshold (STI side-channels) - moderate inversion??
the ultimate (analogue) challenge mixed signal system solutions lost time to market can often benefit from availability of extremely small mismatch components (<< 0.1 %) when searching below 1 % mismatch, many subtle technological and layout artefacts can severely degrade the equality of supposedly identical components environmental effects, local mechanical strain, mask making artefacts etc. yield loss
a grim outlook... (mv) 160 120 80 σ VT = A VT (1.5L min2 ) 40 0 ITRS node (nm) 130 90 70 45 32 22 2002 2004 2006 2008 2010 2012 2014 2016 year - conventional bulk CMOS architecture with effective dimensions and small feature sizes dopant & low levels supply as voltages given in the 2001 ITRS - multiplied (widdershoven) increase dopant the impact fluctuation of variation A VT of with transistor factor 2 - higher dopants for short channel devices (halo s) properties on chip or system performance - possible additional disturbance factor (high k dielectrics...) unconventional solutions required, but beware of Murphy...
conclusions Parametric mismatch fluctuations evolved from a typical analogue building block design issue to a severe performance and yield limiter for digital and mixed signal systems. It pays to work on improving mismatch fluctuations: - mismatch fluctuation evaluation provides better insights into the microscopic device architecture - improving mismatch fluctuation is often possible by reducing non dopant related fluctuation causes - dopant fluctuations form a fundamental limit for conventional CMOS process architectures - unconventional CMOS process architecture solutions are required, but these will probably come with their own inherent fluctuation contributions