HN27C1024HG/HCC Series

Similar documents
HN27C4096G/CC Series. Ordering Information. Features word 16-bit CMOS UV Erasable and Programmable ROM

HN27C4096AHG/AHCC Series

HN58C256 Series word 8-bit Electrically Erasable and Programmable CMOS ROM

HN58C65 Series word 8-bit Electrically Erasable and Programmable CMOS ROM

HN58C66 Series word 8-bit CMOS Electrically Erasable and Programmable CMOS ROM. ADE F (Z) Rev. 6.0 Apr. 12, Description.

HM6264A Series. Features. Ordering Information word 8-bit High Speed CMOS Static RAM

DS K x 8 Static RAM FEATURES PIN ASSIGNMENT PIN DESCRIPTION

High Speed Super Low Power SRAM


32K x 8 EEPROM - 5 Volt, Byte Alterable

IS61C K x 16 HIGH-SPEED CMOS STATIC RAM

5 V 64K X 16 CMOS SRAM

LH5P832. CMOS 256K (32K 8) Pseudo-Static RAM

DS1225Y. 64K Nonvolatile SRAM FEATURES PIN ASSIGNMENT

3.3 V 256 K 16 CMOS SRAM

IS61LV K x 16 LOW VOLTAGE CMOS STATIC RAM

LH5P8128. CMOS 1M (128K 8) Pseudo-Static RAM PIN CONNECTIONS

HB56A1636B/SB-6B/7B/8B

DECODER I/O DATA CIRCUIT CONTROL CIRCUIT

5.0 V 256 K 16 CMOS SRAM

3.3 V 64K X 16 CMOS SRAM

P4C164 ULTRA HIGH SPEED 8K X 8 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS, 6T Cell. Common Data I/O

PYA28C16 2K X 8 EEPROM FEATURES PIN CONFIGURATIONS DESCRIPTION FUNCTIONAL BLOCK DIAGRAM. Access Times of 150, 200, 250 and 350ns

256K X 16 BIT LOW POWER CMOS SRAM

SRAM & FLASH Mixed Module

2 Megabit (256K x 8) SuperFlash MTP SST27SF020, SST27VF020

HN58V65A Series HN58V66A Series

SRM2264L10/12 CMOS 64K-BIT STATIC RAM. Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous DESCRIPTION

HM514400B/BL Series HM514400C/CL Series

16-Mbit (1M x 16) Pseudo Static RAM

SRAM AS5LC512K8. 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT. PIN ASSIGNMENT (Top View)

8-Mbit (512K x 16) Pseudo Static RAM

DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT

April 2004 AS7C3256A

NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset

DQ0 DQ1 DQ2 DQ3 NC WE# RAS# A0 A1 A2 A3 A4 A5. x = speed

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

M74HCT138TTR 3 TO 8 LINE DECODER (INVERTING)

NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output

1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet

Revision No History Draft Date Remark

. HIGH SPEED .LOW POWER DISSIPATION .OUTPUT DRIVE CAPABILITY M54HCT138 M74HCT138 3 TO 8 LINE DECODER (INVERTING) t PD = 16 ns (TYP.

LH NMOS 256K (256K 1) Dynamic RAM DESCRIPTION

74VHCT138ATTR 3 TO 8 LINE DECODER (INVERTING)

Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters

White Electronic Designs

DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5

IBM B IBM P 8M x 8 12/11 EDO DRAM

1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS

MM74C912 6-Digit BCD Display Controller/Driver

1-Mbit (128K x 8) Static RAM

16-Mbit (1M x 16) Static RAM

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs

Synchronous 4 Bit Counters; Binary, Direct Reset

Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output. Rev. No. History Issue Date Remark

About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd.

74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Logic Diagram. Connection Diagram. Function Table (Each Latch)

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

NJU BIT PARALLEL TO SERIAL CONVERTER PRELIMINARY PACKAGE OUTLINE GENERAL DESCRIPTION PIN CONFIGURATION FEATURES BLOCK DIAGRAM

4-Mbit (256K x 16) Static RAM

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

DS Tap Silicon Delay Line FEATURES PIN ASSIGNMENT. PIN DESCRIPTION TAP 1 TAP 5 TAP Output Number +5 Volts

2-Mbit (128K x 16)Static RAM

R1RW0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. REJ03C Z Rev Mar

CMOS HIGHSPEED 8-BIT A/D CONVERTER WITH TRACK AND HOLD. Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:

High Speed MOSFET Drivers

MR48V256A GENERAL DESCRIPTION FEATURES PRODUCT FAMILY. PEDR48V256A-06 Issue Date: Oct. 17, 2011

UNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC

NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder

SRAM AS5C512K8. 512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS FEATURES

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

256K x 16 Static RAM CY7C1041BN. Features. Functional Description

512K x 32 Static RAM CY7C1062AV33. Features. Functional Description. Logic Block Diagram. Selection Guide

IBM IBM M IBM B IBM P 4M x 4 12/10 DRAM

Obsolete Product(s) - Obsolete Product(s)

2M x 32 Bit 5V FPM SIMM. Fast Page Mode (FPM) DRAM SIMM S51T04JD Pin 2Mx32 FPM SIMM Unbuffered, 1k Refresh, 5V. General Description.

64K x 18 Synchronous Burst RAM Pipelined Output

I/O 8 I/O 15 A13 A 14 BHE WE CE OE BLE

PO54G74A, PO74G74A. Pin Configuration. Logic Block Diagram. Pin Description. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: 1D 2

5V 1M 16 CMOS DRAM (fast-page mode) DQ16 DQ15 DQ14 DQ13 RAS DQ12 DQ11 DQ10 DQ9 OE WE UCAS LCAS LCAS UCAS OE A9 A8 A7 A6 A5 A4

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

PALCE22V10 and PALCE22V10Z Families

TC74VHCT573AF,TC74VHCT573AFW,TC74VHCT573AFT

8-bit binary counter with output register; 3-state

CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders

TC4013BP,TC4013BF,TC4013BFN

74LS165 8-Bit Parallel In/Serial Output Shift Registers

DRAM MT4LC4M16R6, MT4LC4M16N3. 4 MEG x 16 EDO DRAM

LED Display Product Data Sheet LTM-0215F Spec No.: DS Effective Date: 11/12/2003 LITE-ON DCC RELEASE

SGM7SZ00 Small Logic Two-Input NAND Gate

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC148 M74HC148 8 TO 3 LINE PRIORITY ENCODER. tpd = 15 ns (TYP.

NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register

UNISONIC TECHNOLOGIES CO., LTD U74HC14

9A HIGH-SPEED MOSFET DRIVERS

TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK

Transcription:

65536-word 16-bit CMOS UV Erasable and Programmable ROM Description The Hitachi HN27C1024H series is a 1-Mbit (64-kword 16-bit) ultraviolet erasable and electrically programmable ROM. Fabricated on new advanced fine process technique, the HN27C1024H makes high speed access time 85/100 ns (max) possible. (HN27C1024H is the fastest 1-Mbit EPROM.) Therefore, it is suitable for 16-bit microcomputer systems using high speed microcomputer such as the 8086 and 68000. The HN27C1024H offers high speed programming using page programming mode. It has the package variation of cerdip 40-pin and JLCC 44-pin. Features Fast high-reliability programming mode and fast high-reliability page programming mode Programming voltage: 12.5 V DC Fast High-reliability page programming 14 sec (typ) High speed inputs and outputs TTL compatible during both read and program modes Low power dissipation: 60 mw/mhz (typ) Device identifier mode: Manufacturer code and device code JEDEC standard Ordering Information Type No. Access Time Package HN27C1024HG-85 HN27C1024HG-10 HN27C1024HG-12 HN27C1024HG-15 HN27C1024HCC-85 HN27C1024HCC-10 HN27C1024HCC-12 HN27C1024HCC-15 85 ns 100 ns 120 ns 150 ns 85 ns 100 ns 120 ns 150 ns 600-mil 40-pincerdip (DG-40A) 44-pin J-bend leaded chip carrier (CC-44)

Pin Arrangement HN27C1024HG Series HN27C1024HCC Series V PP CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 V SS I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V CC PGM NC A15 A14 A13 A12 A11 A10 A9 V SS A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O12 I/O11 I/O10 I/O9 I/O8 V SS NC I/O7 I/O6 I/O5 I/O4 7 8 9 10 11 12 13 14 15 16 17 I/O13 I/O14 I/O15 CE V PP NC V CC PGM NC A15 A14 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 I/O3 I/O2 I/O1 I/O0 OE NC A0 A1 A2 A3 A4 (Top view) 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 V SS NC A8 A7 A6 A5 (Top view) Pin Description Pin Name A0 A15 I/O0 I/O15 CE OE V CC V PP V SS PGM NC Function Address Input/output Chip enable Output enable Power supply Programming power supply Ground Programming enable No connection 2

Block Diagram A6 X-Decoder 1024 1024 Memory Matrix A15 I/O0 I/O15 Input Data Control Y-Gating Y-Decoder CE OE PGM A0 A5 V CC V PP H H : High Threshold Inverter V SS 3

Mode Selection Pin CE OE PGM V PP V CC A9 I/O G (2) (20) (39) (1) (40) (31) (3 10, 12 19) Mode CC (3) (22) (43) (2) (44) (35) (4 11, 14 21) Read V IL V IL V IH V CC V CC X Dout Output disable V IL V IH V IH V CC V CC X High-Z Standby V IH X X V CC V CC X High-Z Program V IL V IH V IL V PP V CC X Din Program verify V IL V IL V IH V PP V CC X Dout Page data latch V IH V IL V IH V PP V CC X Din Page program V IH V IH V IL V PP V CC X High-Z Program inhibit V IL V IL V IL V PP V CC X High-Z V IL V IH V IH V IH V IL V IL V IH V IH V IH Identifier V IL V IL V IH V CC V CC V H Code Notes: 1. X: Don t care 2. V H : 12.0 V ± 0.5 V Absolute Maximum Ratings Parameter Symbol Value Unit All input and output voltages * 1 Vin, Vout 0.6* 2 to +7.0 V A9 input voltage * 1 V ID 0.6* 2 to +13.5 V V PP voltage * 1 V PP 0.6 to +13.0 V V CC voltage * 1 V CC 0.6 to 7.0 V Operating temperature range Topr 0 to +70 C Storage temperature range Tstg 65 to +125 C Storage temperature range under bias Tbias 10 to +80 C Notes: 1. Relative to V SS. 2. Vin, Vout, V ID min = 1.0 V for pulse width ± 50 ns 4

Capacitance (Ta = 25 C, f = 1 MHz) HN27C1024HG Series Parameter Symbol Min Typ Max Unit Test Conditions Input capacitance Cin 12 pf Vin = 0 V Output capacitance Cout 15 pf Vout = 0 V HN27C1024HCC Series Parameter Symbol Min Typ Max Unit Test Conditions Input capacitance Cin 6 pf Vin = 0 V Output capacitance Cout 12 pf Vout = 0 V Read Operation DC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 5%, V PP = V CC ) Parameter Symbol Min Typ Max Unit Test Conditions Input leakage current I LI 2 µa Vin = 5.25 V Output leakage current I LO 2 µa Vout = 5.25 V/0.45 V V PP current I PP1 1 20 µa V PP = 5.5 V Standby V CC current I SB 25 ma CE = V IH Operating V CC current I CC1 50 ma CE = V IL, Iout = 0 ma I CC2 110 ma f = 12 MHz, Iout = 0 ma I CC3 25 ma f = 1 MHz, Iout = 0 ma, Input low voltage V IL 0.3* 1 0.8 V Input high voltage V IH 2.2 V CC + 1.0* 2 V Output low voltage V OL 0.45 V I OL = 2.1 ma Output high voltage V OH 2.4 V I OH = 400 µa Notes: 1. V IL min = 1.0 V for pulse width 50 ns 2. V IH max = V CC + 1.5 V for pulse width 20 ns If V IH is over the specified maximum value, read operation cannot be guaranteed. 5

AC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 5%, V PP = V CC ) Test Conditions Input pulse levels: 0.45 V to 2.4 V Input rise and fall time: 10 ns Output load: 1 TTL gate + 100 pf Reference levels for measuring timing: Inputs; 1.5 V Outputs; 1.5 V HN27C1024H -85-10 -12-15 Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions Address to output delay t ACC 85 100 120 150 ns CE = OE = V IL CE to output delay t CE 85 100 120 150 ns OE = V IL OE to output delay t OE 45 50 60 60 ns CE = V IL OE high to output float t DF 0 30 0 50 0 50 0 50 ns CE = V IL Address to output hold t OH 0 0 0 0 ns CE = OE = V IL Note: t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Read Timing Waveform Address CE Standby Mode Active Mode Standby Mode t CE OE t OE t DF t OH t ACC Data Out Data Out Valid 6

Fast High-Reliability Programming This device can be applied the programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. START SET PROG./VERIFY MODE V PP = 12.5 ± 0.3 V, V CC = 6.0 ± 0.25 V Address = 0 n = 0 n + 1 n Program t PW = 0.2 ms ± 5% Address + 1 Address VERIFY NOGO GO Program t OPW = 0.2n ms n = 25 NO NO LAST Address? YES YES SET READ MODE V CC = 5.0 V ± 0.25 V, V PP = V CC READ All Address NOGO END GO FAIL Fast High-Reliability Programming Flowchart 7

DC Characteristics (Ta = 25 C ± 5 C, V CC = 6 V ± 0.25 V, V PP = 12.5 V ± 0.3 V) Parameter Symbol Min Typ Max Unit Test Conditions Input leakage current I LI 2 µa Vin = 6.25 V/0.45 V Output low voltage during verify V OL 0.45 V I OL = 2.1 ma Output high voltage during verify V OH 2.4 V I OH = 400 µa Operating Vcc current I CC 50 ma Input low level V IL 0.1* 5 0.8 V Input high level V IH 2.2 V CC + 0.5* 6 V V PP supply current I PP 40 ma CE = PGM = V IL Notes: 1. V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP. 2. V PP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while V PP = 12.5 V. 4. Do not alter V PP either V IL to 12.5 V or 12.5 V to V IL when CE = low. 5. V IL min = 0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed. 8

AC Characteristics (Ta = 25 C ± 5 C, V CC = 6 V ± 0.25 V, V PP = 12.5 V ± 0.3 V) Test Conditions Input pulse levels: 0.45 to 2.4 V Input rise and fall time: 20 ns Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V Outputs: 0.8 V, 2.0 V Parameter Symbol Min Typ Max Unit Address setup time t AS 2 µs OE setup time t OES 2 µs Data setup time t DS 2 µs Address hold time t AH 0 µs Data hold time t DH 2 µs OE to output float delay t DF * 1 0 130 ns V PP setup time t VPS 2 µs V CC setup time t VCS 2 µs PGM initial programming pulse width t PW 0.19 0.2 0.21 ms PGM overprogramming pulse width t OPW * 2 0.19 5.25 ms CE setup time t CES 2 µs Data valid from OE t OE 0 150 ns Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Refer to the programming flowchart for t OPW. 9

Fast High-Reliability Programming Timing Waveform Program Program Verify Address t AS t AH Data Data in Stable Data Out Valid t DS t DH t DF V PP V PP V CC t VPS V CC V CC +1 V CC t VCS CE t CES PGM t PW toes t OE OE 10

Fast High-Reliability Page Programming This device can be applied the high performance page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. START SET PAGE PROGRAM LATCH MODE V PP = 12.5 ± 0.3 V, V CC = 6.0 ± 0.25 V Address = 0 n = 0 Latch Address + 1 Address Latch n + 1 SET PAGE PROG./VERIFY MODE V PP = 12.5 ± 0.3 V, V CC = 6.0 ± 0.25 V Program t PW = 0.2 ms ± 5% n NO n = 25 YES Address + 1 Address NOGO VERIFY GO Program t OPW = 0.2n ms NO LAST Address? YES SET READ MODE V CC = 5.0 V ± 0.25 V, V PP = V CC READ All Address NOGO END GO FAIL Fast High-Reliability Page Programming Flowchart 11

DC Characteristics (V CC = 6 V ± 0.25 V, V PP =12.5 V ± 0.3 V, Ta = 25 C ± 5 C) Parameter Symbol Min Typ Max Unit Test Conditions Input leakage current I LI 2 µa Vin = 6.25 V/0.45 V Output low voltage during verify V OL 0.45 V I OL = 2.1 ma Output high voltage during verify V OH 2.4 V I OH = 400 µa Operating V CC current I CC 50 ma Input low level V IL 0.1* 5 0.8 V Input high level V IH 2.2 V CC +0.5* 6 V V PP supply current I PP 50 ma PGM = V IL Notes: 1. V CC must be applied simultaneously or before V PP and removed simultaneously after V PP. 2. V PP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while V PP = 12.5 V. 4. Do not alter V PP either V IL to 12.5 V or 12.5 V to V IL when CE = low. 5. V IL min = 0.6 V for pulse width 20 ns. 6. If V IH is over the specified maximum value, programming operation cannot be guaranteed. 12

AC Characteristics (V CC = 6 V ± 0.25 V, V PP = 12.5 V ± 0.3 V, Ta = 25 C ± 5 C) Test Conditions Input pulse levels: 0.45 to 2.4 V Input rise and fall time: 20 ns Reference levels for measuring timings: Inputs; Outputs; 0.8 V, 2.0 V 0.8 V, 2.0 V Parameter Symbol Min Typ Max Unit Address setup time t AS 2 µs OE setup time t OES 2 µs Data setup time t DS 2 µs Address hold time t AH 0 µs t AHL 2 µs Data hold time t DH 2 µs OE to output float delay t DF * 1 0 130 ns V PP setup time t VPS 2 µs V CC setup time t VCS 2 µs PGM initial programming pulse width t PW 0.19 0.2 0.21 µs PGM overprogramming pulse width t OPW * 2 0.19 5.25 µs CE setup time t CES 2 µs Data valid from OE t OE 0 150 ns OE pulse width during data latch t LW 1 µs PGM setup time t PGMS 2 µs CE hold time t CEH 2 µs OE hold time t OEH 2 µs Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Refer to the programming flowchart for t OPW. 13

Fast High-Reliability Programming Timing Waveform Page data latch Page Program Program Verify A1 to A15 t AS t AHL t AH A0 t DF t DS t DH t PGMS t OE Data Data in Stable t VPS Data Out Valid V PP V PP V CC t VCS V CC +1 V CC VCC t CES t OEH CE t CEH PGM t LW t PW t OES OE Erase Erasure of HN27C4096G/CC is performed by exposure to ultraviolet light of 2537 Å and all the output data are changed to 1 after this erasure procedure. The minimum integrated dose (i.e. UV intensity exposure time) for erasure is 15 W sec/cm 2. 14

Mode Description Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C1024H Identifier Code Pin A0 I/O8 to I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 G (21) (10) to (3) (12) (13) (14) (15) (16) (17) (18) (19) Identifier CC (24) (11) to (4) (14) (15) (16) (17) (18) (19) (20) (21) Data Hex Manufacturer code V IL X 0 0 0 0 0 1 1 1 07 Device code V IH X 1 0 1 1 1 0 1 0 BA Note: X: Don t care, A9 = 12.0 V ± 0.5 V, A1 A8, A10 A15, CE, OE=V IL, PGM = V IH Electric Curves Supply Current I CC2 (Normalized) Supply Current vs. Supply Voltage 1.6 Ta=25 C Vin= V CC /V SS 1.4 f=12 MHz 1.2 1.0 0.8 0.6 4 5 6 Supply Voltage V CC (V) 15

Supply Current I CC2 (Normalized) Supply Current vs. Ambient Temperature 1.6 1.4 1.2 1.0 0.8 0.6 V CC =5. 0V Vin=V CC /V SS f=12 MHz 0.4 0 20 40 60 80 Ambient Temperature Ta ( C) Supply Current I CC (Normalized) 10 5 2 1.0 0.5 0.2 Supply Current vs. Frequency V CC =5 V Ta=25 C Vin=V CC /V SS 0.1 0.1 0.2 0.5 1.0 2 5 10 20 Frequency f (MHz) 16

Access Time t ACC, t CE (Nomalized) Access Time vs. Supply Voltage 1.4 Ta=25 C 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 Supply Voltage V CC (V) Access Time t ACC, t CE (Nomalized) Access Time vs. Ambient Temperature 1.3 V CC =5. 0V 1.2 1.1 1.0 0.9 0.8 0.7 0 20 40 60 80 Ambient Temperature Ta ( C) 17

Package Dimensions HN27C1024HG Series (DG-40A) Unit: mm 52.07 40 53.34 Max 21 φ8.89 1 1.32 20 2.54 Max 14.66 15.51 Max 0.51 Min 6.30 Max 15.24 2.54 ± 0.25 0.48 ± 0.10 2.54 Min 0 10 0.25 + 0.11 0.05 HN27C1024HCC Series (CC-44) Unit: mm 17.57 +0.16 0.24 +0.38 16.51 0.22 39 29 40 28 +0.16 0.24 17.57 44 1 φ 8.89 6 18 7 17 0.89 0.73 1.025 0.46 +0.07 0.13 15.75 +0.38 0.22 0.18 1.27 M 4.80 Max 2.75 Max 15.75 +0.38 0.22 0.15 18