CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components - Learn how to simulate Part 1: 2-bit Combinational Divider: Develop a minimized Boolean implementation of 2-bit combinational divider. The subsystem has two 2-bit inputs A,B (dividend) and C,D (divisor), and generates two 2-bit outputs, the quotient W,X and the remainder Y,Z. When the divisor = 00, assume that the quotient will be 00 and remainder will be same as dividend. (For eg., 3/0 will have a quotient=0 and remainder=3). Report should include: a. Design steps including Truth Table for W,X,Y and Z. b. Minimize the functions W,X,Y and Z using 4-variable K-maps. Write down the Boolean expressions for the minimized sum-of-products form of each function. c. Circuit schematic. d. Screen shot of the outputs W,X,Y and Z for the following input combinations: i. A,B = 00 and C,D = 10 ii. A,B = 01 and C,D = 10 iii. A,B = 10 and C,D = 01 iv. A,B = 11 and C,D = 01 Sol: a) Truth Table ABCD WXYZ 0000 0000 0001 0001 0010 0010 0011 0011 0100 0001 0101 0100 0110 0001 0111 0001 1000 0010 1001 1000 1010 0100
1011 0010 1100 0011 1101 1100 1110 0101 1111 0100 b) Boolean expressions: i. W = AC D ii. X = BC D + ABC + ACD = BC D + AC(B+D ) iii. Y = A B C + AC D + AB CD = AC D + B C(A + AD) iv. Z = BD + A B D + A CD = BD + A D(B +C) c) Circuit schematic: d) Screen shot of the outputs W,X,Y and Z for the following input combinations: i. A,B = 00 and C,D = 10 Output WXYZ = 0010
ii. A,B = 01 and C,D = 10 Output WXYZ = 0001 iii. A,B = 10 and C,D = 01 Output WXYZ = 1000 iv. A,B = 11 and C,D = 01 Output WXYZ = 1100
Part 2: Adder/ Subtractor Binary adder/subtractor based on a select input. Design a 4-bit adder/subtractor with the following specifications with minimum possible gatecount. Inputs: Two 4-bit unsigned binary numbers (A[3:0] & B[3:0]) and one bit select (Sel). Output: Sum output (S[3:0]) and Carry out (C_out). If Sel = 0 => (C_out,S) = A+B Sel = 1 => (C_out,S) = A-B Report should include: a. Write the Boolean equation for Sum and carry of a one-bit full adder and use it to design the 4-bit adder/subtractor. b. Circuit schematic c. Results: Include one screen snapshot of the simulator outcome for the following input combinations A= 5 and B= 9 and Sel = 0 A= 12 and B= 3 and Sel = 1 Sol: a) One bit Full Adder: Let x and y be the inputs and Cin be the carry in. i. Sum = x XOR y XOR Cin ii. Cout = xy + y.cin + Cin.z b) Circuit schematic
c) Results: i. A= 5 and B= 9 and Sel = 0 => Sum = 1110 ii. A= 12 and B= 3 and Sel = 1 => Sum = 1001 Part 3: Selective encoder: Implement a circuit that supports the following four encoding schemes to perform selective encoding on a 4-bit binary input. The design should enable a user to select from the available schemes through the use of two selective switches S0 and S1 as given below: Input ABC Select Switches Encoding Schemes S0, S1 3-bit binary 00 2 s Complement 01 Excess-3 Encoder 10 2421 Code 11 Gray Code For 2 s complement assume an implicit sign bit which is always 0 which implies that inputs for 2 s complement range from 0000 to 0111. Thus the output should be a 4-bit number for that switch setting. Information about Coding styles could be obtained from: http://www.asicworld.com/digital/numbering3.html Input (ABC) 2 s Complement (WXYZ) (S1,S0) = 00 Excess-3 (WXYZ) (S1,S0) = 01 2421 Code (WXYZ) (S1,S0) = 10 000 0000 0011 0000 000 001 0001 0100 0001 001 010 0010 0101 0010 011 011 0011 0110 0011 010 100 0100 0111 0100 110 101 0101 1000 1011 111 110 0110 1001 1100 101 111 0111 1010 1101 100 Report should include: a. Truth-table for the above design (Use the given table only) Gray code (WXYZ) (S1,S0) = 11
b. Boolean Expression from the truth table for each output of the four encoding schemes. c. Schematic of the circuit d. Screen Snapshot i.e. the simulation for the following combinations of input X=2, (S1, S0) = (0,0); X=4, (S1,S0) = (0,1); X=5, (S1, S0) = (1,0); X=7, (S1, S0) = (1,1). Sol: a) Truth table is given in the question. b) Boolean Expressions: a. 2 s Compliment: i. W = 0 ii. X = A iii. Y = B iv. Z = C b. Excess -3 encoding: i. W = AB + AC = A(B+C) ii. X = A B + A C + AB C = A (B+C) + AB C iii. Y = BC + B C = (B xor C) iv. Z = C c. 2421 encoding: i. W = AB + AC = A(B+C) ii. X = AB + AC = A (B+C ) iii. Y = A B + AB C iv. Z = C d. Gray encoding i. W = 0 ii. X = A iii. Y = AB + A B = A xor B iv. Z = BC + B C = B xor C c) Circuit Schematic:
d) Screen Snapshot i.e. the simulation for the following combinations of input i. ABC=010, (S1, S0) = (0,0); => Output = 0010 ii. ABC=100, (S1,S0) = (0,1); => Output = 0111 iii. ABC=101, (S1, S0) = (1,0); => Output = 1011 iv. ABC=111, (S1, S0) = (1,1). => Output = 0100 Part 4: 7-segment display decoder For a given binary input that is in the range of 000-111, design a circuit that outputs alphabets A, b, C, d, E, F, G, H on the 7 segment display (use the given table). X Y Z S1 S2 S3 S4 S5 S6 S7 0 0 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1
Report should include: a. Boolean Expression for each input b. Schematic of the same c. Screen Snapshot i.e. the simulation of the 7-segment decoder when the decimal equivalent of the input changes from 0 to 7. Sol: a) Boolean Expression: S1 = Z + XY S2 = YZ + X Y Z S3 = X Y + YZ + XY = (X xor Y) + YZ S4 = XZ + X Z + YZ = (X xor Y) + YZ S5 = 1 S6 = X + Y + Z S7 = X + Y + Z b) Schematic c) Simulation Screen shot: Input (X,Y,Z) = A[2:0] Part 5: (Calculate delay)
a. Find the best-case and worst-case time delays for a circuit (with minimum possible gate count) represented by the following Boolean equation: (A+B ) + (A+C) + (B+C) (Hint: Minimize the expression before computing the best/worst case delays). b. Show the CMOS circuit diagram for the same and also the truth table. c. Implement the circuit using logic gates and simulate using Xilinx tools. Provide a Screen Snapshot for the input combination: (A,B,C) = (1,0,1); (0,1,1). Measure the delay for the same and provide a Screen Snapshot for input combinations that give maximum and minimum delay. d. Simulate the same circuit using NAND and Inverter using Xilinx tools. What is the difference between the delays observed in (part a) and the delay in the design using NAND and Inverter gates? Sol: a) Minimizing the given Boolean expression: (A+B ) + (A+C) + (B+C) = ((A+B ). (A+C). (B+C)) = ((A + B ). (B + B ). (A + C). (B + C)) = ((AB + B ) + (AB + C)) = (AB + B C) Best and Worst case delay computations:
b) Truth Table: X Y Z Output 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0
CMOS Circuit Diagram: C) Using basic logic gates(and-or-inv):
d) Using Nand gates: For the particular input combination when input changing from 011 to 101, the delay for the output using AND-OR-INV logic is same as the output delay when NAND-INV logic is used.