Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate Capacitance Models

Urban & Fischer Verlag http://www.urbanfischer.de/journals/aeue Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate Capacitance Models Josef Dobeš Abstract: The problems with convergence caused by both voltageand charge-controlled models of MOSFET gate capacitances are often a iting factor of the computer aided design tools. In the paper an idea of the exponential smoothing of model discontinuities is proposed. The method is demonstrated on smoothing the gate capacitance discontinuity at zero drain-source voltage. An advanced integration algorithm convenient for the computer aided design of radio frequency and microwave CMOS circuits suppressing possible physically incorrect results of the traditional methods is also described. The updated model and algorithm are checked by analyzing a sophisticated CMOS flip-flop circuit. Keywords: CMOS circuits Flip-flops Gate capacitance CAD SPICE Modeling Numerical integration 1. Introduction The gate capacitance models have been thoroughly defined for the gate-source controlling voltage. However the models need a refinement for the case of a large drainsource voltage variation especially if the drain-source voltage changes its sign. The improvement achieved by the presented method will be demonstrated on an example of a CMOS flip-flop circuit analysis by an author s C.I.A. (Circuit Interactive Analyzer) program with built-in updated gate capacitance models. 2. Necessity for ensuring the convergence The SPICE3 program uses the Meyer s voltage controlled model the programs of the PSPICE family [1] contain both the same model and the Ward s charge controlled model at several levels especially for the BSIM class. In most cases the models do not have problems related to gate-source voltage changes. However if the drain-source voltage changes its sign during a transient analysis the problems with convergence can occur. Such problems are described in [2 pp. 197 198] for both Meyer s and Ward s models. For that reason a requirement for an updated Received October 14 2002. Revised April 18 2003. Czech Technical University in Prague Dept. of Radioelectronics Technická 2 16627 Praha 6 Czech Republic. E-mail: dobes@feld.cvut.cz model can be defined as C GS = C GS V DS 0+ V DS 0 C GD = C GD (1) V DS 0+ V DS 0 for the Meyer s model and (see the definition of related charges in [2 pp. 210 211 and 198]) V DS 0+ Q S = V DS 0 Q S V DS 0+ Q D = V DS 0 (2a) for the Ward s model. The condition (2a) is often written in the more usual form Q S Q S = V DS 0+ V Y V DS 0 V Y Q D Q D = (2b) V DS 0+ V Y V DS 0 V Y in view of dq X /dt = ( Q X / V Y ) V Y where the symbols X and Y stand for G B D and Y S. 3. Discontinuities of the classical models 3.1 Meyer s model The problem with discontinuities can easily be demonstrated on the classical Meyer s model which is defined in [1] in a simple form and in [2] in a complete form. However the actual implementation in the new SPICE programs slightly differs from that in [2]. Therefore let s define the updated model in the complete form with all the discontinuities to be considered. The definition of the Meyer s gate capacitance model splits for the normal mode (V DS 0) into the following regions: accumulation region for V GS V on φ S : C GB = C ox C GS = 0 C GD = 0 (3a) transition region for φ S < V GS V on φ S 2 : C GB = C ox V GS V on φ S C GS = 0 C GD = 0 Q D (3b) Int. J. Electron. Commun. (AEÜ) 57 (2003) No. 6 372 380 1434-8411/03/57/06-372 $15.00/0

Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... 373 depletion region for φ S 2 < V GS V on 0: V GS V on C GB = C ox φ S C GS = 2 ( 3 C ox 2 V ) GS V on + 1 φ S C GD = 0 (3c) saturation region for 0 < V GS V on V DS : C GB = 0 C GS = 2 3 C ox C GD = 0 (3d) linear region for V GS V on > V DS : C GB = 0 { C GS = 2 [ ] } 3 C VGS V on V 2 DS ox 1 2(V GS V on ) V DS C GD = 2 { [ ] } 3 C V GS V 2 on ox 1 ; (3e) 2(V GS V on ) V DS V on voltage is defined in the static part of the model [2] and acts as a boundary between the regions of the weak and strong inversions [3] φ S is the surface inversion potential and C ox is determined by the oxide permittivity and thickness effective channel length and width by the classical formula C ox = C ox L effw eff = ε ox L eff W eff. (4) t ox (The entire updated Meyer s gate capacitance model is shown in Fig. 1.) Easily observed the Meyer s modified model defined by (3) is continuous with respect to the gate-source voltage. However if the drain-source voltage is changing its sign whereas the gate-source voltage remains unchanged then a discontinuity might arise. For example suppose the gate-source voltage fulfills the condition for the saturation region i.e. 0 < V GS V on V DS the discontinuities arise for both source and drain gate capacitances C GS = C GD = 2 V DS 0+ V DS 0 3 C ox C GS = C GD = 0 V DS 0 V DS 0+ (5a) (5b) because in the reverse mode (V DS < 0) the roles of C GS and C GD must change. (Similarly V GD is the control voltage of the gate capacitance model instead of V GS in the reverse mode.) In other words it is natural to expect C GS = C GD (6) V DS 0 V DS 0 but this condition is not fulfilled in general. Fig. 1. Updated Meyer s gate capacitance model. 3.2 Ward s model The charge elements of the Ward s model can be expressed by equivalent capacitances [2] where C XY = sgn Q X XY (7) V Y { 1forX= Y sgn XY = 1 forx = Y are factors included so that C XY defined by (7) should be nonnegative the symbols X and Y stand for G B D and S again. The sixteen capacitances defined as Q X / V Y have been proposed to solve the problem of charge nonconservation in the Meyer s model [4]. Therefore they fulfill the two fundamental conditions:

374 Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... if all the terminal voltages change by an equal value the terminal charges remain the same i.e. C XY = 0 for X= G B D S; Y=GBDS the sum of the terminal currents induced by the capacitances is zero i.e. C GG + C BG + C DG + C SG = 0 C GB + C BB + C DB + C SB = 0 C GD + C BD + C DD + C SD = 0 C GS + C BS + C DS + C SS = 0. The definition of the Ward s model splits up to the following regions (similar to that in the Meyer s model): accumulation (V GS V FB ) subthreshold (V FB < V GS < V TH ) saturation (V GS V TH V DS V Dsat ) linear (V GS V TH V DS < V Dsat ); V FB V TH andv Dsat are the flatband threshold and saturation voltages defined in the static part of the model [5] respectively. The exact equations of the Ward s model are very complicated (especially for the 40/60 50/50 and 0/100 partitioning modes in the inversion linear region) and are defined in [6] and [7] in complete forms. Six of the sixteen capacitances are shown in Fig. 2 the problem of discontinuities related to the drain-source voltage is the same as that in the Meyer s model; moreover the capacitances are also discontinuous related to the gate-source voltage. Therefore the problems with convergence caused by the Ward s model are expected to be considerable and practical examples often confirm it. 4. Solution of the problem by exponential smoothing 4.1 Meyer s model The problem of discontinuities (5) and (6) can be easily overcome by means of the exponential factor ( F G = exp V ) DS for V DS 0 (normal mode) n smooth V T (8a) and F G = exp ( VDS n smooth V T ) for V DS < 0 (reverse mode) (8b) where n smooth is a new model parameter with a unit default value and V T is the thermal voltage. For all C GS and C GD capacitances ((3a) (3e)) the new ones are defined by smoothing formulae C GS = F C GS + C GD G + (1 F G ) C GS (9a) 2 C GD = F C GS + C GD G + (1 F G ) C GD ; (9b) 2 C GB capacitance does not have the problem of the discontinuity and therefore it is left without any changes i.e. C GB = C GB. In other words C GS and C GD capacitances are equal for V DS 0 now (in accordance with the physical reality the drain and source nodes can be considered connected when the drain-source voltage approaches zero) and they have the original unmodified values for V DS V T. 4.2 Ward s model Fig. 2. Ward s gate capacitance model six basic capacitances. Solving the problem of the discontinuities in the Ward s model is more difficult than that in the Meyer s one and it consists of the two steps: removing the discontinuities with respect to the gatesource voltage by the inclusion of transition regions analogous to (3b) in the updated Meyer s model removing the discontinuities with respect to the drainsource voltage by the same F G factors as used in the Meyer s model. The eqs. (8) and (9) can be considered a general tool for smoothing discontinuities i.e. for fulfilling (1) and (2).

Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... 375 5. Advanced algorithm for solving a system of algebraic-differential equations There is a very detailed derivation in [2 pp. 197 202] proving that the typical SPICE integration algorithm (e.g. a trapezoidal scheme demonstrated in [2]) in conjunction with the Meyer s model may cause physically incorrect results for the circuits with isolated nodes. For this and other reasons discussed below a special robust and very flexible algorithm has been used. The main features of the algorithm are characterized in this section. The algorithm has been built into the author s program C.I.A. which has been used for solving a sophisticated test example presented in the following section. An artificial example [2 p. 198] (to check the behavior of a circuit with isolated nodes) also solved by this algorithm can be found in the Appendix A 2. The system of algebraic-differential equations of a circuit is generally defined in an implicit form f ( x(t) ẋ(t) t ) = 0. (10) Let s assume now that the first n steps of a numerical integration of (10) have finished. To make equations simpler let s mark x(t n ) by x n and define backward scaled differences by the recursive formulae δ (0) x n = x n δ (i) x n = δ (i 1) x n α n (i 1) δ (i 1) x n 1 i = 1...k n + 2 (11) where k n is the order of a polynomial interpolation used in the last integration step and α n (0) = 1 α n (i) = t n t n i α(i 1) n i = 1...k n + 1. (12) t n 1 t n 1 i The predictor of the variables for the next chosen time (i.e. for t ) marked by x (0) is determined by the extrapolation using the backward scaled differences (11) in the explicit form (see Theorem 1 in the Appendix A 1) k x (0) = i=0 α (i) δ(i) x n. (13) By differentiating (13) with respect to t the predictor of derivatives may also be expressed as k ẋ (0) = i=0 β (i) δ(i) x n (14) where the β multipliers may simply be derived from the recursive form (12) in terms of the α ones β n (0) = 0 β (i) n = α(i 1) n + (t n t n i )β n (i 1) i = 1...k n. (15) t n 1 t n 1 i (Using (15) in (14) needs replacing the subscript n by n + 1 of course.) The corrector of the variables x ( j max) x for t is determined by using modified Newton iterations (the symbol x marks an element of the vector x) [ ( ) f ( j) ( ) ] dẋ + x [ ( ) f ( j) x ( ) f ( j) ẋ dx ] ( ) f ( j) + γ ẋ x ( j) = x ( j) = f ( j) j = 0... j max < MAXIT (16) (MAXIT is a maximum number of iterations in one integration step) i.e. by repeated solving the linear system (16) with applying the implicit form of the derivatives approximation (see Theorem 2 in the Appendix A 1) ẋ ( j) = t t x ( j) x t t k 1 = δ (i) x ( j) t t i i=1 k 1 γ = (17) t t i i=1 which gives a standard formula γ = 1 / (t t n ) = 1 / t if the first order (Euler) method is used. After resolving the linear system (16) the vectors x (... ) are updated and ẋ (... ) x ( j+1) = x ( j) j) + x( (18a) ẋ ( j+1) = ẋ ( j) + γ x ( j). (18b) However if an indication of divergence is detected during the iterations then logarithmic damping 1 (again the symbol x marks an element of the vector x) ( ) x ( j) := sgn x ( j) x ( j) ln 1 + x ( j) x ( j) (19) may be used 2 for all the elements of the vector x ( j) before updating to subsequent values by (18). A new length of the integration step t and a new order of the polynomial interpolation k aretobechosen after converging the corrector (16) and (18) the 1 Idea of logarithmic damping is based on Maclaurin series ln(1 + x) = x x 2 /2 + x 3 /3 + x if x 0. 2 More precisely ( j ) x + NULL is used instead of x ( j ) to avoid possible zero division (NULL is another algorithm controlling parameter).

376 Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... quality of the two procedures is very important for the efficiency of the algorithm. Firstly an estimation of the interpolation error in the last step must be determined. In general the absolute truncation error for the k order caused by the derivatives approximation (17) may be written as t e = δ (k+1) x (20) t t n k for any element x of the vector x. The relation (20) for the element e of the absolute truncation error vector e must be modified in the following way: the absolute errors are replaced by the relative ones (to be comparable with one another and with an algorithm parameter) the fraction t /(t t n k ) is omitted (to give a preference to simpler and more stable lower interpolation orders). Consequently the relative truncation error acquires the simple form 3 δ (k +1) x ε = max x x x x x (0) = max. (21) x x x (See the final equality in eq. (A2) of the proof of Theorem 1 in the Appendix A1 and (13) as a simple derivation of the second equality in (21).) Therefore the truncation error may be checked by the difference between the corrector and the predictor the step may be rejected and halved even after the first iteration of the corrector if the truncation error seems too big. Secondly the new step and order are determined by means of the error (21). Generally the truncation errors of the ith interpolation order can be determined by the formulae (consider a component of e with the greatest error) ( d e (i) i+1 ) = x const.(i) t i+1 e (i) = const.(i) dt i+1 ( d i+1 ) x dt i+1 t i+1. The new step estimate is based on the assumption of a similarity of neighboring steps const. (i) const.(i) ( d i+1 ) ( x d i+1 ) x dt i+1 dt i+1 3 Similarly as that in logarithmic damping ( j ) x + NULL is used instead of ( j ) x to avoid possible zero division. which gives the relation e (i) e (i) ( t t ) i+1 ε(i) ε (i) The error in the following integration step is to be equal to ε prescribed relative truncation tolerance i.e. ( t is already known when t (i) should be compared for all possible i) ε t (i) = t i+1 ε (i) i = 1... k + 1 (22) where all the possible truncation relative errors ε (i) are computed directly by the δ (i+1) x (that is why the differences (11) are defined up to the k n + 2order sothat the order of the polynomial interpolation can sequentially increase). However the step increase is ited due to the stability conditions especially for higher orders of interpolation see the stability comparisons of the basic implicit integration methods in [8]. Thus the relation (22) must be modified by a semiempirical factor t (i) = t i+1 t i+1 4 ε ε (i) for ε ε (i). < 4 otherwise i = 1...k + 1 (23) where the factor i+1 4 may theoretically be derived under special circumstances only; however it has been proven by thousands practical analyses as well. In conclusion the new k order (k {1... k + 1}) is chosen whose step determined by (23) is the longest. To summarize the algorithm defined above has the following merits: it is also usable for the CMOS circuits with isolated nodes see the solution of the artificial example in the Appendix A 2 it is usable in conjunction with the smoothed Meyer s model for reliable analyses of (practically) arbitrary accuracy see Table 1 in Section 6 it is convenient for analyses of microwave (i.e. fast) devices let s consider that the very short time steps in (12) are divided by one another (they are not multiplied as those in standard interpolation schemes which may cause underflow errors for higher orders) the algorithm is more flexible than the Gear s method implemented in PSPICE with respect to quick step and order alterations the order of the interpolation may change in every step for instance the algorithm is convenient for the enhancement towards a time domain sensitivity analysis [9] due to its efficiency the results are obtained in a reasonable time.

Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... 377 6. Test of exponential smoothing the discontinuities A radio frequency CMOS flip-flop circuit appeared to be an appropriate convergence test. Only a part of the whole integrated circuit is necessary for the test (see Fig. 3). The clock reset inp outp FLIP-FLOP inv outp first NOR inp FLIP-FLOP nor second outp inv outp Fig. 3. Block diagram of the probed fraction of a large CMOS integrated circuit see Figs. 4 and 5 for FLIP-FLOP and NOR respectively. circuit caused serious convergence problems in SPICE analyses because it contains the transistors which alternate the sign of the drain-source voltage during the transient analysis. Therefore the analyses have been performed by the algorithm discussed in Section 5. The subcircuits FLIP-FLOP and NOR are shown in Figs. 4 and 5 respectively. Each of the transistors is labeled by the SPICE s AREA factor. The threshold voltages and other parameters of the static model are determined for all the transistors from a set of technological parameters. The gate capacitors are defined by the eqs. (3a 3e) for the classical model and by the updates (8) and (9) for the smoothed one both are determined by (4) (with the oxide thickness 50 nm) and several parameters of the static model modifying the voltage V on and effective channel length L eff. The capacitance part of the model is complemented by three (slight) gate overlap capacitors and of course by junction capacitors ([2 5]) with the zero-bias bottom capacitances 0.2 pf and the zero-bias perimeter capacitances 0.05 pf. The results of the test are shown in Fig. 6. Table 1 summarizes the fundamental differences between the analyses of the test circuit with the classical and updated models by inp to inv outp 1.2 +5 V 3.0 3.3 reset 4.9 3.1 1.2 5.9 3.1 2.5 1.3 6.2 outp 5.4 4.3 2.1 5.8 3.6 5.8 4.6 3.2 1.3 1.5 5.0 2.8 4.4 inv outp Fig. 4. The CMOS flip-flop circuit used as a test of convergence the numbers represent SPICE s AREA factors.

378 Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... +5 V inp1 5.2 inp2 5.2 outp 4.0 4.0 Fig. 5. The CMOS negative-or circuit. the algorithm of Section 5. As expected and also received by SPICE analyses the results using classical models show several non-convergences: here for 200 MHz clock signal with 250 ps rise and fall times 5 and 10 nonconvergences occurred for ε = 5 10 3 and ε = 2 10 3 respectively even for the maximum number of iterations allowed in one integration step MAXIT = 200. Let s emphasize that huge numbers of non-convergenceshave been received for the classical Meyer s model if ε 10 3 and therefore such analyses are impossible. Moreover the problems with convergence cause a number of logarithmic dampings (19) to be used in the case of classical model and which is the worst the number of LU factorizations of the Jacobian in (16) to be executed is considerably higher. As an illustration of the algorithm flexibility let s compare the results for the smoothed model if the relative truncation tolerance ε varies from 10 2 to 10 6 (the first and last rows for the smoothed model) while the error is 10000 times lesser the number of necessary LU factorizations is only 10 times greater! Fig. 6. Results of the test the first flip-flop is switched by the clock signal the second is switched by the first one. 7. Conclusions An exponential smoothing for the eination of the discontinuities is suggested for both Meyer s and Ward s gate capacitance models. The method is tested on a sophisticated CMOS flip-flop circuit with transistors changing signs of their drain-source voltages with time. A reliable and flexible integration algorithm convenient for the time domain analyses of the fast CMOS circuits has been characterized with some improvements. Basic theorems of the modified numerical integration algorithm have been proven. Acknowledgement. This paper has been supported by the Grant Agency of the Czech Republic grant N o Table 1. Comparison of the results using the classical and smoothed models. Task specification Total number of Gate capacitance model Truncation relat. toler. Non-convergences Solut. of lin. equat. LU-factorizations Logaritm. dampings 10 2 0 2193 1650 0 Meyer s classical 5 10 3 5 3575 2903 987 2 10 3 10 5550 4525 1978 10 2 0 2153 1612 0 5 10 3 0 2484 1853 0 2 10 3 0 3217 2349 0 Meyer s smoothed 10 3 0 3671 2678 0 10 4 0 7117 5150 0 10 5 0 12634 9235 0 10 6 0 21020 15446 0 Analyses with the classical model cause a lot of non-convergences if the truncation relative tolerance is 10 3.

Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... 379 102/01/0432 (the algorithmic part) and by the Research Program N o J04/98:212300014 of the Czech Technical University in Prague (the model part). Appendix A 1. Fundamental interpolation and algebraization formulae Theorem 1 (Universal interpolation principle). The formula (13) can be regarded as a transformed Newton interpolation polynomial. Proof : A member of the classical Newton interpolation polynomial x = x n + (t t n ) x nn 1 + (t t n )(t t n 1 ) x nn 1n 2 + + ) (t t n ) (t t k xn...n k (A1a) where x nn 1... = x n x n 1 t n t n 1 x n...n k = x n... k x n 1...n k t n t n k may sequentially be transformed in the following way: (t t n ) (t t i ) x n...n i = (t t n ) (t t i ) t n t n i (x n... i x n 1...n i ) = (t t n ) (t t i ) (t n t n i )(t n t i ) [ xn... i x n 1... i (t n t i ) ] (t t n ) (t t i ) x n 1...n i = = (t n t n i ) (t n t n 1 ) [ x n x n 1 (t n t n 1 ) x n 1n 2 (t n t n 1 )(t n t n 2 ) x n 1n 2n 3 ] (t n t n 1 ) (t n t i ) x n 1...n i = [ x n x n 1 t n t n 1 (x n 1 x n 2 ) t n 1 t n 2 α (i) α (2) n {}}{ (t n t n 1 )(t n t n 2 ) (t n 1 t n 3 )(t n 1 t n 2 ) (A1b) α (1) δ (1) n 1 x n 1 {}}{ δ (1) x n 2 {}}{ (t n 1 t n 2 ) {}}{ x n 1 x n 2 (x n 2 x n 3 ) (t n 2 t n 3 ) }{{} δ (2) x n 1 ] ( = α (i) x n x n 1 α n (1) δ(1) x n 1 ) α n (i 1) δ (i 1) x n 1 = α (i) δ(i) x n. (A2) Thus the Newton interpolation polynomial (A1) is reordered to a more convenient form. Theorem 2 (Algebraization). The approximation of the derivatives (17) can be regarded as a borderline case of using the formula (13). Proof : The vector x ( j) is to be expressed as a polynomial created by (13) and (12): x ( j) x = t t t t ( t t 1 t t n δ (1) x ( j) + 1 t t n δ (2) x ( j) t t n t t + + n 1 ) 1 t k t δ (k ) ( j) x = t t n t t k k i=1 1 t t i δ (i) x ( j) ; (A3) the last formula in (A3) gives the γ factor in (16). A 2. CMOS circuits with isolated nodes Consider an artificial circuit in Fig. A 1. The gate node of the MOSFET cannot change its charge due to the 0.5 pf capacitor. There exists an analytical expression [2 pp. 197 198] stating that the gate voltage must be growing continuously if the classical Meyer s model is used. The simulation results [2 p. 199] confirm this analytical derivation. Moreover a simulation of the same circuit using the Ward s model provides correct results. The same circuit has also been analyzed by the C.I.A. program using the smoothed Meyer s model the results of the simulation are presented in Fig. A 2. The gate voltage is correct now similar to the result in [2] using the Ward s model. The physical eccentricity of the circuit is proven only by the requirement of a very large number of integration steps.

380 Josef Dobeš: Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate... References Fig. A 1. An artificial circuit with a node which cannot change its charge. [1] Vladimirescu A.: The SPICE book. New York: John Wiley & Sons 1994. [2] Massobrio G.; Antognetti P.: Semiconductor device modeling with SPICE. New York: McGraw-Hill 1993. [3] Singh J.: Semiconductor devices. New York: John Wiley & Sons 2001. [4] Sheu B. J.; Scharfetter D. L.; Ko P. K.; Jeng M.-C.: BSIM: Berkeley short-channel IGFET model for MOS transistors. Journal of Solid-State Circuits 22 (1987) 558 566. [5] Cadence SPICE reference. San Jose: Cadence Design Systems 1993. [6] Cheng Y.; Hu C.: MOSFET modeling and BSIM3 user s guide. Boston: Kluwer Academic Publishers 1999. [7] Liu W.: MOSFET models for SPICE simulation including BSIM3v3 and BSIM4. New York: John Wiley & Sons 2001. [8] Petrenko A. I.; Vlasov A. I.; Timtschenko A. P.: Tabular methods of computer-aided modeling. (In Russian.) Kiyv: Higher School 1977. [9] Dobeš J.: Nonstandard sensitivity analyses in frequency and time domains. Proc. of IEEE Int. Conf. on Electronics Circuits and Systems Dubrovnik Croatia 3 (2002) 1119 1122. Fig. A 2. Correct C.I.A. results of the circuit with the isolated node. As an outcome the smoothed models in conjunction with the improved integration algorithm described above can be considered to be robust tools for the radio frequency and microwave CMOS circuit analysis. Josef Dobeš received the Ph.D. degree in microelectronics from the Czech Technical University Prague in 1986. From 1986 to 1992 he was a researcher of the TESLA Research Institute where he performed analyses on algorithms for CMOS Technology Simulators. Currently he is with the Department of Radioelectronics of the Czech Technical University. His research interests include the physical modeling of radioelectronic circuit elements especially RF and microwave transistors and transmission lines creating or improving special algorithms for the circuit analysis and optimization such as time- and frequency-domain sensitivity poles-zeros or steady-state analyses creating a comprehensive CAD tool for the analysis and optimization of RF and microwave circuits.