A B OUT_0 OUT_1 OUT_2 OUT_3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 A Decoder is something that does the opposite of encoding; it converts the data back into its original form. This decoder converts data from binary into decimal, and is also a 2 bit decoder meaning it allows 4 different choices ranging from 0 to 3. This decoder allows the 4 to 1 Multiplexer to choose from the 4 inputs it has. The waveform corresponds with the truth table in a way that shows the conversion from binary to decimal where A and B are in binary and OUT_0, OUT_1, OUT_2, and OUT_3 all correspond to their decimal counterparts (OUT_0 = 0, OUT_1 = 1, etc.). The design for this decoder came from the book Logic and Computers Design Fundamentals by Mano and Kime, page 122. The design is that of a 2-to-4 line decoder.
IN ENABLER OUT 0 0 0 0 1 0 1 0 0 1 1 1 An Enabler allows for a certain path to be able to move through thro and gates and the use of an enabler source. The enabler takes an 8 bit input from the source in the 4 to 1 Multiplexer and runs it into the Enabler. The input and the output of the enabler are the same so the data isn t changed while passing thro. The data is only passed when the enabler is started by an outside source, essentially the enabler has been chosen to allow the data to pass through the enabler itself and finish the circuit. The enabler ipin is changed by the decoder inside of the Multiplexer. The data is only able to pass thru the enabler if the ENABLER ipin has data passing thru it. The waveform and the truth table show this. The data will only pass this way because it is all run through AND gates that are connected with the ipin as an input. This design is a change on the design from the textbook, Logic and Computers Design Fundamentals by Mano and Kime, so that only the and gates are present and the OR gates are used in the Combiner. This designed allowed less connections and easier testing.
A_IN B_IN C_IN D_IN COMB_OUT 1 0 0 0 A_IN 0 1 0 0 B_IN 0 0 1 0 C_IN 0 0 0 1 D_IN 0 0 0 0 0 This OR gate set up combines the date down to 1 output, so it is essentially a combiner. This is the part that performs to to 1 in the 4 to 1 Multiplexer. The data will remain the same as it passes through the combiner. The Waveform and the truth table show that the output will remain the same as the input. The design is changed from the design in the book, Logic and Computers Design Fundamentals by Mano and Kime, so that the inputs come from the Enabler which already had the chosen data sent thru it. The design allows all inputs, that can be selected, to be put through the same series of OR gates, but only one series input leaves.
SELECT 0 1 2 3 OUT 0 1 0 0 0 0 1 0 1 0 0 1 2 0 0 1 0 2 3 0 0 0 1 3 A Multiplexer is a circuit that takes an input of binary information and directs it to a single output line, this multiplexer is a 4 to 1. It uses the 2-to-4 line decoder to allow for the direction of the data through the multiplexer by switching the enablers on or off. The enabler then sends the data to the combiner which then combines the data and sends it out for the final output. The reasons for the values chosen in the Waveform and the truth table are to see if a connection was made correctly since all the sub designs have been tested and proven to work properly. The OUT column is numbered from 0 thru 3, the meaning for that is that the value of each of the data pertaining to the selects input will be passed thro and is equal to that input. The design for this Multiplexer came from the textbook Logic and Computers Design Fundamentals by Mano and Kime, page 134. The only change in the design was making the AND OR gates into two separate sub designs which made it easier to test and made a cleaner final design.
X_IN Y_IN C_IN S_OUT C_OUT 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 An 8-Bit adder is 8 Full Adders connected to each other that takes 8 Bit inputs. The adder in the book Logic and Computer Design and Function: Fourth Edition on page 169 was the basis of the design I used. The adder takes in three inputs, X, Y, and C IN, and runs them through to end up with an output of S and C OUT, where C OUT can be carried onto the next operation. The design for this adder is that of a ripple carry adder where it takes the C IN to be that of a C OUT of a previous adder.