Feaures Triple channel device wih inegraed and proeced oupu sages (curren sources), opimized o drive LEDs as addiional low cos curren source High oupu curren (up o 80 ma) per channel Very low curren consumpion in sleep mode Very low oupu leakage when channel is off Low curren consumpion during faul Addiional oupu curren demand suppored by LITIX Companion direc drive Very high precision digial dimming suppored Inelligen faul managemen: up o 16 and more devices can share a common error nework wih only one exernal resisor Reverse polariy proecion allows reducion of exernal componens and improves sysem performance a low baery/inpu volages Overload proecion Wide emperaure range: -40 C < T J < 150 C Oupu curren conrol via exernal low power resisor Green produc (RoHS complian) Poenial applicaions Cos effecive sop / ail funcion implemenaion wih shared and separaed LEDs per funcion Turn indicaors Posiion, fog, rear lighs and side markers Animaed ligh funcions like wiping indicaors and welcome/goodbye funcions Day Running Ligh Inerior lighing funcions like ambien lighing (including RGB color conrol), illuminaion and dash board lighing LED indicaors for indusrial applicaions and insrumenaion Produc validaion Qualified for Auomoive Applicaions. Produc Validaion according o AEC-Q100/101. Daashee Rev. 1.00 www.infineon.com 1
Descripion The TLD2331-3EP is a riple channel high-side driver IC wih inegraed oupu sages. I is designed o conrol LEDs wih a curren up o 80 ma. In ypical auomoive applicaions he device is capable of driving 3 red LEDs per chain (oal 9 LEDs) wih a curren up o 60 ma and even above, if no limied by he overall sysem hermal properies. Pracically, he oupu curren is conrolled by an exernal resisor or reference source, independenly from load and supply volage changes. Table 1 Produc summary Parameer Symbol Values Operaing volage V S(nom) 5.5 V 40 V Maximum volage V S(max) 40 V V OUTx(max) Nominal oupu (load) curren I OUTx(nom) 60 ma (nominal) when using he auomoive supply volage range 8 V - 18 V. Currens up o I OUTx(max) are possible wih low hermal resisance R hja Maximum oupu (load) curren I OUTx(max) 80 ma depending on R hja Curren accuracy a R SET = 10 kω K LTx 300 ±5% Curren consumpion in sleep mode I S(sleep, yp) 0.1 µa Maximum curren consumpion during faul I S(faul, ERRN) 850 µa or less when faul is deeced from anoher device (disabled via ERRN) Type Package Marking TLD2331-3EP PG-TSDSO-14 TLD2331 Daashee 2 Rev. 1.00
Table of Conens 1 Block diagram................................................................... 4 2 Pin configuraion................................................................. 5 2.1 Pin assignmen........................................................................... 5 2.2 Pin definiions and funcions.............................................................. 5 3 General produc characerisics.................................................... 7 3.1 Absolue maximum raings................................................................ 7 3.2 Funcional range......................................................................... 8 3.3 Thermal resisance....................................................................... 9 4 Inernal supply.................................................................. 10 4.1 Descripion............................................................................. 10 4.2 Elecrical characerisics inernal supply and EN pin........................................ 12 5 Power sages................................................................... 14 5.1 Proecion.............................................................................. 14 5.1.1 Thermal proecion.................................................................... 14 5.1.2 Reverse baery proecion.............................................................. 15 5.2 Oupu configuraion via IN_SETx and PWMI pins........................................... 15 5.2.1 IN_SETx pins.......................................................................... 15 5.2.2 Oupu curren adjusmen via R SET...................................................... 15 5.2.3 Oupu conrol via IN_SETx............................................................. 16 5.2.4 IN_SETx pins behavior during device faul managemen................................... 17 5.2.5 Timing diagrams....................................................................... 17 5.3 Elecrical characerisics power sage...................................................... 19 5.4 Elecrical characerisics IN_SETx and PWMI pins for oupu seings......................... 21 6 Load diagnosis.................................................................. 23 6.1 Error managemen via ERRN and D-pins................................................... 23 6.1.1 ERRN pin.............................................................................. 23 6.1.2 D-pin................................................................................. 25 6.2 Open Load (OL) and shor OUTx o GND (SC)............................................... 26 6.2.1 Faul managemen (D-pin open or conneced wih a capacior o GND)..................... 26 6.2.2 Faul managemen (D-pin conneced o GND)............................................ 28 6.3 Single LED Shor deecion, SLS_REF and DS pins........................................... 30 6.3.1 SLS_REF pin........................................................................... 31 6.3.2 DS pin................................................................................ 32 6.3.3 SLS faul deecion..................................................................... 32 6.3.4 SLS faul managemen: D and DS pins open or conneced wih capaciors o GND (low power consumpion mode wih rery sraegy) 32 6.3.5 SLS faul managemen: D-pin shored o GND............................................ 33 6.4 Elecrical characerisics: Load diagnosis and Overload managemen......................... 34 7 Applicaion informaion.......................................................... 37 8 Package ouline................................................................. 38 9 Revision Hisory................................................................. 39 Daashee 3 Rev. 1.00
Block diagram 1 Block diagram 10 VS 9 7 5 6 EN/DEN D DS PWMI Inernal supply Thermal proecion Oupu conrol & proecion ERRN SLS_REF OUT3 OUT2 OUT1 14 1 11 12 13 2 3 4 IN_SET1 IN_SET2 IN_SET3 Curren references TLD2331-3EP GND 8 Figure 1 Block diagram Daashee 4 Rev. 1.00
Pin configuraion 2 Pin configuraion 2.1 Pin assignmen SLS_REF IN_SET1 IN_SET2 IN_SET3 DS PWMI D 1 2 3 4 5 6 7 EP 14 13 12 11 10 9 8 exposed pad (boom) TLD2331-3EP ERRN OUT1 OUT2 OUT3 VS EN/DEN GND Figure 2 Pin configuraion 2.2 Pin definiions and funcions Pin Symbol Funcion 10 VS Supply volage; Conneced o baery or supply conrol swich, wih EMC filer 8 GND Ground; Signal ground 2 IN_SET1 Conrol inpu for OUT1 channel; Connec o a low power resisor o adjus OUT1 oupu curren. Alernaively, a differen curren reference (i.e. he OUT_SET of anoher LED Driver) may be conneced 3 IN_SET2 Conrol inpu for OUT2 channel; Connec o a low power resisor o adjus OUT2 oupu curren. Alernaively, a differen curren reference (i.e. he OUT_SET of anoher LED Driver) may be conneced 4 IN_SET3 Conrol inpu for OUT3 channel; Connec o a low power resisor o adjus OUT3 oupu curren. Alernaively, a differen curren reference (i.e. he OUT_SET of anoher LED Driver) may be conneced 6 PWMI PWM inpu; Connec o an exernal PWM conroller. If no used, connec o GND 1 SLS_REF Single LED shor reference inpu; Connec o a low power resisor or a volage reference o adjus Inernal SLS hreshold. If no used, connec o GND 5 DS Single LED shor delay/resar inpu; Connec o a capacior, leave open or connec o GND, depending on he required diagnosis managemen for single LED shor deecion (see Chaper 6 for furher deails) 7 D Disable/delay error inpu; Connec o a capacior, leave open or connec o GND, depending on he required diagnosis managemen (see Chaper 6 for furher deails) Daashee 5 Rev. 1.00
Pin configuraion Pin Symbol Funcion 14 ERRN ERROR flag I/O; Open drain, acive low. Connec o a pull-up resisor 9 EN/DEN Oupus enable and diagnosis conrol inpu; Connec o a conrol inpu (i.e. o VS via a resisor divider or a Zener diode) o enable OUTx conrol and diagnosis capabiliy 13 OUT1 Channel 1 oupu pin; Connec o he arge load 12 OUT2 Channel 2 oupu pin; Connec o he arge load 11 OUT3 Channel 3 oupu pin; Connec o he arge load Exposed Pad EP Exposed Pad; Conneced o GND-pin in applicaion Daashee 6 Rev. 1.00
General produc characerisics 3 General produc characerisics 3.1 Absolue maximum raings Table 2 Absolue maximum raings 1) T J = -40 C o +150 C; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Volage Supply volage V S -18 40 V P_4.1.1 EN/DEN volage V EN/DEN -18 40 V P_4.1.3 EN/DEN volage relaed o V S : V EN/DEN(VS -40 18 V P_4.1.4 V EN/DEN - V S ) EN/DEN volage relaed o V OUTx : V EN/DEN(V -18 40 V P_4.1.5 V EN/DEN - V OUTx OUTx) Oupu volages V OUTx -1 40 V P_4.1.10 Oupu volages relaed o V S : V S V OUTx(VS) -18 40 V P_4.1.11 - V OUTx IN_SETx volages V IN_SETx -0.3 6 V P_4.1.12 PWMI volage V PWMI -0.3 6 V P_4.1.14 ERRN volage V ERRN -0.3 40 V P_4.1.18 D Volage V D -0.3 6 V P_4.1.19 DS volage V DS -0.3 6 V P_4.1.42 SLS_REF volage V SLS_REF -0.3 6 V P_4.1.43 Curren Oupu currens (On each I OUTx 0 90 ma P_4.1.21 oupu channel OUTn) PWMI curren I PWMI -0.5 0.5 ma P_4.1.26 IN_SETx currens I IN_SETx 0 300 µa P_4.1.30 D curren I D -0.5 0.5 ma P_4.1.31 DS curren I DS -0.5 0.5 ma P_4.1.44 SLS_REF curren I SLS_REF -0.5 0 ma P_4.1.45 Temperaure Juncion emperaure T J -40 150 C P_4.1.33 Sorage emperaure T sg -55 150 C P_4.1.34 ESD suscepibiliy ESD suscepibiliy all pins o GND V ESD -2 2 kv HBM 2) P_4.1.36 Daashee 7 Rev. 1.00
General produc characerisics Table 2 Absolue maximum raings 1) (con d) T J = -40 C o +150 C; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion ESD suscepibiliy all pins o V ESD -500 500 V CDM 3) P_4.1.37 GND ESD suscepibiliy Pin 1, 7, 8, 14 (corner pins) o GND V ESD1,7,8,1 4-750 750 V CDM 3) P_4.1.38 1) No subjec o producion es, specified by design 2) ESD suscepibiliy, HBM according o ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pf) 3) ESD suscepibiliy, Charged Device Model CDM according JEDEC JESD22-C101 Noes 1. Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. 2. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 3.2 Funcional range Table 3 Funcional range Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Volage range for normal V S(nom) 5.5 18 V P_4.2.1 operaion Exended supply volage for V S(ex) V SUV(ON) 40 V P_4.2.2 funcional range Juncion emperaure T J -40 150 C P_4.2.4 Noe: Wihin he Normal Operaion range, he IC operaes as described in he circui descripion. Wihin he Exended Operaion range, parameers deviaions are possible. The elecrical characerisics are specified wihin he condiions given in he Elecrical Characerisics able. Daashee 8 Rev. 1.00
General produc characerisics 3.3 Thermal resisance Noe: This hermal daa was generaed in accordance wih JEDEC JESD51 sandards. For more informaion, go o www.jedec.org. Table 4 Thermal resisance 1) Parameer Symbol Values Uni Noe or Min. Typ. Max. Tes Condiion Juncion o Case R hjc 10 K/W 1)2) Juncion o Ambien 1s0p board Juncion o Ambien 2s2p board R hja1 R hja2 61 56 45 43 Number P_4.3.1 1) No subjec o producion es, specified by design. 2) Specified R hjc value is simulaed a naural convecion on a cold plae seup (all pins and exposed pad are fixed o ambien emperaure). T A = 85 C. Toal power dissipaion = 1.5 W 3) Specified R hja value is according o Jedec JESD51-3 a naural convecion on FR4 1s0p board. The produc (chip+package) was simulaed on a 76.2 114.3 1.5 mm board wih 70 µm Cu, 300 mm 2 cooling area. Toal power dissipaion 1.5W disribued saically and homogenously over all power sages 4) Specified R hja value is according o Jedec JESD51-5,-7 a naural convecion on FR4 2s2p board; The produc (chip+package) was simulaed on a 76.2 114.3 1.5 mm board wih 2 inner copper layers (2 70 mm Cu, 2 35 mm Cu). Where applicable a hermal via array under he exposed pad conaced he firs inner copper layer. Toal power dissipaion 1.5W disribued saically and homogenously over all power sages K/W 1)3) K/W 1)4) T A = 85 C T A = 135 C T A = 85 C T A = 135 C P_4.3.3 P_4.3.4 Daashee 9 Rev. 1.00
Inernal supply 4 Inernal supply This chaper describes he inernal supply in is main parameers and funcionaliy. 4.1 Descripion The inernal supply principle is highlighed in he concep diagram of Figure 3. If he volage applied a he EN/DEN pin is below V EN(h) he device eners sleep mode. In his sae all inernal funcions are swiched off and he curren consumpion is reduced o I S(sleep). As soon as he volage applied a he supply pin V S is above V SUV(ON) and he volage applied a he EN/DEN pin is above V EN(h), afer he power-on rese ime POR, he device is ready o deliver oupu curren from he oupu sages. The power on rese ime POR has o be aken ino accoun also in relevan applicaion condiions, i. e. wih PWM conrol from VS or EN/DEN lines. V SUV VS - + EN/DEN Inernal Supply V EN(h) - + + - OUTx Conrol OUTx Diagnosis Conrol V DE N(h) Figure 3 Inernal supply Furhermore, as soon as he volage applied a he supply pin VS is above V SUV(ON) and he volage applied o he EN/DEN pin V EN is above V DEN(h), he device is ready o deec and repor faul condiions via ERRN (error nework pin) as described in Chaper 6. To program oupus enable and diagnosis enable via EN/DEN pin here are several possibiliies, like a resisor divider from VS o GND, a Zener diode from EN/DEN o VS and also a logic conrol pin (e.g. from a microconroller oupu). Daashee 10 Rev. 1.00
Inernal supply V S V SU V(h) V EN VEN (h) I OUT 100% 80% PO R Figure 4 Power on rese iming diagram Daashee 11 Rev. 1.00
Inernal supply 4.2 Elecrical characerisics inernal supply and EN pin Table 5 Elecrical characerisics: Inernal supply and EN pin T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Curren consumpion, sleep mode Curren consumpion, acive mode (no faul) Curren consumpion during faul condiion riggered from anoher device sharing ERRN bus (all channels deacivaed) Curren consumpion during faul condiion (all channels deacivaed) Supply hresholds Required supply volage for oupu acivaion Required supply volage for oupu deacivaion I S(sleep) 0.1 2 µa 1) V EN = 0 V T J < 85 C V S = 18 V V OUTx = 3.6 V I S(acive) 1.5 3 ma V EN = 5.5 V I IN_SETx = 0 µa T J < 105 C V S = 18 V V OUTx = 3.6 V I S(faul, ERRN) 850 µa V EN = 5.5 V T J < 105 C V S = 18 V V ERRN = 0 V V OUTx = 3.6 V D open I S(faul, OUT) 1.25 ma V EN = 5.5 V T J < 105 C V S = 18 V V OUT1 = 0 V V OUT2 = V OUT3 = 3.6 V D open V SUV(ON) 5.5 V V EN = V S V OUTx = 3 V R IN_SETx = 6.8 kω I OUTx > 50% I OUTx(nom) V SUV(OFF) 4.5 V V EN = V S V OUTx = 3 V R IN_SETx = 6.8 kω I OUTx < 50% P_5.2.1 P_5.2.3 P_5.2.4 P_5.2.16 P_5.2.5 P_5.2.6 Supply volage acivaion V SUV(hys) 200 mv hyseresis: V SUV(ON) - V SUV(OFF) I OUTx(nom) 1) V EN > V EN(h) P_5.2.8 Daashee 12 Rev. 1.00
Inernal supply Table 5 Elecrical characerisics: Inernal supply and EN pin (con d) T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion EN pin EN oupus enable hreshold V EN(h) 1.4 1.65 1.8 V V S = 5.5 V V PS = 2 V R IN_SETx = 6.8 kω I OUTx = 50% I OUTx(nom) P_5.2.9 DEN diagnosis enable V DEN(h) 2.4 2.5 2.8 V V S = 5.5 V P_5.2.11 hreshold DEN diagnosis enable V DEN(hys) 120 mv 1) R IN_SETx = 6.8 kω P_5.2.12 hyseresis EN/DEN pull-down curren I EN/DEN(PD) 60 µa 1) V S > 8 V P_5.2.17 V EN/DEN = 2.8 V EN/DEN pull-down curren I EN/DEN(PD) 110 µa 1) V S > 8 V P_5.2.14 V EN/DEN = 5.5 V EN/DEN pull-down curren I EN/DEN(PD) 350 µa 1) V S > 8 V P_5.2.15 V EN/DEN = V S Timing Power on rese delay ime POR 25 µs 1) V S rising from 0 V o 13.5 V V OUTx = 3.6 V R IN_SETx = 6.8 kω I OUTx = 80% P_5.2.13 1) No subjeced o producion es: specified by design. I OUTx(nom) Daashee 13 Rev. 1.00
Power sages 5 Power sages The hree oupu sages are realized as high-side curren sources wih an oupu curren up o 80mA. During off sae he leakage curren a he oupu sages is minimized in order o preven a slighly glowing LED. The maximum oupu curren is limied by he power dissipaion and used PCB cooling areas. For an operaing oupu curren conrol loop, he supply and oupu volages have o be considered according o he following parameers: Required supply volage for curren conrol V S(CC) Volage drop over hrough he oupu sage during curren conrol V PSx(CC) Required oupu volage for curren conrol V OUTx(CC) 5.1 Proecion The device provides embedded proecive funcions, which are designed o preven IC damage under faul condiions described in his daashee. Faul condiions are considered as ouside normal operaing range. Proecive funcions are no designed for coninuous nor for repeiive operaions. 5.1.1 Thermal proecion A hermal proecion circuiry is inegraed in he device. I is realized by a emperaure monioring of he oupu sages. As soon as he juncion emperaure exceeds he curren reducion emperaure hreshold T J(CRT) he oupu curren can be reduced by he device by reducing he IN_SETx reference volage V IN_SETx(ref). This feaure grealy helps o avoid LEDs flickering during saic oupu overload condiions. Furhermore, i helps o proec he LEDs, which are mouned hermally close o he device, agains overemperaure. If he device emperaure sill increases, he hree oupu currens decrease close o 0 A. As soon as he device cools down he oupu currens rise again. I OUTx V IN _SE Tx T j(crt) T j Figure 5 Noe: Oupu curren reducion a high emperaure (qualiaive diagram) I is assumed ha a configuraion resisor R SET is applied from IN_SET o GND, and no a curren source, o make he proecion effecive. Daashee 14 Rev. 1.00
Power sages 5.1.2 Reverse baery proecion The device has an inegraed reverse baery proecion feaure. This feaure proecs he driver IC iself and, poenially, also conneced LEDs. The oupu reverse curren is limied o I OUTx(REV) by he reverse baery proecion. 5.2 Oupu configuraion via IN_SETx and PWMI pins Oupus curren can be defined via IN_SETx and pins. 5.2.1 IN_SETx pins The IN_SETx pins is aare muliple funcion pins for he oupus curren definiion and inpus conrol. Oupu currens definiion and analog dimming conrol can be done defining accordingly he IN_SETx currens. ref/faul selecion logic IN_SET I IN_SET V IN_SET(ref) I IN_SET(faul) GND Figure 6 IN_SETx pins block diagram 5.2.2 Oupu curren adjusmen via R SET The oupu curren for he channels can be defined connecing a low power resisor (R SETx ) beween he IN_SETx pins and GND. The dimensioning of he resisors can be done using he formula: I = k I = k V / R OUTx IN _ SETx IN _ SETx( ref ) SETx (5.1) The gain facor k x (defined as he raio I OUTx /I IN_SETx ) is graphically described in Figure 7. The curren hrough he R SETx is defined by he resisor iself and he reference volage V IN_SETx(ref), which is applied o he IN_SETx pin when he device is supplied and he channel enabled. Daashee 15 Rev. 1.00
Power sages 5.2.3 Oupu conrol via IN_SETx The IN_SETx pins can be conneced via heir R SETx o he open-drain oupus of a microconroller or o an exernal NMOS ransisor as described in Figure 9. This signal can be used o urn off he relaive oupu sages of he IC. A minimum IN_SETx curren of I IN_SETx(ACT) is required o urn on he oupu sages. This feaure is implemened o preven glowing of LEDs caused by leakage currens on he IN_SETn pins, see again Figure 7 for deails. I OUTx [ma] I OUTx k x = I OUTx / I IN_SETx I IN_SETx(ACT) I IN_SETx I IN_SETx [µa] Figure 7 I OUTx vs I IN_SETx k/k (yp) 105% 100% 95% 33 66 100 150 200 I IN_SET [µa] 267 Figure 8 Typical oupu curren accuracy I OUT / I IN_SET a T J = 25 C Daashee 16 Rev. 1.00
Power sages VS Supply Proecion Microconroller OUT R SET VS EN LITIX Basic+ (*) IN_SET OUT PWMI GND (*) The drawing refers o a generic LITIX BASIC+ device, and does no represen a specific device pinou (only he relevan connecions for microconroller IN_SET conrol are shown) Figure 9 Oupu conrol via IN_SET pin and open-drain microconroller ou (simplified diagram) 5.2.4 IN_SETx pins behavior during device faul managemen If a faul condiion arises on he channel conrolled by he IN_SETx pins, once he D-pin reaches he high level hreshold V D(h), he curren of all he IN_SETx pins is reduced o I IN_SETx(faul), in order o minimise he curren consumpion of he whole device under faul condiion (deailed descripion is in he load diagnosis secion, Chaper 6). 5.2.5 Timing diagrams In he following diagrams (Figure 10, Figure 11) he influences of differen driving inpus on oupu acivaion delays are shown. I IN_SET x I OUTx ON(IN_SET ) OFF (IN _SET ) 100% 90% 10% Figure 10 IN_SET urn on and urn off delay iming diagram Daashee 17 Rev. 1.00
Power sages V PWMI I OUTx ON(PWMI ) OFF (PWMI ) 100% 90% 10% Figure 11 PWMI urn on and urn off iming diagram Daashee 18 Rev. 1.00
Power sages 5.3 Elecrical characerisics power sage Table 6 Elecrical characerisics: Power sage T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Oupu leakage currens I OUTx(leak) 3 µa 1) V ENx = 5.5 V I IN_SETx = 0 µa V OUTx = 2.5 V T J = 85 C P_6.5.1 Oupu leakage currens I OUTx(leak) 7 µa 1) V ENx = 5.5 V I IN_SETx = 0 µa V OUTx = 2.5 V T J = 150 C Reverse oupu currens I OUTx(rev) 3 µa 1) V EN = V s V Sx = -18 V Oupu load: LED wih break down volage < - 0.6 V Oupu curren accuracy Oupu curren accuracy K LTx 279 300 321 1) T J = 25... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 33 µa Oupu curren accuracy K ALLx 267 300 333 1) T J = -40... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 33 µa Oupu curren accuracy K LTx 285 300 315 Oupu curren accuracy K ALLx 279 300 321 1) T J = 25... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 66 µa 1) T J = -40... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 66 µa Oupu curren accuracy K LTx 288 300 312 1) T J = 25... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 200 µa Oupu curren accuracy K ALLx 285 300 315 1) T J = -40... 115 C V S = 8... 18 V V PSx = 2 V I IN_SETx = 200 µa P_6.5.59 P_6.5.2 P_6.5.30 P_6.5.31 P_6.5.32 P_6.5.33 P_6.5.34 P_6.5.35 Daashee 19 Rev. 1.00
Power sages Table 6 Elecrical characerisics: Power sage (con d) T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Required volage drop during curren conrol V PSx(CC) = V S - V OUTx Required volage drop during curren conrol V PSx(CC) = V S - V OUTx Required volage drop during curren conrol V PSx(CC) = V S - V OUTx Required volage drop during curren conrol V PSx(CC) = V S - V OUTx Required supply volage for curren conrol Required oupu volage for curren conrol Curren reducion emperaure hreshold Oupu curren during curren reducion a high emperaure V PSx(CC) 1.0 V 2) V S = 8... 18 V I OUTx > 90% of K x(yp) *I IN_SETx V PSx(CC) 0.65 V 2) V S = 8... 18 V I IN_SETx = 133 µa I OUTx > 90% of K x(yp) *I IN_SETx T J = -40 C V PSx(CC) 0.75 V 2) V S = 8... 18 V I IN_SETx = 133 µa I OUTx > 90% of K x(yp) *I IN_SETx T J = 25 C V PSx(CC) 0.85 V 2) V S = 8... 18V I IN_SETx = 133 µa I OUTx > 90% of K x(yp) *I IN_SETx T J = 150 C P_6.5.36 P_6.5.37 P_6.5.38 P_6.5.39 V S(CC) 5.5 V V EN = 5.5 V V OUTx = 3 V R IN_SETx = 6.8 kω I OUTx > 90% of K x *I IN_SETx P_6.5.40 V OUTx(CC) 1.4 V V S = 8... 18 V P_6.5.41 I OUTx > 90% of K x *I IN_SETx T J(CRT) 140 C 1) P_6.5.44 I OUT(CRT) 85% of ma I OUT(yp) 1) T J = 150 C P_6.5.45 1) No subjeced o producion es: specified by design. 2) In hese es condiions, he parameer K (yp) represens he ypical value of oupu curren accuracy. Daashee 20 Rev. 1.00
Power sages 5.4 Elecrical characerisics IN_SETx and PWMI pins for oupu seings Table 7 Elecrical characerisics: IN_SETx and PWMI pins T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion IN_SETx reference volage V IN_SETx(ref) 1.195 1.22 1.245 V 1) V EN = 5.5 V P_6.6.1 T J = 25 C IN_SETx reference volage V IN_SETx(ref) 1.184 1.22 1.256 V 1) V EN = 5.5 V T J = -40... 115 C P_6.6.17 IN_SETx oupu acivaion curren I IN_SETx(ACT) 15 µa V EN = 5.5 V V PSx = 3 V I OUTx > 50% of K x(yp) *I IN_SETx PWMI low hreshold V PWMI(L) 1.5 1.7 2 V V S = 8 V o 18 V V EN = 5.5 V PWMI high hreshold V PWMI(H) 2.5 2.7 3 V V S = 8 V o 18 V V EN = 5.5 V Timing IN_SETx urn on ime ON(IN_SETx) 20 µs 1)2) V S = 13.5 V V PSx = 4 V I IN_SETx rising from 0 o 180 µa I OUTx = 90% of K x *I IN_SETx IN_SETx urn off ime OFF(IN_SETx) 10 µs 1)2) V S = 13.5 V V PSx = 4 V I IN_SETx falling from 180 o 0 µa I OUTx = 10% of P_6.6.2 P_6.6.6 P_6.6.7 P_6.6.8 P_6.6.9 PWMI urn on ime ON(PWMI) 15 µs K x *I IN_SETx 1)3) V S = 8 V o 18 V V EN = 5.5 V V PWMI falling from 5V o 0 V I OUTx = 90% of K x *I IN_SETx T J = -40... 115 C PWMI urn off ime OFF(PWMI) 10 µs 1)3) V S = 8 V o 18 V V EN = 5.5 V V PWMI = 0 rising from 0 V o 5 V I OUTx = 10% of K x *I IN_SETx T J = -40... 115 C P_6.6.12 P_6.6.13 Daashee 21 Rev. 1.00
Power sages 1) No subjeced o producion es: specified by design. 2) Refer o Figure 10. 3) Refer o Figure 11. Daashee 22 Rev. 1.00
Load diagnosis 6 Load diagnosis 6.1 Error managemen via ERRN and D-pins Several diagnosis feaures are inegraed in he TLD2331-3EP: Open load deecion (OL) for any of he oupu channels OUTx. Shor circui OUTx-GND (SC) for any of he oupu channels OUTx. Single LED Shor deecion (SLS). 6.1.1 ERRN pin ERRN faul no faul + - Oupu conrol V ERRN(h) I ERRN(faul) Figure 12 ERRN pin (block diagram) The device is able o repor a deeced failure in one of is driven loads and reac o a faul deeced by anoher LED driver in he sysem if a shared error nework is implemened (i. e. driving LED chains of he same ligh funcion). This is possible wih he usage of an exernal pull-up resisor, allowing muliple devices o share he open drain diagnosis oupu pin ERRN. All devices sharing he common error nework are capable o deec he faul from any of he channels driven by he LED drivers and, if desired, o swich muliple loads off. Daashee 23 Rev. 1.00
Load diagnosis VS Supply Proecion RERRN VS EN VS EN ERRN ERRN RSET LITIX Basic+ (*) IN_SET PWMI GND OUT Connecion o furher devices RSET LITIX Basic+ (*) IN_SET PWMI GND OUT (*) The drawing refers o a generic LITIX BASIC+ device, and does no represen a specific device pinou (only he relevan connecions are shown) Figure 13 Shared error nework principle beween family devices When one of he channels is deeced o be under faul condiions (for, a leas, a filer ime faul ), he opendrain ERRN pin sinks a pull-down curren I ERRN(faul) oward GND. Therefore an acive low sae can be deeced a ERRN pin when V ERRN < V ERRN(faul) and if his condiion is reached, provided he proper seup of he delay pin D, all he channels are swiched off. Similarly, when he faul is removed, ERRN pin is pu back in high impedance sae, and he channels reacivaion procedure can be compleed once D-pin volage is below he value V D(h), as illusraed in he iming diagrams in his chaper. Daashee 24 Rev. 1.00
Load diagnosis 6.1.2 D-pin I D(faul) ERRN = H ERRN = L CD D ERRN = H ERRN = L + - Ou pu conrol V D(h) I D(PD) Figure 14 D-pin (block diagram). The D-pin is designed for 2 main purposes: To reac o error condiions in LED arrays according o he implemened faul managemen policy, in sysems where muliple LED chains are used for a given ligh funcion. To exend he channels deacivaion delay ime of a value D, adding a small signal capacior from he D- pin o GND. In his way, an unsable or noisy faul condiion may be prevened from swiching off all he channels of a given ligh funcion (i.e. driven by several driver ICs sharing he same error nework). The funcionaliy of he D-pin is shown in he Figure 14 simplified block diagram: If one LED wihin one chain fails in open load condiion or one of he device oupus are shored o GND, he respecive LED chain is off. Differen auomoive applicaions require a complee deacivaion of a ligh funcion, if he desired brighness of he funcion (LED array) can no be achieved due o an inernal error condiion. In normal operaive saus (no faul) a pull-down curren I D(PD) is sunk from he D-pin o GND. If here is a faul condiion (for, a leas, a filer ime faul ) in one of he LED channels driven by he IC or in any of he devices sharing he same ERRN error nework line, a pull-up curren I D(faul) is insead sourced from he D-pin. As a consequence, if a capaciive or open load is applied a his pin, is volage sars rising. When V D(h) is reached a D-pin, all he channels driven by he device are swiched off and if oher devices share he same ERRN and D-pins nodes, all he devices urn heir oupus off. Alernaively, if he D-pin is ied o GND, only he channel ha has been deeced wih a faul is safely deacivaed. Daashee 25 Rev. 1.00
Load diagnosis The capacior value used a he D-pin, C D, ses he delay imes D(se/rese) according o he following equaions: D( se ) = C D V I D D( h) (6.1) D( rese) C = D ( VD( CL) VD( h) I D ) (6.2) Noe: If he device deecs a Single LED Shor failure, he D-pin behavior and he overall faul managemen is slighly differen (allows periodical reries wih load reacivaion, according o DS pin seings oo), as described in Chaper 6.3. 6.2 Open Load (OL) and shor OUTx o GND (SC) The behavior of he device during overload condiions ha lead o an excess of inernal heaing up o overemperaure condiion, is already described in Chaper 5. Open load (OL) and OUTx shored o GND (SC) diagnosis feaures are also inegraed in he TLD2331-3EP. An open load condiion is deeced if he volage drop over one of he oupu sages V PSx is below he hreshold V PSx(OL) a leas for a filer ime faul. A shor o GND condiion is deeced if he volage of one oupu sages V OUTx is below he hreshold V OUTx(SC) a leas for a filer ime faul. 6.2.1 Faul managemen (D-pin open or conneced wih a capacior o GND) Wih D-pin open or conneced wih a capacior o GND configuraion, i is possible o swich off all he channels which share a common error nework, wihou he need of an auxiliary microconroller. For more deails refer also o he iming diagram of Figure 15, Figure 16. If here is an OL or SC condiion on one of he oupus, a pull-up curren I OUT(faul) hen flows ou from he affeced channel, replacing he configured oupu curren (bu limied by he acual load impedance, e.g. reduced o zero wih an ideal open load). Under hese condiions, he ERRN pin sars sinking a curren I ERRN(faul) oward GND and (wih proper dimensioning of he exernal pull-up resisor) reaches a volage level below V ERRN(faul). Afer D(se), he volage V D(h) is reached a D-pin, he IN_SETx goes in a weak pull-down sae wih a curren consumpion I IN_SETx(faul) afer an addiional laency ime IN_SETx(del). The ERRN low volage can also be used as inpu signal for a microconroller o perform he desired diagnosis policy. The OL and SC error condiions are no lached: as soon as he faul condiion is no longer presen (a leas for a filer ime faul ) ERRN goes back o high impedance. When is volage is above V ERRN(faul), he D-pin volage sars decreasing and afer D(rese) goes below (V D(h) - V D(h,hys) ). Then he IN_SETx volages go up o V IN_SETx(ref), again afer a ime IN_SETx(del) : a his poin, he oupu sages are acivaed again. The oal ime beween he faul removal and he IN_SET reacivaion ERR(rese) is exended by an addiional laency which depends on he exernal ERRN pin pull-up and filer circuiry. Daashee 26 Rev. 1.00
Load diagnosis V IN_SET V IN _SET (ref) V ERRN IN _SET (del) IN _SET (del) VER R N(faul) V D V D(h, hys) V D( h) D(se) D(rese) V OUT faul ERR(rese) faul V S V S V PS (O L) V F open load occurs open load disappears Figure 15 Open load condiion iming diagram example (D-pin unconneced or conneced o exernal capacior o GND, V F represens he ypical forward volage of he oupu load) Daashee 27 Rev. 1.00
Load diagnosis V IN_SET V IN _SET (ref) V ERRN IN_SET (del) IN_SET (del) VERRN(faul) V D V D(h, hys) VD (h) D(se) D(rese) V OUT faul ERR(rese) faul V S V F V OUT(SC ) shor circui occurs shor circui disappears Figure 16 Shor circui o GND condiion iming diagram example (D-pin no conneced or conneced o exernal capacior o GND, V Fxyz represens he forward volage of he oupu loads) 6.2.2 Faul managemen (D-pin conneced o GND) Wih D-pin conneced o GND configuraion, i is possible o deacivae only he channel under faul condiions, sill sharing ERRN pin in a common error nework wih oher devices of family. If here is faul condiion on one of he oupus, a pull-up curren I OUT(faul) flows ou from he affeced channel, replacing he configured oupu curren (bu limied by he acual load impedance, e.g. reduced o zero wih an ideal open load). Under faul condiions he ERRN pin sars sinking a curren I ERRN(faul) o ground and he volage level on his pin will drop below V ERRN(faul) if he exernal pull-up resisor is properly dimensioned. The ERRN low volage can also be used as inpu signal for a µc o perform he desired diagnosis policy. Daashee 28 Rev. 1.00
Load diagnosis The faul saus is no lached: as soon as he faul condiion is no longer presen (a leas for a filer ime faul ), ERRN goes back o high impedance and, once is volage is above V ERRN(faul), finally he oupu sages are acivaed again. Examples of open load or shor o GND diagnosis wih D-pin open or conneced o GND are shown in he iming diagrams of Figure 17 and Figure 18. V IN _SE T V IN_SE T(ref) V ERRN V ER RN (faul) V OUT faul faul V S V S V PS (O L) V F open load occurs open load disappears Figure 17 Open load condiion iming diagram example (D-pin conneced o GND, V F represens he forward volage of he oupu load) Daashee 29 Rev. 1.00
Load diagnosis V IN_SET V IN_SET (ref) V ERRN V ER R N( faul) V OUT faul faul V S V F V OUT(SC ) shor circui occurs shor circui disappears Figure 18 Shor circui condiion iming diagram example (D-pin conneced o GND, V F represens he forward volage of he oupu load) 6.3 Single LED Shor deecion, SLS_REF and DS pins An oupu single LED shor circui (SLS) deecion diagnosis feaure is available. This allows an easy deecion of loss of luminous flux in he ligh funcion due o his failure mode, which does no necessarily resul in a condiion similar or equivalen o an open load or shor o GND condiion. To make he SLS error managemen complian wih he majoriy of sysem requiremens, he TLD2331-3EP allows he possibiliy o manage a low curren consumpion mode wih a load reacivaion and rery sraegy (via D and DS pins conneced o exernal capaciors), or wih error deecion via ERRN pin monioring (wih D-pin shored o GND). Daashee 30 Rev. 1.00
Load diagnosis 6.3.1 SLS_REF pin 1/B min(voutx(on)) OUT3 OUT2 OUT1 RSLS_REF SLS_REF I SLS_REF + - V SLS_REF(CL) SLS error managemen sae Machine Oupu conrol Figure 19 SLS_REF pin (block diagram) wih resisor erminaion The SLS_REF pin is designed o generae an accurae and unable reference volage o allow reliable deecion of SLS failure. This reference can be programmed o adap he SLS deecion o he load relaed variables (as number of LED in series, load currens, LED forward volages flucuaion and mismaches, ec.). The pin provides an accurae reference curren I SLS_REF (a replica of I IN_SET2 ) which can be used o generae he desired reference volage wih an exernal low cos precision resisor. The volage V SLS_REF is hen inernally compared wih a fracion of he OUT volage: if he OUT volage is below he minimum expeced value, hen he SLS error managemen sars (see Chaper 6.3.3 for more deailed descripion and reference formulas). Figure 19 shows he basic block diagram of SLS_REF pin. Daashee 31 Rev. 1.00
Load diagnosis 6.3.2 DS pin I DS(PU) V DS(H) CDS DS VDS(CL) - + - + SLS error managemen sae machine V DS(L) I DS(PD) Figure 20 DS pin (block diagram) The DS pin is used o implemen a imer funcion which allows load reacivaion reries during SLS failure. By defaul, when no SLS faul is deeced, a pull-down curren I DS(PD) is sunk from he DS pin o GND. If a SLS faul condiion is verified, a capacior on DS pin allows faul managemen wih minimal curren consumpion of he device for a ime which depends on he capaciive load applied, according o he deailed descripion of Chaper 6.3.4. 6.3.3 SLS faul deecion A single LED anode-cahode shor circui condiion is deeced if he lowes volage beween OUT1, OUT2 and OUT3 is below a fixed muliple B SLS of he volage a SLS_REF pin, according o Equaion (6.3).The volage V SLS_REF can be adjused applying a resisor from SLS_REF o GND, according o Equaion (6.4) and he parameer K SLS_REF (P_7.5.13). min ( V OUT 1, VOUT 2, VOUT 3 ) BSLS VSLS _ REF (6.3) V SLS _ REF = I SLS _ REF R SLS _ REF (6.4) 6.3.4 SLS faul managemen: D and DS pins open or conneced wih capaciors o GND (low power consumpion mode wih rery sraegy) Under his pin configuraion, as described in he ile of his chaper, if here is an SLS condiion he oupus are urned off when he volage level V D(h) is reached a D-pin. Under faul condiion he ERRN pin sars sinking a curren I ERRN(faul) o ground and he volage level on his pin will drop below V ERRN(faul) if he exernal pull-up resisor is properly dimensioned. Afer D(se), he volage V D(h) is reached a D-pin and he IN_SETx pins go ino a weak pull-down sae wih a curren consumpion I IN_SETx(faul), afer an addiional laency ime IN_SETx(del). Daashee 32 Rev. 1.00
Load diagnosis Then (differenly from he managemen of OL and SC deecion) he volage a DS pin also sars rising wih a pull-up curren I DS(PU), unil i reaches he hreshold V DS(H), when i sars discharging wih he curren I DS(PD). Now he DS volage can cross he lower volage hreshold V DS(L) : a his ime a full wai ime cycle SL_WAIT is compleed and he device performs a load reacivaion rery, urning he oupu currens back on. If he SLS faul condiion persiss, a new SL_WAIT cycle is sared. If a he end of one wai cycle he faul is no deeced anymore, he device goes back o normal operaion. The dimensioning of ypical SL_WAIT is ruled by he following equaions. DS( rise) DS( fall) CDS = I C = = V DS( H) DS( PU) DS ( V V ) DS( H ) I DS( PD) + DS( L) + CDS I V DS( H ) DS( PD) SL( wai) DS( rise) DS( fall) IN _ SET ( del) DS ( rise) (6.5) (6.6) (6.7) A graphical descripion is shown in he iming diagram example of Figure 21. Wih his error managemen algorihm, i is possible o deec he SLS faul monioring he device consumpion from he VS line, which remains as low as I S(faul) during he whole wai cycle. V OUT V OUT(yp) SLS faul appears Acive Rery SLS faul disappears Rery + Resar B*V SLS_REF V OUT(SLS) V ERRN faul V ERRN(faul) V D D(se) D(rese) V D(h) V DS V DS(H) SL(wai) V DS(L) IN_SET(del) V IN_SET V IN_SET(ref) IN_SET(del) faul faul Figure 21 Single LED shor csingle LED shor condiion iming diagram example (D pin no conneced or conneced o exernal capacior o GND) 6.3.5 SLS faul managemen: D-pin shored o GND Under D-pin shored o GND configuraion, he oupu affeced by a single LED shor faul is no urned off, differen from an open load or shor circui o GND faul condiion. The poenial on he IN_SETx pins remains Daashee 33 Rev. 1.00
Load diagnosis V IN_SETx(ref), he ERRN pin sars sinking a curren I ERRN(faul) oward GND. Again, he resuling ERRN low volage can be used as inpu signal for a microconroller o perform he desired diagnosis policy. Also he SLS saus is no lached: as soon as he faul condiion is no longer presen (a leas for a filer ime faul ) ERRN goes back o high impedance. An examples of his SLS diagnosis condiion is shown in he iming diagrams of Figure 22. V OUT V OUT(yp) SLS faul appears SLS faul disappears B*V SLS_REF V OUT(SLS) V ERRN faul faul V ERRN(faul) V IN_SET V IN_SET(ref) Figure 22 Single LED shor condiion iming diagram example (D pin shored o GND) 6.4 Elecrical characerisics: Load diagnosis and Overload managemen Table 8 Elecrical Characerisics: Faul managemen T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion IN_SET faul curren I IN_SETx(faul) 10 µa 1) V S > 8 V P_7.5.1 V OUTx = 3.6 V V ERRN = 0 V V IN_SETx = 1 V D open V EN > V DEN(h,max) ERRN faul curren I ERRN(faul) 2 ma 1) V S > 8 V P_7.5.2 V ERRN = 0.8 V Faul condiion V EN > V DEN(h,max) ERRN inpu hreshold V ERRN(h) 0.8 2.0 V 1) V S > 8 V P_7.5.3 OL deecion hreshold V PSx(OL) 0.2 0.4 V V S > 8 V V EN > V DEN(h, max) SC deecion hreshold V OUTx(SC) 0.8 1.35 V V S > 8 V V EN > V DEN(h, max) P_7.5.5 P_7.5.6 Daashee 34 Rev. 1.00
Load diagnosis Table 8 Elecrical Characerisics: Faul managemen (con d) T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Faul deecion curren I OUTx(faul) 50 180 µa V S > 8 V V OUTx = 0 V V EN > V DEN(h, max) D-pin Threshold volage for funcion de-acivaion Threshold hyseresis V D(hys) 100 mv V D(h) 1.4 2 V V S > 8 V V EN = 5.5 V 1) V S > 8 V V EN = 5.5 V V OUTx = V OUTx(OL) Faul pull-up curren I D(faul) 20 35 50 µa V S > 8 V V OUTx = V OUTx(OL) V D = 2 V Pull-down curren I D(PD) 40 60 95 µa V S > 8 V V EN = 5.5 V V D = 1.4 V V ERRN = 2 V V PSx = 3 V No faul condiions Inernal clamp volage V D(CL) 4 6 V V S > 8 V V OUTx = V OUTx(OL) D-pin open SLS_REF pin Relaive pull-up curren, relaed o IN_SET2 I SLS_REF / I INSET2 Oupu aenuaion facor for inernal reference comparison Oupu aenuaion facor for inernal reference comparison Oupu aenuaion facor for inernal reference comparison Oupu aenuaion facor for inernal reference comparison K SLS_REF 0.972 1 1.028 V S > 8 V V SLS_REF = 0.75... 3.25 V I IN_SET2 = 50... 270 µa B SLS 3.77 3.93 4.09 V S > 14.65 V min(v OUTx ) = 13 V B SLS 3.76 3.93 4.10 V S > 8 V min(v OUTx ) = 7 V B SLS 3.75 3.93 4.11 V S > 8 V min(v OUTx ) = 5 V B SLS 3.73 3.93 4.13 V S > 8 V min(v OUTx ) = 3 V P_7.5.7 P_7.5.8 P_7.5.9 P_7.5.10 P_7.5.11 P_7.5.12 P_7.5.13 P_7.5.21 P_7.5.22 P_7.5.23 P_7.5.24 Daashee 35 Rev. 1.00
Load diagnosis Table 8 Elecrical Characerisics: Faul managemen (con d) T J = -40 C o +150 C; V S =5.5 V o 18 V; R IN_SETx = 10 kω; all volages wih respec o GND, posiive curren flowing ino inpu and I/O pins, posiive curren flowing ou from oupu pins (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion SLS sauraion volage hreshold DS pin High hreshold volage (o rigger from pull up o pulldown curren) Low hreshold volage for rery acivaion V SLS_REF(CL) 3.5 6 V V S > 8 V V EN = 5.5 V V PWMI = 0 V SLS_REF open V DS(H) 2.3 2.5 2.7 V V S > 8 V V SLS_REF = 1.5 V V OUT1 = V OUT2 = 7 V V OUT3 = 5 V V DS(L) 0.2 0.3 0.4 V V S > 8 V V SLS_REF = 1.5 V V OUT1 = V OUT2 = 7 V V OUT3 = 5 V Pull-up curren I DS(PU) 25 35 50 µa V S > 8 V V SLS_REF = 1.5 V V OUT1 = V OUT2 = 7 V V OUT3 = 5 V Pull-down curren I DS(PD) 300 500 750 µa V S > 8 V V EN = 5.5 V V DS = 0.4 V V ERRN = 2 V V PSx = 3 V No faul condiions Timing Faul o ERRN acivaion delay Faul appearance/removal o IN_SET deacivaion/acivaion delay 1) No subjeced o producion es: specified by design. faul 40 150 µs 1) V S > 8 V V OUTx rising from 5V o V S V EN > V DEN(h, max) IN_SET(del) 10 µs 1) V S > 8 V OUT open D rising from 0 V o 5V V EN > V DEN(h, max) P_7.5.14 P_7.5.15 P_7.5.16 P_7.5.17 P_7.5.18 P_7.5.19 P_7.5.20 Daashee 36 Rev. 1.00
Applicaion informaion 7 Applicaion informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. VS Supply Proecion COUT* CVS* R SET1 R SET2 R SET3 COUT* COUT* VS D DS EN/DEN ERRN RERRN STATUS ENABLE Microconroller PWM_OUT1 PWM_OUT2 PWM_OUT3 TLD2331-3EP IN_SET1 IN_SET2 IN_SET3 PWMI GND SLS_REF RSLS_REF OUT1 OUT2 OUT3 * For EMI improvemen, if required (e.g. 4,7 or 10nF) Figure 23 Applicaion diagram example Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion. Daashee 37 Rev. 1.00
Package ouline 8 Package ouline Figure 24 PG-TSDSO-14 Green produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). Furher informaion on packages hps://www.infineon.com/packages Daashee 38 Rev. 1.00
Revision Hisory 9 Revision Hisory Revision Dae Changes 1.00 Iniial daashee creaed Daashee 39 Rev. 1.00
Trademarks All referenced produc or service names and rademarks are he propery of heir respecive owners. Ediion Published by Infineon Technologies AG 81726 Munich, Germany 2018 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? Email: erraum@infineon.com Documen reference TLD2331-3EP IMPORTANT NOTICE The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics ("Beschaffenheisgaranie"). Wih respec o any examples, hins or any ypical values saed herein and/or any informaion regarding he applicaion of he produc, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. In addiion, any informaion given in his documen is subjec o cusomer's compliance wih is obligaions saed in his documen and any applicable legal requiremens, norms and sandards concerning cusomer's producs and any use of he produc of Infineon Technologies in cusomer's applicaions. The daa conained in his documen is exclusively inended for echnically rained saff. I is he responsibiliy of cusomer's echnical deparmens o evaluae he suiabiliy of he produc for he inended applicaion and he compleeness of he produc informaion given in his documen wih respec o such applicaion. For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). WARNINGS Due o echnical requiremens producs may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies office. Excep as oherwise explicily approved by Infineon Technologies in a wrien documen signed by auhorized represenaives of Infineon Technologies, Infineon Technologies producs may no be used in any applicaions where a failure of he produc or any consequences of he use hereof can reasonably be expeced o resul in personal injury.