2017 IEEE 67th Electronic Components and Technology Conference Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package Zhaohui Chen, Faxing Che, Mian Zhi Ding, David Soon Wee Ho, Tai Chong Chai, Vempati Srinivasa Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2 Fusionnopolis Way, #08-02, Innovis, Singapore, 138634 Email: chenz@ime.a-star.edu.sg Abstract Reliability of the 20 mm 20 mm RDL-first fan-out wafer level package (FOWLP) on bottom and 8 mm 8 mm wafer level chip scale package (WLCSP) on top for Package on Package (PoP) test vehicle under drop impact loading was validated by the experimental testing in this paper. The results show that the built up PoP test vehicle can 30 times of drop impact test and some samples can 200 times of drop impact test with the loading of 1500 G. Failure mechanisms of Cu pad peeling off, cracking of dielectrics and Cu trace of the bottom RDL-first-FOWLP and cracking on package corner solder joints of top WLCSP were identified by cross section observation. The peeling stress level on the critical solder joint and dielectrics were studied by nonlinear dynamic drop test simulation. Keywords-RDL-first-FOWLP, Package on Package (PoP), Drop Impact Test, Failure Analysis, FEA I. INTRODUCTION Fan-out wafer level package (FOWLP) can provide good solutions for the system in package (SiP) with different functional chips such as logic chip, memory, sensor and ive components [1-4]. RDL-first process flow is developed recently for the FOWLP. RDL-first process flow is as followed. RDL is firstly fabricated on a supporting glass wafer. The temporary adhesive layer was used between RDL and glass wafer for better release of RDL. Different size of chips can be assembled on bonding pad of RDL layer with micro solder bumps by flip chip bonding. Compression molding process is done after die attach. Moldable underfill with fine filler can be used for filling the gaps between the micro bumps. RDL-first-FOWLP process flow has the advantage of avoiding the die shift issue during the molding process. It also can help to reduce wafer level warpage with supporting glass wafer. Reliability for RDL-first-FOWLP under drop test loading, especially for large package size, is the concern for mobile applications. With the highly acceleration loading conditions, crack and delamination failures might be induced to solder joint and also the dielectrics. In this paper, drop impact reliability for the package on package (PoP) test vehicle with the RDL-fist-FOWLP on bottom and wafer level chip scale package (WLCSP) on top was tested. The dimensions of bottom RDL-first-FOWLP package are 20 mm 20 mm 0.2 mm. The dimensions of top WLCSP are 8 mm 8 mm 0.2 mm. RDL-first-FOWLP Drop impact reliability tests for the RDL-first-FOWLP PoP test vehicle were assessed with the loading of 1500 G/0.5 ms according to the standard of JESD22-B111. Daisy chains were designed on the critical interconnections to monitor the resistance during drop impact testing. Failure mechanisms were identified by cross section observation. The stresses on the solder joints and dielectrics layer were simulated with nonlinear dynamic drop impact model with explicit algorism. II. RDL-FIRST-FOWLP POP TEST VEHICLE RDL-first-FOWLP PoP test vehicle is schematized in Figure 1. Three different sizes of dies were embedded in the bottom RDL-first-FOWLP. The sizes of the three dies are 9 mm 8 mm, 5 mm 4 mm and 3 mm 2 mm, respectively, as listed in Table I. The locations of three embedded dies for the bottom RDL-first-FOWLP and top WLCSP are shown as Figure 1 (b). Front-side RDL of RDL-first-FOWLP was fabricated on supporting glass wafer firstly. Three different pitches of 125 μm, 80 μm and 60 μm Cu pillar/solder microbump were used for the interconnections between the three chips and front side RDL of the bottom RDL-first-FOWLP. The height of micro-bumps including solder and copper pillar is controlled as 50 μm. Compression molding process was adopted to reconstruct molded wafer after flip chip bonding. Grinding and polishing process was conducted on the molded wafer to achieve 200 μm thickness of bottom package. Back side RDL was fabricated on the back side of the bottom package. 2 mil diameter vertical Cu wires embedded in the bottom package were used for connecting the front side and back side RDLs. The thicknesses of front side RDL and back side RDL are 24 μm and 12 μm, respectively. The I/O numbers of bottom RDL-first-FOWLP and top WLCSP are 2400 and 361, respectively. Solder joints (SAC305) with 400 μm pitch and 250 μm diameter were used for both bottom RDL-first-FOWLP and top WLCSP. Figure 2 shows RDL-first-FOWLP PoP test vehicle after fabrication. The bottom RDL-first-FOWLP after solder ball drop is exhibited in Figure 2 (a). Top WLCSP after solder ball drop is illustrated in Figure 2 (b). Figure 2 (c) is PoP test vehicle after stacking WLCSP on the RDL-first- FOWLP and PCB with thermal compression bonding. 2377-5726/17 $31.00 2017 IEEE DOI 10.1109/ECTC.2017.201 1196
(a) Schematic of RDL-first-FOWLP PoP. (b) Top WLCSP after solder balls drop. (c) PoP test vehicle after stacking WLCSP on the RDL-first- FOWLP and PCB with thermal compression bonding. Figure 2. RDL-first-FOWLP PoP test vehicle after fabrication: (a) Bottom RDL-first-FOWLP after solder balls drop; (b) Top WLCSP after solder balls drop; (c) PoP test vehicle after stacking WLCSP on the RDL-first-FOWLP and PCB with thermal compression bonding. (b) Location of embedded dies in bottom RDL-first- FOWLP and WLCSP. Figure 1. Schematic of RDL-first-FOWLP PoP test vehicle: (a) RDL-first-FOWLP PoP schematic; (b) Location of embedded dies in bottom RDL-first-FOWLP and WLCSP. TABLE I. DIMENSIONS OF RDL-FIRST-FOWLP POP. Dimensions (mm) Bottom RDL-first-FOWLP 20 mm 20 mm 0.4 mm Top WLCSP Die 1 embedded in bottom RDL-first-FOWLP Die 2 embedded in bottom RDL-first-FOWLP Die 3 embedded in bottom RDL-first-FOWLP Solder joint pitch Solder joint diameter 8 mm 8 mm 0.2 mm 8 mm 9 mm 4 mm 5 mm 2 mm 3 mm 0.4 mm 0.25 mm (a) Bottom RDL-first-FOWLP after solder balls drop. 1197
III. DROP TEST SIMULATION MODEL AND RESULTS Dynamic drop test simulation and analysis results were descripted in this section. The peeling stress level on critical solder joints and dielectrics layers was investigated numerically. The size of drop test board is 131 mm 77 mm 1 mm as required by JESD22-B111. Due to the large size with 20 mm 20 mm of bottom RDL-first-FOWLP, the PCB can only accommodate five RDL-first-FOWLP PoPs. With the symmetry of the structure, one quarter simulation model was established in order to reduce complexity of the simulation task, as illustrated in Figure 3. The RDL-first- FOWLP PoP located at the PCB center was considered in the simulation model. Global and local technique was used for modeling to simplify the simulation task. Fine elements meshes were used for the critical solder joints and with detail features of the structure. The other solder joints were simplified with block structure and meshed with coarse element. The element type for the simulation model is selected as C3D8. For RDL-first-FOWLP PoP test vehicle, 9 9 solder joints array at the corner of bottom RDL-first- FOWLP and 3 3 solder joints array at the corner of top WLCSP were considered as the local model as shown in Figure 3. Tie was applied for the interaction constrains between the global model and local model. was directly applied on the supporting holes at the corners of PCB. The initial velocity in Z direction of -4.77 m/s was applied on whole model. Abaqus with capability of dynamic explicit method was used for the drop test simulation. The material properties with consideration of the anisotropic behavior of PCB and the rate dependent behavior of solder [6] for drop test simulation were listed in Table II. TABLE II. Materials Density Elastic Modulus MATERIAL PROPERTIES FOR DYNAMIC DROP TEST SIMULATION. Poisson s Ratio Yield Stress Kg/m 3 (GPa) (MPa) Silicon 2329 131 0.28 - Copper 8950 117 0.35 120 Dielectrics 2200 2.2 0.35 - PCB 2200 25 in x, y 11 in z 0.11 in x, y 0.39 in z Solder 1300 2.4 0.32 - Mask SnAgCu 7390 41.7 0.35 Rate dependent [6] EMC 2000 18 0.35 - Figure 4 indicates deformation of RDL-first-FOWLP PoP at PCB center under drop impact loading. From the side view of deformation, it can be predicted that the critical solder joints were located at the package corner of bottom RDL-first-FOWLP and the package corner of top WLCSP due to large bending deformation of PCB. The peeling stress σ 33 contour of 9 9 solder joints array at the corner of bottom RDL-first-FOWLP is illustrated in Figure 5. Due to bending effects, higher peeling stress was induced to the solder joint at package corner. Maximum peeling stress σ 33 on the solder joints the package corner of the bottom RDL-first-FOWLP is 229 MPa. The peeling stress on the solder joint at PCB side is higher than that at package side. - Figure 3. 1/4 drop impact simulation model for the RDLfirst-FOWLP PoP with global/local simulation method. The input-g method was developed and widely used for the dynamic drop impact test simulation [5]. With the input- G simulation technique, the acceleration of 1500 g/0.5 ms 1198
Figure 4. Deformation of at RDL-first-FOWLP PoP at the center of PCB due to bending effects. Figure 5. Peeling stress σ 33 of 9 9 solder joints array at the corner of bottom RDL-first-FOWLP. 1199
Figure 6. Peeling stress σ 33 on the dielectrics at the corner of bottom RDL-first-FOWLP. Figure 6 shows peeling stress σ 33 contour on the dielectrics at the corner of bottom RDL-first-FOWLP. The maximum peeling stress σ 33 induced to the dielectrics is about 104 MPa. The critical location is under the Cu pad at package corner. Delamination may be induced to the interface due to highly peeling stress. Figure 7 shows the peeling stress σ 33 contour of 3 3 solder joints array at the corner of top WLCSP. Due to the bending effects of PCB and bottom package, as illustrated in Figure 4, the solder joints at package edge of WLCSP suffered high peeling stress. Maximum peeling stress σ 33 induced to solder joints at the package edge WLCSP is about 253 MPa. The critical location for the solder joint is on the RDL side. Figure 7. Peeling stress σ 33 of 3 3 solder joints array at the corner of top WLCSP. IV. DROP TESTING AND FAILURE MECHANISM ANALYSIS RDL-first-FOWLP PoP test vehicle was mounted on the PCB for drop impact test as shown in Figure 8. Locations of the packages mounted on the PCB were defined as U1 to U5 with U3 at package center. No underfill was adopted for the RDL-first-FOWLP PoP test vehicle. During the drop impact testing, the PCB with five packages was installed on the drop tester table with supporting bolts at four corners. A half sine shock pulse loading was applied with the condition of 1500 g/0.5 ms. Resistance of the designed daisy chains was monitored during the drop testing. 1200
Figure 8. RDL-first-FOWLP PoP test vehicles mounted on the PCB. Table III shows test results of RDL-first-FOWLP PoP test vehicle on three PCB for 200 drops test. The testing results shows that all the samples can 30 times of drop test as required for mobile applications. Some packages can 200 times of drop test. By these drop impact tests, the reliability of RDL-first-FOWLP PoP test vehicle was validated. adhesion of the interface. From the picture, it can be seen that no failure happened to vertical Cu wire interconnection under drop impact loading. Cross section along the edge of bottom RDL-first- FOWLP was also conducted. Figure 10 shows the cross section SEM picture. It is can be observed that Cu pad was peeled off from the dielectrics layer. Crack was induced to dielectrics layer at the Cu pad edge. Large deformation also happened to the Cu pad due to peeling effects. Delamination induced to the interface of Cu pad/dielectrics was also caused by highly peeling stress and poor adhesion of the interface. Delamination happened to the interface of Cu pad /dielectrics and the interface of dielectrics/ EMC causing the critical issues to the drop impact reliability of FOWLP. The adhesion of the interfaces needs to be enhanced to withstand the peeling stress causing by bending effects of drop impact. TABLE III. VEHICEL. DROP TEST RESULTS OF RDL-FIRST-FOWLP POP TEST Location Sample 1 Sample 2 Sample 3 200 drops 170 drops U1 U2 200 drops 200 drops U3 50 drops 50 drops U4 110 drops 50 drops U5 170 drops Some early failures were found for RDL-first-FOWLP PoP under drop impact loading. Cross section was conducted by the method of mechanical grinding followed by fine polishing. The mechanisms of the early failed daisy chains are shown in Figures 9, 10 and 11. Cross section along the corner of bottom RDL-first- FOWLP was conducted. SEM picture of cross section along the failed solder joint at the corner of bottom RDL-first- FOWLP is illustrated in Figure 9. Delamination induced to the interface of Cu pad/dielectrics layer can be seen from the picture. The Cu pad and trace was peeled off. Crack happened to Cu trace. Delamination induced to the interface of Cu pad/dielectrics is due to highly peeling stress and poor Figure 9. Failure mechanisms of critical solder joint at the corner of bottom RDL-first-FOWLP with details of Cu pad peeling and Cu trace cracking. 1201
Figure 11. Failure mechanisms of the package edge solder joints of top WLCSP with details of cracking on RDL side. Figure 11 shows failure mechanisms of the failed solder joints at the package edge of top WLCSP. It can be found that cracks happened to solder joints on back RDL side under 1500 G drop test loading. It can also be found that insufficient wetting happened between the solder joints and the UBM on back RDL side. The cracks can happpen to the solder joints more easily with the insufficient wetting under the highly peeling stress as shown in Figure 7. Figure 10. Failure mechanisms of critical solder joint at the edge of bottom RDL-first-FOWLP with details of Cu pad peeling and dielectrics cracking. V. CONCLUSIONS In this paper, reliability of 20 mm 20 mm RDL-first- FOWLP on bottom and 8 mm 8 mm WLCSP on top for PoP test vehicle under drop impact loading was validated by the experimental testing. The failure mechanisms were identified by cross section observation. Some important conclusions are summarized as following: (1) Drop impact reliability of 20 mm 20 mm RDL-first- FOWLP PoP test vehicle was validated by 1500 G/0.5 ms drop impact tests. The samples can 30 times of drop test and some packages can 200 times of drop test. (2) Failure mechanisms of the early failed samples were identified to be Cu pad peeling off, cracking of dielectrics and Cu trace of the bottom RDL-first- FOWLP and cracks on the edge solder joint of top WLCSP. (3) Delamination was induced on the interface of Cu pad/dielectrics by highly peeling stress due to bending effects. The adhesion of Cu pad to dielectrics layer need to be enhanced to avoid happening of delamination. 1202
(4) Highly peeling stress was induced to the package edge/corner solder joints of top WLCSP due to the bending effects of PCB and bottom package. ACKNOWLEDGMENT The supports from the project High Density Fan-Out Wafer Level Packaging (HD-FOWLP) Consortium are greatly appreciated in terms of participation in discussions and encouragement from members. REFERENCES [1] M. Brunnbauer. T. Meyer. G. Ofner. K. Mueller. R. Hagen, Embedded Wafer Level Ball Grid Array (ewlb), 33rd International Electronics Manufacturing Teclmology Conference, 2008, pp. 1-6. [2] B. Keser, C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W.Lytle, D. Mitchell, R.Wenzel, The Redistributed Chip Package: A Breakthrough for Advanced Packaging, Electronic Components and Technology Conference, 2007, pp. 286-291. [3] K. Liu, B.Adams, and S.W. Yoon, Integration Through Wafer-Level Packaging Approach, 2015 International Wafer Level Packaging Conference (IWLPC) Proceedings, 2015. [4] J. H. Lau, Patent Issues Of Embedded Fan-Out Wafer/Panel Level Packaging, Semiconductor Technology International Conference (CSTIC) China, 2016. [5] J.E. Luan and T. Y. Tee, Novel Board Level Drop Test Simulation using Implicit Transient Analysis with Input-G Method, Electronics Packaging Technology Conference, 2004, pp. 671-677. [6] E.H. Wong, C.S. Selvanayagam, S.K.W. Seah, W.D. van Driel, J.F.J.M. Caers, X.J. Zhao, N. Owens, L.C. Tan, D.R. Frear, M. Leoni, Y.S. Lai, and C.L. Yeh, Stress strain characteristics of Tin based solder alloys for drop impact modeling, J. of Electron. Mater., vol. 37, no. 6, pp. 829-836, 2008. 1203