EE5 ection 8 Arithmetic ircuits Fall 2 Arithmetic ircuits Excellent Examples of ombinational Logic Design Time vs. pace Trade-offs Doing things fast may require more logic and thus more space Example: carry lookahead logic Arithmetic and Logic Units General-purpose building blocks ritical components of processor datapaths Used within most computer instructions EE5 - Fall 2-2
Number ystems Representation of positive numbers is the same in most systems Major differences are in how negative numbers are represented Representation of negative numbers come in three major schemes ign and magnitude s complement 2s complement Assumptions We'll assume a bit machine word 6 different values can be represented Roughly half are positive, half are negative EE5 - Fall 2-3 ign and Magnitude One bit dedicate to sign (positive or negative) sign: = positive (or zero), = negative Rest represent the absolute value or magnitude three low order bits: () thru 7 () Range for n bits +/ 2n (two representations for ) umbersome addition/subtraction must compare magnitudes to determine sign of result 6 + 5 +2 +3 3 = + = 7 2 + + +5 +6 +7 EE5 - Fall 2 -
s omplement If N is a positive number, then the negative of N ( its s complement or N' ) is N' = (2 n ) N Example: s complement of 7 2 = = 2 = 7 = = 7 in s complement form hortcut: simply compute bit-wise complement ( -> ) EE5 - Fall 2-5 s complement (cont'd) ubtraction implemented by s complement and then addition Two representations of auses some complexities in addition High-order bit can act as sign bit = + = + + 2 +2 3 +3 5 6 7 + +5 +6 +7 EE5 - Fall 2-6
= + = 2s omplement s complement with negative numbers shifted one position clockwise Only one representation for One more negative number than positive number High-order bit can act as sign bit 2 3 5 6 7 8 + + +2 +3 + +5 +6 +7 EE5 - Fall 2-7 2s complement (cont d) If N is a positive number, then the negative of N ( its 2s complement or N* ) is N* = 2n N Example: 2s complement of 7 subtract 2 = 7 = = repr. of 7 Example: 2s complement of 7 subtract 2 = 7 = = repr. of 7 hortcut: 2s complement = bit-wise complement + -> + -> (representation of -7) -> + -> (representation of 7) EE5 - Fall 2-8
Addition / ubtraction imple Addition and ubtraction imple scheme makes 2s complement the virtually unanimous choice for integer number systems in computers + 3 + ( 3) 7 7 3 + 3 EE5 - Fall 2-9 Why an the arry-out be Ignored? an't ignore it completely Needed to check for overflow (see next two slides) When there is no overflow, carry-out may be true but can be ignored M + N when N > M: M* + N = (2 n M) + N = 2 n + (N M) ignoring carry-out is just like subtracting 2 n M + N where N + M 2 n ( M) + ( N) = M* + N* = (2 n M) + (2 n N) = 2 n (M + N) + 2 n ignoring the carry, it is just the 2s complement representation for (M + N) EE5 - Fall 2 -
2 3 5 Overflow in 2s omplement Overflow conditions Add two positive numbers to get a negative number Add two negative numbers to get a positive number 6 7 8 + + +2 +3 + +5 +6 +7 2 3 5 + 3 = 8 7 2 = +7 5 6 7 8 + + +2 +3 + +5 +6 +7 EE5 - Fall 2 - Overflow onditions Overflow when carry into sign bit position is not equal to carry-out 5 3 8 overflow 7 2 7 overflow 5 2 7 no overflow 3 5 8 no overflow EE5 - Fall 2-2
ircuits for Binary Addition Half adder (add 2 -bit numbers) um = Ai' Bi + Ai Bi' = Ai xor Bi out = Ai Bi Full adder (carry-in to cascade for multi-bit adders) um = i xor A xor B out = B i + A i + A B = i (A + B) + A B Ai Bi um out Ai Bi in um out EE5 - Fall 2-3 Full adder implementations tandard approach 6 gates 2ORs, 2ANDs, 2ORs A B in Alternative implementation 5 gates half adder is an OR gate and AND gate 2ORs, 2ANDs, OR A B A B in out = A B + in (A xor B) = A B + B in + A in out A B in um AxorB Half Adder out A B um A xor B xor in Half Adder out in (A xor B) um out EE5 - Fall 2 -
Adder/ubtractor Use an adder to do subtraction thanks to 2s complement representation A B = A + ( B) = A + B' + ontrol signal selects B or 2s complement of B A3 B3B3' A2 B2B2' A BB' A BB' el el el el A B out in um A B out in um A B out in um A B out in um Add' ubtract 3 2 Overflow EE5 - Fall 2-5 ritical Delay Ripple-arry Adders The propagation of carry from low to high order stages A B in @2 @2 stage adder @ A @ B @N in @ A @ B @ @N+ @ out @N+2 A B A2 B2 @3 2 @ 2 @5 3 @6 late arriving signal two gate delays to compute out A3 B3 3 @7 out @8 EE5 - Fall 2-6
Ripple-arry Adders (cont d) ritical delay The propagation of carry from low to high order stages + is the worst case addition arry must propagate through all bits, Valid, 2 Valid 2, 3 Valid 3, Valid T T2 T T6 T8 EE5 - Fall 2-7 arry-lookahead Logic arry generate: Gi = Ai Bi Must generate carry when A = B = arry propagate: Pi = Ai xor Bi arry-in will equal carry-out here um and out can be re-expressed in terms of generate/propagate: i = Ai xor Bi xor i = Pi xor i i+= Ai Bi + Ai i + Bi i = Ai Bi + i (Ai + Bi) = Ai Bi + i (Ai xor Bi) =Gi+iPi EE5 - Fall 2-8
arry-lookahead Logic (cont d) Re-express the carry logic as follows: = G + P 2 = G + P = G + P G + P P 3 = G2 + P2 2 = G2 + P2 G + P2 P G + P2 P P = G3 + P3 3 = G3 + P3 G2 + P3 P2 G + P3 P2 P G + P3 P2 P P Each of the carry equations can be implemented with two-level logic All inputs are now directly derived from data inputs and not from intermediate carries this allows computation of all sum outputs to proceed in parallel EE5 - Fall 2-9 arry-lookahead Implementation Adder with propagate and generate outputs Ai Bi i Pi @ gate delay i @ 2 gate delays Gi @ gate delay increasingly complex logic for carries P G P P G P G 2 P P P2 G P P2 G P2 G2 P P P2 P3 G P P2 3 P3 G P2 P3 G2 P3 G3 EE5 - Fall 2-2
arry-lookahead Implementation arry-lookahead logic generates individual carries ums computed much more quickly in parallel However, cost of carry logic increases with more stages A B in A B A2 B2 @2 @2 A3 B3 @3 2 @ 2 @5 3 @6 3 @7 out @8 in A B @3 A B 2 @3 A2 B2 3 @3 @2 @ 2 @ A3 3 @ B3 @3 @3 EE5 - Fall 2-2 ascaded arry-lookahead Logic arry-lookahead adder four-bit adders with internal carry lookahead econd level carry lookahead unit extends lookahead to 6 bits A[5-2]B[5-2] -bit Adder 2 P G A[-8] B[-8] -bit Adder P G 8 A[7-] B[7-] -bit Adder P G A[3-] B[3-] -bit Adder P G @ [5-2] @8 @2 @3 [-8] @8 @5 @2 @3 [7-] @7 @5 @2 @3 [3-] @ @ @2 @3 6 @ P3 G3 3 P2 G2 2 P G Lookahead arry Unit P3- G3- @3 @5 P G @ EE5 - Fall 2-22
arry-elect Adder Redundant hardware to make carry calculation go faster ompute two high-order sums in parallel while waiting for carry-in One assuming carry-in is and another assuming carry-in is elect correct result once carry-in is finally computed 8 -bit adder [7:] adder high 8 -bit adder [7:] adder low five 2: mux -Bit Adder [3:] 8 7 6 5 3 2 EE5 - Fall 2-23 Arithmetic Logic Unit Design M =, logical bitwise operations Function Fi = Ai Fi = not Ai Fi = Ai xor Bi Fi = Ai xnor Bi M =, =, arithmetic operations F = A F = not A F = A plus B F = (not A) plus B M =, =, arithmetic operations F = A plus F = (not A) plus F = A plus B plus F = (not A) plus B plus omment input Ai transferred to output complement of Ai transferred to output compute OR of Ai, Bi compute NOR of Ai, Bi input A passed to output complement of A passed to output sum of A and B sum of B and complement of A increment A twos complement of A increment sum of A and B B minus A logical and arithmetic operations not all operations appear useful, but "fall out" of internal logic EE5 - Fall 2-2
Arithmetic Logic Unit Design ample ALU truth table M i Ai EE5 - Fall 2-25 Bi Fi i+ Arithmetic Logic Unit Design ample ALU multi-level discrete gate logic implementation \ \Bi M Bi Ai [35] [33] [3] i [33] [3] [33] M i [3] o M i \o i [3] [33] \o [3] [35] \o \[3] \[35] Fi 2 gates EE5 - Fall 2-26
Arithmetic Logic Unit Design ample ALU clever multi-level implementation A Bi Ai 2 M A2 i first-level gates use to complement Ai = causes gate to pass Ai = causes gate to pass Ai' use to block Bi = causes gate A to make Bi go forward as (don't want Bi for operations with just A) = causes gate A to pass Bi use M to block i M = causes gate A2 to make i go forward as (don't want i for logical operations) M = causes gate A2 to pass i A3 O A 3 other gates for M= (logical operations, i is ignored) Fi = Bi xor ( xor Ai) = '' ( Ai ) + ' ( Ai' ) + ' ( Ai Bi' + Ai' Bi ) + ( Ai' Bi' + Ai Bi ) for M= (arithmetic operations) Fi = Bi xor ( ( xor Ai ) xor i ) = i+ = i ( xor Ai) + Bi ( ( xor Ai) xor i ) = i+ Fi just a full adder with inputs xor Ai, Bi, and i EE5 - Fall 2-27 BD Addition Decimal digits thru 9 represented as thru in binary Addition: 5 = 3 = = 8 5 = 8 = = 3! Problem when digit sum exceeds 9 olution: add 6 () if sum exceeds 9! 5 = 8 = 6 = = 3 in BD 9 = 7 = = 6 in binary 6 = = 6 in BD EE5 - Fall 2-28
Adder Implementation A 3 B 3 A 2 B 2 A B A B O I O I O I O I in A A2 O I O I out 3 2 Add to sum whenever it exceeds ( or ) EE5 - Fall 2-29 ombinational Multiplier multiplicand multiplier Partial products (3) * () (3) product of 2 -bit numbers is an 8-bit number EE5 - Fall 2-3
Partial Product Accumulation A3 A2 A A B3 B2 B B A2 B A2 B A B A B A3 B A2 B A B A B A3 B2 A2 B2 A B2 A B2 A3 B3 A2 B3 A B3 A B3 7 6 5 3 2 EE5 - Fall 2-3 Partial Product Accumulation A 3 B 3 A 3 B 2 A 2 B 3 A 3 B A 2 B 2 A B 3 A 3 B A 2 B A B 2 A B 3 A 2 B A B A B 2 A B A B A B HA HA HA HA 7 6 5 3 2 Note use of parallel carry-outs to form higher order sums 2 Adders, if full adders, this is 6 gates each = 72 gates 6 gates form the partial products total = 88 gates! EE5 - Fall 2-32
Another Representation um In in Building block: full adder + and Y A O B I out um Out A3 A2 A A B A3 B A2 B A B A B B A3 B A2 B A B A B B2 A3 B2 A2 B2 A B2 A B2 B3 A3 B3 A2 B3 A B3 A B3 P7 P6 P5 P P3 P2 P P x array of building blocks EE5 - Fall 2-33