Xarxes de distribució del senyal de rellotge. Clock skew, jitter, interferència electromagnètica, consum, soroll de conmutació. (transparències generades a partir de la presentació de Jan M. Rabaey, Anantha Chandrakasan,i Borivoje Nikolić en el llibre Digital Integrated Circuits, A design perspective ) 1
When synchronized circuits are employed a clock signal must be distributed to all of the clocked storage elements in a clock domain with a minimum of skew and jitter. Whether the clock domain is an entire system spanning many cabinets or a small portion of a chip, clock distribution is a difficult problem. Variations in wire delays and driver delays, a non-uniform and possible time-varying clocl load, and noise all add to the uncertainty of the clock 2
Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 3
Timing Definitions 4
Latch Parameters D Q Clk Clk D PW m t hold T t su Q t c-q t d-q Delays can be different for rising and falling data transitions 5
Register Parameters D Q Clk Clk T D t hold t su Q t c-q Delays can be different for rising and falling data transitions 6
Clock Uncertainties 4 Power Supply Devices 2 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty 7
Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges for 2 given signals; mainly deterministic, t SK Clock jitter Temporal variations in consecutive edges of the same clock signal; random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width Important for level sensitive clocking 8
Clock Skew # of registers Earliest occurrence of Clk edge Nominal δ/2 Latest occurrence of Clk edge Nominal + δ /2 Insertion delay Max Clk skew Clk delay δ 9
Positive and Negative Skew In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q CLK t CLK1 t CLK2 t CLK3 delay (a) Positive skew delay In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q t CLK1 t CLK2 t CLK3 delay delay CLK (b) Negative skew 10
Positive Skew T CLK + δ CLK1 1 δ T CLK 3 CLK2 2 4 δ + t h Launching edge arrives before the receiving edge 11
Negative Skew T CLK + δ CLK1 1 T CLK 3 CLK2 2 δ 4 Receiving edge arrives before the launching edge 12
Timing Constraints In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Minimum cycle time: T - δ = t c-q + t su + t logic Worst case is when receiving edge arrives early (positive δ) 13
Clock Skew and Jitter Clk t SK Clk t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin 14
Timing Constraints In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold + δ Worst case is when receiving edge arrives late Race between data and clock 15
Impact of Jitter 2 T CLK 5 CLK 1 3 4 -t ji tte r t jitter 6 In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational Logic t logic t logic, cd 16
Longest Logic Path in Edge-Triggered Systems Clk T Clk-Q T T LM T SU T JI + δ Latest point of launching Earliest arrival of next cycle 17
Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: T c-q + T LM + T SU < T T JI,1 T JI,2 - δ Minimum cycle time is determined by the maximum delays through the logic T c-q + T LM + T SU + δ + 2 T JI < T Skew can be either positive or negative 18
How to counter Clock Skew? Negative Skew REG φ REG. REG log Out In REG φ φ Positive Skew φ Clock Distribution Data and Clock Routing 19
Sources of Skew and Jitter Sources of Skew and Jitter Clock uncertainty: systematic or random. Clock uncertainty: static or time-varying (1) Clock signal generation (2) Manufacturing device variations (3) Interconnect variations (4) Environmental variations (5) Capacitive coupling (6) Data-dependent clock jitter 20
Clock Distribution H-tree 4x4 processor array CLK Clock is distributed in a tree-like fashion 21
More realistic H-treeH [Restle98] 22
The Grid System Driver GCLK GCLK Driver Driver GCLK No rc-matching Large power Driver GCLK 23
Example: DEC Alpha 21164 (0.5 µm) Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nf (dynamic logic) Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm! 24
21164 Clocking t rise = 0.35ns t cycle = 3.3ns Clock waveform final drivers pre-driver Location of clock driver on die t skew = 150ps 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation 25
26
Clock Skew in Alpha Processor 27
EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS t cycle = 1.67ns t rise = 0.35ns Global clock waveform t skew = 50ps PLL 2 Phase, with multiple conditional buffered clocks 2.8 nf clock load 40 cm final driver width Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking 28
21264 Clocking 29
ps 5 10 15 20 25 30 35 40 45 50 EV6 Clock Results ps 300 305 310 315 320 325 330 335 340 345 GCLK Skew (at Vdd/2 Crossings) GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%) 30
EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains NCLK (Mem Ctrl) + widely dispersed drivers DLL DLL DLL + DLLs compensate static and lowfrequency variation + divides design and verification effort L2L_CLK (L2 Cache) GCLK (CPU Core) PLL L2R_CLK (L2 Cache) - DLL design and verification is added work SYSCLK + tailored clocks 31
Moreover Clock lines are the most active of the lines in a synchronous system. Consequently they are the main factor for electromagnetic interference (EMI), noise coupling and consumption. 32