EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr., due Fr. Apr. 13 5pm. 2
Class Material Last lecture Power Today s lecture Sequential Circuits 3 Sequential Logic 4
Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive feedback charge-based 5 Latch versus Register Latch level-sensitive clock is low hold mode clock is high - transparent Register edge-triggered stores data when clock rises Clk Clk Clk Clk 6
Naming Convention In our book, latch is level sensitive, register is edge-triggered There are many different naming conventions Many books call edge-triggered elements flip-flops 7 Latches Positive Latch Negative Latch In G Out In G Out clk In Out clk In Out Out stable Out follows In Out stable Out follows In 8
Latch-Based esign N latch is transparent when φ = φ P latch is transparent when φ = 1 N Latch Logic P Latch Logic 9 Timing efinitions t su t hold t Register ATA STABLE t t c q ATA STABLE t 1
Characterizing Timing t Clk Clk t C Register t C Latch 11 Maximum Clock Frequency φ FF s LOGIC t p,comb t clk- + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay 12
V 1 o V 5 V 1 o 2 i V 5 V 1 o 2 i Positive Feedback: Bi-Stability V i1 V o1 =V i2 V o2 V o2 =V i1 V i1 V o2 A C B V i1 =V o2 13 Meta-Stability V i2 5V o1 A V i2 5V o1 A C C B B V d i1 5V o2 V d i1 5V o2 Gain should be larger than 1 in the transition region 14
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOS-only) 15 Cross-Coupled Coupled Pairs NOR-based set-reset S S S R R R 1 1 1 1 1 1 Forbidden State The Overpowering Approach 16
Cross-Coupled Coupled NAN Cross-coupled NANs Added clock V S M 2 M 4 R M 6 M 1 M 8 M 3 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell 17 Sizing Issues 2. 3 S (Volts) 1.5 1..5. 2. 2.5 3. W/L 5 and 6 3.5 4. Volts 2 1 W =.5 µ m W =.6 µ m W =.7 µ m W =.8 µ m W =.9 µ m W = 1 µ m.2.4.6.8 1 1.2 1.4 1.6 1.8 2 time (ns) (a) (b) Output voltage dependence on transistor width Transient response 18
Pseudo-Static Latch 19 Mux-Based Latches Negative latch (transparent when = ) Positive latch (transparent when = 1) 1 1 = Clk + Clk In = Clk + Clk In 2
Mux-Based Latch 21 Mux-Based Latch M M NMOS only Non-overlapping clocks 22
Storage Mechanisms Static ynamic 23 Master-Slave (Edge-Triggered) Register Master Slave 1 M 1 M Two opposite latches trigger on edge Also called master-slave latch pair 24
Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 25 Clk- elay 2.5 Volts 1.5.5 t c 2 q(lh) t c 2 q(hl) 2.5.5 1 1.5 2 2.5 time, nsec 26
Setup 3. 2.5 3. 2.5 2. M 2. I 2 2 T 2 Volts 1.5 1. Volts 1.5 1..5 I 2 2 T 2.5 M.. 2.5.2.4.6.8 1 time (nsec) 2.5.2.4.6.8 1 time (nsec) (a) T setup 5.21 nsec (b) T setup 5.2 nsec 27 More Precise Setup Clk t t (a) t 1.5t C 2 t C 2 t Su t 2 C t H (b) 28
Setup-Hold Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 T Setup-1 t= 29 Setup-Hold Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 T Setup-1 t= 3
Setup-Hold Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 T Setup-1 t= 31 Setup-Hold Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP ata Clock T Setup-1 T Setup-1 t= 32
Setup-Hold Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay T Clk- Inv1 CP ata Clock T Setup-1 T Setup-1 t= 33 Setup-Hold Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- Clock ata T Hold-1 T Hold-1 t= 34
Setup-Hold Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- Clock ata T Hold-1 T Hold-1 t= 35 Setup-Hold Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- Clock ata T Hold-1 T Hold-1 t= 36
Setup-Hold Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP Clock T Hold-1 ata T Hold-1 t= 37 Setup-Hold Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk- elay Inv1 CP Clock T Hold-1 ata T Hold-1 t= 38
Reduced Clock Load Master-Slave Register T 1 I 1 T 2 I 3 I 2 I 4 39 Avoiding Clock Overlap A X B (a) Schematic diagram (b) Overlapping clock pairs 4
Next Lecture Sequential logic (cntd) 41