LH2256 NMOS 256K (256K ) Dynamic RAM FEATURES 262,44 bit organization Access times: 00/20/50 ns (MAX.) Cycle times: 200/230/260 ns (MIN.) Page mode operation Power supply: +5 V ± 0% Power consumption: Operating: 467.5/440/385 mw (MAX.) Standby: 27.5 mw (MAX.) TTL compatible I/O Built-in gated function Separate I/O allows Early-Write action Available for read modify write, only refresh, hidden refresh, before refresh 256 refresh cycle (refreshing time 4 ms) Built-in high output bias generator circuit DESCRIPTION The LH2256 is a 262,44 word bit dynamic RAM fabricated using N-channel 2-layer polysilicon gate process technology. With mulitiplexed address inputs and standard 6-pin DIP/ZIP packages, it is easy to comprise memory systems with high speed, low power consumption and large memory capacity. The LH2256 operates on a single +5 V power supply. The built-in high output substrate bias generator circuit eliminates sensitivity to undershoot on the input signals. PIN CONNECTIONS 6-PIN DIP 6-PIN ZIP A 8 D IN A 0 A 2 A V CC 2 3 4 5 6 7 8 6 5 4 3 2 0 9 V SS A 6 A 3 A 4 A 5 A 7 TOP VIEW Packages: 6-pin, 300-mil DIP 6-pin, 325-mil ZIP A 6 3 A 8 5 7 A 0 9 A A 7 3 A 4 5 2 4 V SS 6 D IN 8 0 A 2 2 V CC 4 A 5 6 A 3 Figure. Pin Connections for DIP and ZIP Packages 2256-2-
LH2256 NMOS 256K (256K ) Dynamic RAM 4 5 CLOCK GENERATOR CLOCK GENERATOR 2 INPUT 5 6 7 9 0 2 3 COLUMN BUFFER ROW BUFFER REFRESH COUNTER EXT/INT MUX. ROW DECODER COLUMN DECODER SENSE AMPLIFIERS MEMORY ARRAY WRITE CLOCKS I/O SELECTOR DATA IN BUFFER DATA OUT BUFFER 3 4 2 D IN V CC 8 V SS 6 V BB GENERATOR NOTE: Pin numbers apply to 6-pin DIP. 2256-2 Figure 2. LH2256 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME Address input Row address strobe Column address strobe Write enable SIGNAL PIN NAME D IN Data input Data output V CC Power supply (+5 V) V SS Power supply (0 V) ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage V T -.0 to 7.0 V Output short-circuit current I O 50 ma Power consumption P D.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +50 C NOTE:. Referenced to V SS 2-2
NMOS 256K (256K ) Dynamic RAM LH2256 RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70 C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Supply voltage Input voltage NOTE:. Referenced to V SS V CC 4.5 5.0 5.5 V SS 0 0 0 2.4 6.5 -.0 0.8 V V CAPACITANCE (V CC = 5 V ± 0%, T A = 0 to +70 C, f = MHz) PARAMETER SYMBOL MIN. TYPICAL MAX. UNIT, Input capacitance D IN, C IN 7 pf, C IN2 0 pf Output capacitance C OUT 8 pf DC CHARACTERISTICS (V CC = 5 V ± 0%, T A = 0 to +70 C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE 65 LH2256-0 85 Average supply current I in normal operation LH2256-2 CC 80 ma, 2 LH2256-5 70 Average supply current in standby mode I CC2 5.0 ma LH2256-0 65 Average supply current in only refresh time LH2256-2 I CC3 60 ma, 2 LH2256-5 55 LH2256-0 50 Average supply current I in page mode LH2256-2 CC4 45 ma, 2 LH2256-5 40 before LH2256-0 average supply current LH2256-2 I CC5 60 ma, 2 in refresh cycle LH2256-5 55 Input leakage current 0 V V IN 6.5 V 0 V on all other pins I I(L) -0 0 µa Output leakage current 0 V V OUT 6.5 V Output in high-impedance state I O(L) -0 0 µa Output High voltage I OUT = -5 ma 2.4 V Output Low voltage I OUT = 4.2 ma 0.4 V NOTES:. The output pins are in high-impedance state. 2. I CC, I CC3, I CC4, and I CC5 depend on the cycle time. 2-3
LH2256 NMOS 256K (256K ) Dynamic RAM AC CHARACTERISTICS, 2, 3 (V CC = 5 V ± 0%, T A = 0 to 70 C) PARAMETER SYMBOL LH2256-0 LH2256-2 LH2256-5 MIN. MAX. MIN. MAX. MIN. MAX. UNIT NOTE Random read/write cycle time t RC 200 230 260 ns Read write cycle time t RWC 240 275 30 ns Access time from t RAC 00 20 50 ns 4, 6 Access time from tcac 50 60 75 ns 5, 6 Output turn-off delay time t OFF 0 30 0 35 0 40 ns Rise and fall time tt 3 35 3 35 3 35 ns 3 precharge time trp 90 00 00 ns pulse width t 00 0,000 20 0,000 50 0,000 ns hold time t RSH 50 60 75 ns precharge time t CPN 25 30 35 ns pulse width t 50 0,000 60 0,000 75 0,000 ns hold time tcsh 00 20 50 ns hold time ( before ) tfch 00 20 50 ns set up time ( before ) t FCS 20 25 30 ns / delay time trcd 20 50 25 60 30 75 ns 7, 8 / precharge time tcrp 20 25 30 ns Row address setup time tasr 0 0 0 ns Row address hold time trah 0 5 20 ns Column address setup time tasc 0 0 0 ns Column address hold time 25 25 45 ns Column address hold time from t AR 75 95 20 ns Read command setup time t RCS 0 0 0 ns Read command hold time t RCH 0 0 0 ns Read command hold time from t RRH 20 20 20 ns Write command setup time t WC S 0 0 0 ns 0 Write command hold time t WCH 35 40 45 ns Write command hold time from twcr 85 00 20 ns Write command pulse width twp 35 40 45 ns Write command lead time trwl 35 40 45 ns Write command lead time tcwl 35 40 45 ns write command delay time trwd 95 20 50 ns write command delay time tcwd 45 60 75 ns Data input setup time tds 0 0 0 ns 9 Data input hold time t DH 30 30 35 ns 9 Data input hold time from t DHR 80 90 0 ns Refresh time t REF 4 4 4 ms precharge hold time C 0 0 0 ns NOTES:. For proper operation, at least 500 µs of pause time after power-on followed by several initialization cycles (usually 8 ordinary refresh cycles) should be given. 2. AC characteristics assume t T = 5 ns. 3. Timing measurements are referenced to (MIN.) and (MAX.). (t T refers to the transition time between and.) 4. Only when t RCD t RCD (MAX.). If t RCD > t RCD (MAX.), t RAC will increase by (t RCD - t RCD (MAX.)) 5. When t RCD t RCD (MAX.). 6. Load condition for 2TTL + 00 pf. 7. t RCD (MAX.) is the maximum point for t RCD where t RAC (MAX.) is ensured, and does not represent a limit of operation. If t RCD (MAX.) t RCD, the access time is controlled by t CAC. 8. t RCD (MIN.) = t RAH (MIN.) + 2t T + (MIN.). 9. t DS and t DH are given with respect to the fall of in the Early-Write cycle and the fall of in the read/write cycle and the Read-Modify-Write cycle. 0. t WCS, t CWD and t RWD are the specified points of the operating mode, and do not represent a limit of operation. When t WCS t WCS (MIN.), it comes into early write cycle with pin coming into high-impedance state. When t CWD t CWD (MIN.) and t RWD t RWD (MIN.), it comes into the read/write cycle with the output data becoming the information for the selection cell. Timing other than the above-mentions will give undefined value of output.. The operation is ensured when either t RCH or t RRH is satisfied. 2-4
NMOS 256K (256K ) Dynamic RAM LH2256 t RC t t CSH t RCD t RSH t CRP t t AR t CPN t ASR t RAH ROW COLUMN t RCS t RRH t RCH t CAC t RAC t OFF DATA VALID 2256-3 Figure 3. Read Cycle 2-5
LH2256 NMOS 256K (256K ) Dynamic RAM t RC t t RSH t CSH t CRP t RCD t t AR t CPN t ASR t RAH ROW COLUMN t WCR t CWL t WCS t WCH t WP t RWL t DS t DH D IN DATA VALID t DHR 2256-4 Figure 4. Write Cycle (Early Write) 2-6
NMOS 256K (256K ) Dynamic RAM LH2256 t RWC t t AR t RSH t CSH t CRP t RCD t t RAH t CPN t ASR ROW COLUMN t RCS t CWL t CWD t RWL t RWD t WP t CAC t OFF DATA VALID t RAC t DS t DH D IN DATA VALID 2256-5 Figure 5. Read-Write/Read-Modify-Write Cycle 2-7
LH2256 NMOS 256K (256K ) Dynamic RAM t RC t t RAH t ASR A 0 - A 7 ROW NOTE: = 2256-6 Figure 6. Only Refresh Cycle t RC t t AR t t t RCD t RSH t CRP t t RAH t CPN t ASR 2 t RCS t RRH t RCH t CAC t OFF t RAC DATA VALID NOTES:. Row address 2. Column address 2256-7 Figure 7. Hidden Refresh Cycle 2-8
NMOS 256K (256K ) Dynamic RAM LH2256 t RC t t FCS t FCH C Figure 8. Before Refresh Cycle 2256-8 2-9
LH2256 NMOS 256K (256K ) Dynamic RAM PAGE MODE CHARACTERISTICS (V CC = 5 V ± 0%, T A = 0 to +70 C) PARAMETER SYMBOL LH2256-0 LH2256-2 LH2256-5 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Page mode cycle time t PC 00 20 45 ns precharge time t CP 40 50 60 ns NOTE t t AR t CSH t PC t RSH t RCD t t CP t t t CRP t RAH t CPN t ASR 2 2 2 t CAC t RAC t OFF t CAC t OFF t CAC t OFF t RCS t RCS t RCS t RCH trch t RRH NOTES:. Row address 2. Column address t RCH 2256-9 Figure 9. Page Mode Read Cycle 2-0
NMOS 256K (256K ) Dynamic RAM LH2256 t t AR t CSH t PC t RSH t RCD t t CP t t t CRP t RAH t CPN t ASR V A IH 0 - A 8 V 2 2 2 IL t WCH t WCH t WCH t WCR t CWL t CWL t CWL t WP t WP t WP t DH t DH t RWL t DS t DS t DS t DH D IN DATA VALID DATA VALID DATA VALID NOTES:. Row address 2. Column address t DHR Figure 0. Page Mode Write Cycle 2256-0 2-
LH2256 NMOS 256K (256K ) Dynamic RAM PACKAGE DIAGRAMS 6DIP (DIP06-P-0300B) DETAIL 6 9 6.65 [0.262] 6.25 [0.246] 9.50 [0.768] 9.00 [0.748] 8 0.30 [0.02] 0.20 [0.008] 0 TO 5 3.65 [0.44] 3.25 [0.28] 7.62 [0.300] TYP. 2.54 [0.00] TYP. 0.56 [0.022] 0.36 [0.04] 0.5 [0.020] MIN 4.40 [0.73] 4.00 [0.57] 3.40 [0.34] 3.00 [0.8] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 6DIP 6-pin, 300-mil DIP 6ZIP (ZIP06-P-0325).30 [0.05] 3.05 [0.20] 2.65 [0.04] 6.90 [0.272] 6.50 [0.256] 8.50 [0.335] 7.70 [0.303] 6 0.30 [0.02] 0.20 [0.008] 3.60 [0.42] 3.00 [0.8].27 [0.050] TYP. 0.60 [0.024] 0.40 [0.06] 2.54 [0.00] TYP. 20.45 [0.805] 9.95 [0.785] 5 2 6 DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 6ZIP 6-pin, 325-mil ZIP 2-2
NMOS 256K (256K ) Dynamic RAM LH2256 ORDERING INFORMATION LH2256 Device Type X Package - ## Speed 0 00 2 20 5 50 Access Time (ns) Blank 6-pin, 300-mil DIP (DIP6-P-300) Z 6-pin, 325-mil ZIP (ZIP6-P-325) NMOS 256K (256K x ) Dynamic RAM Example: LH2256-0 (NMOS 256K (256K x ) Dynamic RAM, 00 ns, 6-pin, 300-mil DIP, Page Mode) 2256-7 2-3