mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut dthiebaut@smith.edu
Lab 1: Lessons Learned
a0 b0 adder c0 S0
a1 b1 a0 b0 adder adder S1 S0
a31 b31 a1 b1 a0 b0 adder... adder adder S31 S1 S0
a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 S1 S0
Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 S1 S0
Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 S1 S0 delay = 1ns
Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 S1 S0 delay = 1ns
Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 1+1ns S1 S0 delay = 1ns
Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 delay = 32ns 1+1ns S1 S0 delay = 1ns
Multi-bit adders designed with "Look-Ahead" Carry Generator Small Lie a31 b31 a1 b1 a0 b0 adder... adder S0 adder S31 delay = 32ns 1+1ns S1 S0 delay = 1ns
Outline Back to Duality Universal Gates: Nands & Nors Karnaugh Maps and Simplification Decoders CHAPTER 3
de Morgan & Duality
de Morgan & Duality (a. b)' = a' + b'
de Morgan & Duality (a. b)' = a' + b' a b
de Morgan & Duality (a. b)' = a' + b' a b a b
de Morgan & Duality (a. b)' = a' + b' Meet the NAND gate! a b a b
Meet the NAND gate! a b a b
NAND: a Gate with Interesting Properties: 1 A B (A. B)' 0 0 1 0 1 1 1 0 1 1 1 0 a
NAND: a Gate with Interesting Properties: 2 Can we implement an AND with NAND(s)? A B (A. B)' 0 0 1 0 1 1 1 0 1 1 1 0 a b a.b
NAND: a Gate with Interesting Properties: 3 Can we implement an OR with NAND(s)? A B (A. B)' 0 0 1 0 1 1 1 0 1 1 1 0 a b a + b
So, we can implement an AND, an OR, and a NOT gate with NANDs, So
Exercise Implement an XOR with only NAND gates. A B A B 0 0 0 0 1 1 1 0 1 1 1 0
Exercise Implement f = Σ (1, 2, 3) with NANDs only.
Exercise Implement the boolean function below with NANDs only.
Advantages of Using NAND Gates
Advantages of Using NAND Gates Uniformity Smaller footprint Large scale programming
Exercise What is the boolean expression of the output of this circuit?
Exercise What is the relationship between the midterm canonical form of a function, and its Nand representation?
(Later) Outline Back to Duality Universal Gates: Nands & Nors Karnaugh Maps and Simplification Decoders CHAPTER 3
Karnaugh Maps
A B C D f 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setup
A B C D f 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 AB CD OO O1 11 1O OO O1 11 1O f Setup
We stopped here last time
Exercises Simplify the following functions using Karnaugh maps: f(a, b, c, d) = Σ (1, 2, 3) g(a, b, c, d) = Σ (1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 15) h(a, b, c, d) = Π (1, 2, 3, 4, 12, 13, 14, 15)
Outline Back to Duality Universal Gates: Nands & Nors Karnaugh Maps and Simplification Nors CHAPTER 3 Decoders
Group Work Look at how we dealt with the NAND gate, and figure out everything there is to say about the NOR gate.
Outline Back to Duality Universal Gates: Nands & Nors Karnaugh Maps and Simplification Nors CHAPTER 3 Decoders
Decoders Processor bit0 bit1 Address bit2 bit3 The "purest" form of decoding
2-to-4 Decoder A0 Y0 Y1 A1 Y2 Y3 A1 A0 Y3 Y2 Y1 Y0 0 0 0 1 1 0 1 1
2-to-4 Decoder A0 A1 Y0 Y1 Y2 Y3 Active-Low Outputs A1 A0 Y3 Y2 Y1 Y0 0 0 0 1 1 0 1 1
Exercise Use a decoder with active-high outputs to implement a 2-bit adder Use a decoder with active-low outputs and only NAND gates to implement a 2-bit adder
Outline Decoders Active-High Active-Low With Enable Input CHAPTER 3
A0 A1 E Y0 Y1 Y2 Y3 A1 A0 E Y3 Y2 Y1 Y0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1
A0 A1 Y0 Y1 Y2 A1 A0 E Y3 Y2 Y1 Y0 0 0 0 1 0 1 1 E Y3 1 0 1 1 1 1
A0 Y 0 A1 A0 E Y3 Y2 Y1 Y0 A1 Y 1 Y 2 E Y 3