UNIT 1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS Numerical Presentation: In science, technology, business, and, in fact, most other fields of endeavour, we are constantly dealing with quantities. Quantities are measured, monitored, recorded, manipulated arithmetically, observed, or in some other way utilized in most physical systems. It is important when dealing with various quantities that we be able to represent their values efficiently and accurately. There are basically two ways of representing the numerical value of quantities: analog and digital. Analog Representation: In analog representation a quantity is represented by a voltage, current, or meter movement that is proportional to the value of that quantity. Analog quantities such as those cited above have an important characteristic: they can vary over a continuous range of values. Below is a diagram of analog voltage vs time: Digital Representation: In digital representation the quantities are represented not by proportional quantities but by symbols called digits. As an example, consider the digital watch, which provides the time of day in the form of decimal digits which represent hours and minutes (and sometimes seconds). As we know, the time of day changes continuously, but the digital watch reading does not change continuously; rather, it changes in steps of one per minute (or per second). In other words, this digital representation of the time of day changes in discrete steps, as compared with the representation of time provided by an analog watch, where the dial reading changes continuously. Below is a diagram of digital voltage vs time:
The major difference between analog and digital quantities, then, can be simply stated as follows: Analog = continuous Digital = discrete (step by step) Advantages and Limitations of Digital Techniques: Advantages: 1. Easier to design. Exact values of voltage or current are not important, only the range (HIGH or LOW) in which they fall. 2. Information storage is easy. 3. Accuracy and precision are greater. 4. Operation can be programmed. Analog systems can also be programmed, but the variety and complexity of the available operations is severely limited. 5. Digital circuits are less affected by noise. As long as the noise is not large enough to prevent us from distinguishing a HIGH from a LOW. 6. More digital circuitry can be fabricated on IC chips. Limitations: There is really only one major drawback when using digital techniques: The real world is mainly analog. Most physical quantities are analog in nature, and it is these quantities that are often the inputs and outputs that are being monitored, operated on, and controlled by a system. To take advantage of digital techniques when dealing with analog inputs and outputs, three steps must be followed: 1. Convert the real-world analog inputs to digital form. (ADC) 2. Process (operate on) the digital information. 3. Convert the digital outputs back to real-world analog form. (DAC) The following diagram shows a temperature control system that requires analog/digital conversions in order to allow the use of digital processing techniques.
Digital Number System: Many number systems are in use in digital technology. The most common are the decimal, binary, octal, and hexadecimal systems. The decimal system is clearly the most familiar to us because it is a tool that we use every day. Examining some of its characteristics will help us to better understand the other systems. Decimal System : Decimal System The decimal system is composed of 10 numerals or symbols. These 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; using these symbols as digits of a number, we can express any quantity. The decimal system, also called the base-10 system because it has 10 digits. 10 3 10 2 10 1 10 0 10-1 10-2 10-3 =1000 =100 =10 =1. =0.1 =0.01 =0.001 Most Significant Digit Binary System: Decimal point Least Significant Digit In the binary system, there are only two symbols or possible digit values, 0 and 1. This base- 2 system can be used to represent any quantity that can be represented in decimal or other number system. 2 3 2 2 2 1 2 0 2-1 2-2 2-3 =8 =4 =2 =1. =1/2 =1/4 =1/8 Most Significant Bit Binary point Least Significant Bit
Binary Counting: The Binary counting sequence is shown in the table: Representing Binary Quantities: In digital systems the information that is being processed is usually presented in binary form. Binary quantities can be represented by any device that has only two operating states or possible conditions. Eg. a switch has only open or closed. We arbitrarily (as we define them) let an open switch represent binary 0 and a closed switch represent binary 1. Thus we can represent any binary number by using series of switches. Typical Voltage Assignment: Binary 1: Any voltage between 2V to 5V Binary 0: Any voltage between 0V to 0.8V Not used: Voltage between 0.8V to 2V, this may cause error in a digital circuit.
We can see another significant difference between digital and analog systems. In digital systems, the exact value of a voltage is not important; eg, a voltage of 3.6V means the same as a voltage of 4.3V. In analog systems, the exact value of a voltage is important. Binary-To-Decimal Conversion: Any binary number can be converted to its decimal equivalent simply by summing together the weights of the various positions in the binary number which contain a 1. and 1 1 0 1 1 2 (binary) 2 4 +2 3 +0+2 1 +2 0 = 16+8+0+2+1 = 27 10 (decimal) 1 0 1 1 0 1 0 1 2 (binary) 2 7 +0+2 5 +2 4 +0+2 2 +0+2 0 = 128+0+32+16+0+4+0+1 = 181 10 (decimal) You should noticed the method is find the weights (i.e., powers of 2) for each bit position that contains a 1, and then to add them up. Decimal-To-Binary Conversion: There are 2 methods: (A) Revese of Binary-To-Digital Method 45 10 = 32 + 0 + 8 + 4 +0 + 1 = 2 5 +0+2 3 +2 2 +0+2 0 = 1 0 1 1 0 1 2 (B) Repeat Division This method uses repeated division by 2. Eg. convert 25 10 to binary
25/ 2 = 12+ remainder of 1 1 (Least Significant Bit) 12/ 2 = 6 + remainder of 0 0 6 / 2 = 3 + remainder of 0 0 3 / 2 = 1 + remainder of 1 1 1 / 2 = 0 + remainder of 1 1 (Most Significant Bit) Result 25 10 = 1 1 0 0 1 2 The Flow chart for repeated-division method is as follow: Octal Number System: The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6,7. 8 3 8 2 8 1 8 0 8-1 8-2 8-3 =512 =64 =8 =1. =1/8 =1/64 =1/512 Most Significant Digit Octal to Decimal Conversion Octal point Least Significant Digit eg. 24.6 8 = 2 x (8 1 ) + 4 x (8 0 ) + 6 x (8-1 ) = 20.75 10
Binary-To-Octal / Octal-To-Binary Conversion: Octal Digit 0 1 2 3 4 5 6 7 Binary Equivalent 000 001 010 011 100 101 110 111 Each Octal digit is represented by three bits of binary digit. eg. 100 111 010 2 = (100) (111) (010) 2 = 4 7 2 8 Repeat Division This method uses repeated division by 8. Eg. convert 177 10 to octal and binary: 177/8 = 22+ remainder of 1 1 (Least Significant Bit) 22/ 8 = 2 + remainder of 6 6 2 / 8 = 0 + remainder of 2 2 (Most Significant Bit) Result 177 10 = 261 8 Convert to Binary = 010110001 2 Decimal-To-Binary Conversion: There are 2 methods: (A) Revese of Binary-To-Digital Method 45 10 = 32 + 0 + 8 + 4 +0 + 1 = 2 5 +0+2 3 +2 2 +0+2 0 = 1 0 1 1 0 1 2 (B) Repeat Division This method uses repeated division by 2. Eg. convert 25 10 to binary 25/ 2 = 12+ remainder of 1 1 (Least Significant Bit) 12/ 2 = 6 + remainder of 0 0 6 / 2 = 3 + remainder of 0 0 3 / 2 = 1 + remainder of 1 1 1 / 2 = 0 + remainder of 1 1 (Most Significant Bit) Result 25 10 = 1 1 0 0 1 2 RESULT: (25) 10 =(11001) 2
The Flow chart for repeated-division method is as follow: Hexadecimal Number System: The hexadecimal system uses base 16. Thus, it has 16 possible digit symbols. It uses the digits 0 through 9 plus the letters A, B, C, D, E, and F as the 16 digit symbols. 16 3 16 2 16 1 16 0 16-1 16-2 16-3 =4096 =256 =16 =1. =1/16 =1/256 =1/4096 Most Significant Digit Hexadec. point Hexadecimal to Decimal Conversion: Least Significant Digit eg. 2AF 16 = 2 x (16 2 ) + 10 x (16 1 ) + 15 x (16 0 ) = 687 10 Repeat Division: Convert decimal to hexadecimal This method uses repeated division by 16. Eg. convert 378 10 to hexadecimal and binary:
378/16 = 23+ remainder of 10 A (Least Significant Bit) 23/ 16 = 1 + remainder of 7 7 1 / 16 = 0 + remainder of 1 1 (Most Significant Bit) Result 378 10 = 17A 8 Convert to Binary = 0001 0111 1010 2 = 0000 0001 0111 1010 (16 bits) Binary-To-Hexadecimal /Hexadecimal-To-Binary Conversion Hexadecimal Digit 0 1 2 3 4 5 6 7 Binary Equivalent 0000 0001 0010 0011 0100 0101 0110 0111 Hexadecimal Digit 8 9 A B C D E F Binary Equivalent 1000 1001 1010 1011 1100 1101 1110 1111 Each Hexadecimal digit is represented by four bits of binary digit. eg. 1011 0010 1111 2 = (1011) (0010) (1111) 2 = B 2 F 16 Octal-To-Hexadecimal /Hexadecimal-To-Octal Conversion 1) Convert Octal (Hexadecimal) to Binary first. 2a) Regroup the binary number in 3 bits a group starts from the LSB if Octal is required. 2b) Regroup the binary number in 4 bits a group from the LSB if Hexadecimal is required. eg. Convert 5A8 16 to Octal. 5A8 16 = 0101 1010 1000 (Binary) = 2 6 5 0 (Octal) Choose the correct answers in the following questions. 1. Convert (63.25) 10 to binary. A. 11111.11 B. 111001.01 C. 111111.01 D. 111111.1 E. NA 2. Convert (43.8125) 10 to binary. A. 101011.1101 B. 110101.1101 C. 101011.1011 D. 110101.1011 E. NA
3. Convert (1001011.011) 2 to decimal. A. 73.0375 B. 75.375 C. 91.375 D. 75.573 E. NA 4. Convert (110101.1011) 2 to decimal. A. 53.6875 B. 53.6375 C. 52.6875 D. 55.6375 E. NA 5. Convert (11001.1) 2 to base 8. A. (62.4) 8 B. (62.1) 8 C. (31.1) 8 D. (31.2) 8 E. (31.4) 8 6. Convert (25.6) 8 to binary. A. (10101.11) 2 B. (11101.10) 2 C. (10101.10) 2 D. (10010.11) 2 E. (11111.01) 2 7. Convert (35.1) 8 to base 16. A. (17.4) 16 B. (1D.1) 16 C. (D1.2) 16 D. (E8.1) 16 E. NA 8. Convert (39.A) 16 to base 8. A. (35.5) 8 B. (70.5) 8 C. (71.5) 8 D. (72.25) 8 E. (75.5) 8 9. Convert (485) 10 to base 16. A. (1E5) 16 B. (231) 16 C. (5E1) 16 D. (15E) 16 E. NA 10. Try Harder Convert (397) 10 to base 3. A. (12310) 3 B. (121201) 3 C. (012211) 3 D. (112201) 3 E. (100202) 3 Boolean Variables & Truth Tables: Boolean algebra differs in a major way from ordinary algebra in that boolean constants and variables are allowed to have only two possible values, 0 or 1.
Boolean 0 and 1 do not represent actual numbers but instead represent the state of a voltage variable, or what is called its logic level. Some common representation of 0 and 1 is shown in the following diagram. Logic 0 Logic 1 False Off Low No Open Switch True On High Yes Close Switch In boolean algebra, there are three basic logic operations: OR, AND and NOT. These logic gates are digital circuits constructed from diodes, transistors, and resistors connected in such a way that the circuit output is the result of a basic logic operation (OR, AND, NOT) performed on the inputs. Truth Table: A truth table is a means for describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. In the following two-inputs logic circuit, the table lists all possible combinations of logic levels present at inputs A and B along with the corresponding output level X. When either input A OR B is 1, the output X is 1. Therefore the "?" in the box is an OR gate. Go to next section to explore more on the OR gate. OR Operation: The expression X = A + B reads as "X equals A OR B". The + sign stands for the OR operation, not for ordinary addition. The OR operation produces a result of 1 when any of the input variable is 1. The OR operation produces a result of 0 only when all the input variables are 0.
An example of three input OR gate and its truth table is as follows: With the OR operation, 1 + 1 = 1, 1+ 1 + 1 = 1 and so on. AND Operation: The expression X = A * B reads as "X equals A AND B". The multiplication sign stands for the AND operation, same for ordinary multiplication of 1s and 0s. The AND operation produces a result of 1 occurs only for the single case when all of the input variables are 1. The output is 0 for any case where one or more inputs are 0
An example of three input AND gate and its truth table is as follows: With the AND operation, 1*1 = 1, 1*1*1 = 1 and so on. NOT Operation: The NOT operation is unlike the OR and AND operations in that it can be performed on a single input variable. For example, if the variable A is subjected to the NOT operation, the result x can be expressed as x = A' where the prime (') represents the NOT operation. This expression is read as: x equals NOT A x equals the inverse of A x equals the complement of A Each of these is in common usage and all indicate that the logic value of x = A' is opposite to the logic value of A.
The truth table of the NOT operation is as follows: 1' = 0 because NOT 1 is 0 0' = 1 because NOT 0 is 1 The NOT operation is also referred to as inversion or complementation, and these terms are used interchangeably. NOR Operation: NOR and NAND gates are used extensively in digital circuitry. These gates combine the basic operations AND, OR and NOT, which make it relatively easy to describe then using Boolean Algebra. NOR is the same as the OR gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NOR gate is: X = ( A + B )'
An example of three input OR gate can be constructed by a NOR gate plus a NOT gate: NAND Operation: NAND is the same as the AND gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NAND gate is: X = ( AB )' Choose the correct answers in the following questions. 1. Boolean algebra is different from ordinary algebra in which way? A. Boolean algebra can represent more than 1 discrete level between 0 and 1 B. Boolean algebra have only 2 discrete levels: 0 and 1 C. Boolean algebra can describe up to 3 levels of logic levels D. They are actually the same E. NA The following 2 questions are refered to the below image:
2. What is the output X if both inputs A and B are 0? A. 0 B. 1 C. I don't know D. NA 3. What is the output X if A=1 and B=0? A. 0 B. 1 C. I don't know D. NA 4. For a three inputs (A,B C) OR gate, what inputs are needed if output=0? A. A=0, B=0, C=1 B. A=0, B=1, C=0 C. A=1, B=1, C=1 D. A=0, B=0,C=0 E. NA The following 2 questions are refered to the below image: 5. What is the output X if input A=1, B=0 and C=1? A. 0 B. 1 C. I don't know D. NA 6. What inputs are needed if output=1? A. A=0,B=0,C=0 B. A=1, B=0, C=1 C. A=0, B=1, C=0 D. A=1, B=1, C=1 E. NA The following 2 questions are related to the below image: 7. What is the ouput of the above gate if input A=0, B=1? A. 0 B. 1 C. Not sure D. NA 8. What are the value of the inputs if output=1? A. A=0, B=0 B. A=0, B=1 C. A=1, B=0 D. A=1, B=1 E. I don't know
The following 2 questions are related to the below image: 9. What are the values of the inputs if output=0? A. A=0, B=0 B. A=0, B=1 C. A=1, B=0 D. A=1, B=1 E. I don't know 10. Try Harder For the truth table below, what type of logic gate is it? A. 3 Inputs OR B. 3 Inputs AND C. 3 Inputs NOR D. 3 Inputs NAND E. Not sure Describing Logic Circuits Algebraically: Any logic circuit, no matter how complex, may be completely described using the Boolean operations, because the OR gate, AND gate, and NOT circuit are the basic building blocks of digital systems. This is an example of the circuit using Boolean expression: If an expression contains both AND and OR operations, the AND operations are performed first (X=AB+C : AB is performed first), unless there are parentheses in the expression, in which case the operation inside the parentheses is to be performed first (X=(A+B)+C : A+B is performed first). Circuits containing Inverters:
Whenever an INVERTER is present in a logic-circuit diagram, its output expression is simply equal to the input expression with a prime (') over it. Evaluating Logic Circuit Outputs: Once the Boolean expression for a circuit output has been obtained, the output logic level can be determined for any set of input levels. This are two examples of the evaluating logic circuit output: Let A=0, B=1, C=1, D=1 X = A'BC (A+D)' = 0'*1*1* (0+1)' = 1 *1*1* (1)' = 1 *1*1* 0 = 0 Let A=0, B=0, C=1, D=1, E=1 X = [D+ ((A+B)C)'] * E = [1 + ((0+0)1 )'] * 1 = [1 + (0*1)'] * 1 = [1+ 0'] *1 = [1+ 1 ] * 1 = 1 In general, the following rules must always be followed when evaluating a Boolean expression: 1. First, perform all inversions of single terms; that is, 0 = 1 or 1 = 0. 2. Then perform all operations within parentheses. 3. Perform an AND operation before an OR operation unless parentheses indicate otherwise. 4. If an expression has a bar over it, perform the operations of the expression first and then invert the result.
Determining Output Level from a Diagram: The output logic level for given input levels can also be determined directly from the circuit diagram without using the Boolean expression. Implementing Circuits from Boolean Expression: If the operation of a circuit is defined by a Boolean expression, a logic-circuit diagram can he implemented directly from that expression. Suppose that we wanted to construct a circuit whose output is y = AC+BC' + A'BC. This Boolean expression contains three terms (AC, BC', A'BC), which are ORed together. This tells us that a three-input OR gate is required with inputs that are equal to AC, BC', and A'BC, respectively. Each OR-gate input is an AND product term, which means that an AND gate with appropriate inputs can be used to generate each of these terms. Note the use of Inverters to produce the A' and C' terms required in the expression.
Boolean Theorems Investigating the various Boolean theorems (rules) can help us to simplify logic expressions and logic circuits. Multivariable Theorems The theorems presented below involve more than one variable: (9) x + y = y + x (commutative law) (10) x * y = y * x (commutative law) (11) x+ (y+z) = (x+y) +z = x+y+z (associative law) (12) x (yz) = (xy) z = xyz (associative law) (13a) x (y+z) = xy + xz (13b) (w+x)(y+z) = wy + xy + wz + xz (14) x + xy = x [proof see below] (15) x + x'y = x + y
Proof of (14) x + xy = x (1+y) = x * 1 [using theorem (6)] = x [using theorem (2)] DeMorgan's Theorem: DeMorgan's theorems are extremely useful in simplifying expressions in which a product or sum of variables is inverted. The two theorems are: (16) (x+y)' = x' * y' (17) (x*y)' = x' + y' Theorem (16) says that when the OR sum of two variables is inverted, this is the same as inverting each variable individually and then ANDing these inverted variables. Theorem (17) says that when the AND product of two variables is inverted, this is the same as inverting each variable individually and then ORing them. Example: X = [(A'+C) * (B+D')]' = (A'+C)' + (B+D')' [by theorem (17)] = (A''*C') + (B'+D'') [by theorem (16)] = AC' + B'D Three Variables DeMorgan's Theorem (18) (x+y+z)' = x' * y' * z' (19) (xyz)' = x' + y' + z' Implications of DeMorgan's Theorem For (16): (x+y)' = x' * y'
For (17): (x*y)' = x' + y' Universality of NAND & NOR Gates: It is possible to implement any logic expression using only NAND gates and no other type of gate. This is because NAND gates, in the proper combination, can be used to perform each of the Boolean operations OR, AND, and INVERT.
In a similar manner, it can be shown that NOR gates can be arranged to implement any of the Boolean operations. Alternate Logic Gate Representations: The left side of the illustration shows the standard symbol for each logic gate, and the right side shows the alternate symbol. The alternate symbol for each gate is obtained from the standard symbol by doing the following: 1. Invert each input and output of the standard symbol. This is done by adding bubbles (small circles) on input and output lines that do not have bubbles, and by removing bubbles that are already there. 2. Change the operation symbol from AND to OR, or from OR to AND. (In the special case of the INVERTER, the operation symbol is not changed.)
Several points should be stressed regarding the logic symbol equivalences: 1. The equivalences are valid for gates with any number of inputs. 2. None of the standard symbols have bubbles on their inputs, and all the alternate symbols do. 3. The standard and alternate symbols for each gate represent the same physical circuit: there is no difference in the circuits represented by the two symbols. 4. NAND and NOR gates are inverting gates, and so both the standard and alternate symbols for each will have a bubble on either the input or the output. AND and OR gates are non Inverting gates, and so the alternate symbols for each will have bubbles on both inputs and output. Logic Symbol Interpretation: Concept of Active Logic Levels: When an input or output line on a logic circuit symbol has no bubble on it, that line is said to be active-high. When an input or output line does have a bubble on it, that line is said to be active-low. The presence or absence of a bubble, then, determines the active-high/active- LOW status of a circuit's inputs and output, and is used to interpret the circuit operation.
Choose the correct answers in the following questions. 1. What function is implemented by the circuit shown A. x'y'+z B. (x'+y')z C. x'y'z D. x'+y'+z E. NA 2. What function is implemented by the circuit shown A. x+y+z B. x+y+z' C. x'y'z D. x'+y'+z' E. NA 3. What function is implemented by the circuit shown A. xz'+y B. xz+y C. x'z+y' D. x'y'+y'z' E. x'y'+y'z 4. Which gate is the following circuit equivalent to? A. AND B. OR
C. NAND D. NOR E. None of the above 5. Which of the following functions equals the function: f=x+yz'? A. x(y'+z) B. x(y'+z) C. (y+x)(z'+x) D. (y+x')(x'+z') E. NA 6. Any possible binary logic function can be implemented using only. A. AND B. OR C. NOT D. AA (anyone is sufficient) E. NAND 7. The function in the following circuit is: A. abcd B. ab+cd C. (a+b)(c+d) D. a+b+c+d E. (a'+b')(c'+d') 8. Given F=A'B+(C'+E)(D+F'), use de Morgan's theorem to find F'. A. ACE'+BCE'+D'F B. (A+B')(CE'D'F) C. A+B+CE'D'F D. ACE'+AD'F+B'CE'+B'D'F E. NA 9. The function in the following circuit is: A. x'+y'+z' B. x+y+z C. x'z'+y'z' D. xy+z E. z 10. Try Harder Simplify the following: {[(AB)'C]'D}' A. (A'+B')C+D' B. (A+B')C'+D' C. A'+(B'+C')D D. A'+B'+C'+D' E. A+B+C+D
MINIMIZATION OF BOOLEAN EXPRESSION WHY we Need to simplify (minimize) expressions? 1.Boolean expressions are practically implemented in the form of GATES (Circuits). 2. A minimized Boolean expression means less number of gates which is used to minimize hardware cost for the same expression List Different Methods for Minimization: 1. Karnaugh Maps 2. Algebraic method WHAT is Karnaugh Map (K-Map)? 1.A special version of a truth table 2.Karnaugh Map (K-Map) is a GRAPHICAL display of fundamental terms in a Truth Table. 3. Don t require the use of Boolean Algebra theorems and equation. 4.Works with 2,3,4 (even more) input variables (gets more and more difficult with more variables). 5.K-maps provide an alternate way of simplifying logic circuits. 6. One can transfer logic values from a Truth Table into a K-Map. 7.The arrangement of 0 s and 1 s within a map helps in visualizing, leading directly to Simplified Boolean Expression. Drawing a Karnaugh Map (K-Map) : 1.K-map is a rectangle made up of certain number of SQUARES 2.For a given Boolean function there are 2 N squares where N is the number of variables (inputs) 3.In a K-Map for a Boolean Function with 2 Variables f(a,b) there will be 2 2 =4 squares 4.Each square is different from its neighbour by ONE Literal 5.Each SQUARE represents a MAXTERM or MINTERM
The figure shows the Four variable K-Map. Correspondence between the Karnaugh Map and the Truth Table for the general case of a two Variable Problem: Karnaugh maps consist of a set of 2 2 squares where 2 is the number of variables in the Boolean expression being minimized: For three and four variable expressions Maps with 2 3 = 8 and 2 4 = 16 cells are used. Each cell represents a MINTERM or a MAXTERM :
Minimization Steps (SOP Expression) Form groups of adjacent 1's. Make groups as large as possible. Group size must be a power of two. i.e. Group of 8 (OCTET), 4 (QUAD), 2 (PAIR) or 1 (Single) OCTET REDUCTION ( Group of 8): The term gets reduced by 3 literals i.e. 3 variables change within the group of 8 ( Octets )
Another type of Octet Reduction: Another type of Octet Reduction: QUAD REDUCTION ( Group of 4): The term gets reduced by 2 literals i.e. 2 variables change within the group of 4( QUAD )
QUAD REDUCTION ( Group of 4): PAIR REDUCTION ( Group of 2): The term gets reduced by 1 literals i.e. 1 variables change within the group of 2( PAIR )
SINGLE CELL REDUCTION: The term is not reduced in a single cell Karnaugh Maps - Rules of Simplification: 1.Groups may not include any cell containing a zero 2.Groups may be horizontal or vertical, but not diagonal
Groups must contain 1, 2, 4, 8, or in general 2 n cells. That is if n = 1, a group will contain two 1's since 2 1 = 2. If n = 2, a group will contain four 1's since 2 2 = 4. Groups may wrap around the table. The leftmost cell in a row may be grouped with the rightmost cell and The top cell in a column may be grouped with the bottom cell.
Important Rules: Minimization Steps (SOP Expression) Example: Reduce f(wxyz)=σ(1,3,4,5,7,10,11,12,14,15)
Example.1. Simplify the following Boolean function in to (a) Sum of Product (b) Product of Sums form: F=(A,B,C,D)= (0,1,2,5,8,9,10) Sol: The K-map of the given function as shown in the figure The 1 s marked in the map represents the minterms of the function. The 0 s marked in the map represents the minterms which is not covered in function F. S o it denotes the compliment of F. By combining 1 s in the map,it gives the simplified function in Sum of Product form: (a) F=B D +B C +A C D By combining marked with 0 s are combined in the map,we got the compliment function :F=AB+CD+BD Applying Demorgan s theorem (dual, complimenting each literal) we obtained the simplified function in Product of Sums : (b) F=(A +B )(C +D )(B +D ) The simplified functions of both (a),(b) are realized using logic gates as shown in the figure. DON T CARE CONDITIONS:
In some applications the function is not specified for certain combinations of the variables.(example- the four bit binary code for the decimal digits has six combinations) Functions that have unspecified outputs for some input combinations are called incompletely specified functions.the unspecified minterms of a function is called Don t Care Conditions. This used on a map to provide further simplification of the Boolean expression. Simplify the Boolean function F(w,x,y,z)= (1,3,7,11,15). Sol: The Don t care conditions d(w,x,y,z)= (0,2,5) The minterms of F are the variable combinations that make the function equal to 1.The minterms of d are the don t care minterms that may be assigned either 0 or 1. The K-map simplification as shown figure. The minterms of F are the variable combinations that make the function equal to 1. Those of d are marked by X s.to get the simplified Boolean we can combine the X with 1. QUINE-McCLUSKEY MINIMIZATION: Quine-McCluskey minimization method uses the same theorem to produce the solution as the K-map method, namely X(Y+Y')=X. Minimization Technique:
The expression is represented in the canonical SOP form if not already in that form. The function is converted into numeric notation. The numbers are converted into binary form. The minterms are arranged in a column divided into groups. Begin with the minimization procedure. Each minterm of one group is compared with each minterm in the group immediately below. Each time a number is found in one group which is the same as a number in the group below except for one digit, the numbers pair is ticked and a new composite is created. This composite number has the same number of digits as the numbers in the pair except the digit different which is replaced by an "x". The above procedure is repeated on the second column to generate a third column. The next step is to identify the essential prime implicants, which can be done using a prime implicant chart. Where a prime implicant covers a minterm, the intersection of the corresponding row and column is marked with a cross. Those columns with only one cross identify the essential prime implicants. -> These prime implicants must be in the final answer. The single crosses on a column are circled and all the crosses on the same row are also circled, indicating that these crosses are covered by the prime implicants selected. Once one cross on a column is circled, all the crosses on that column can be circled since the minterm is now covered. If any non-essential prime implicant has all its crosses circled, the prime implicant is redundant and need not be considered further. Next, a selection must be made from the remaining nonessential prime implicants, by considering how the non-circled crosses can be covered best. One generally would take those prime implicants which cover the greatest number of crosses on their row. If all the crosses in one row also occur on another row which includes further crosses, then the latter is said to dominate the former and can be selected. The dominated prime implicant can then be deleted. Example: Find the minimal sum of products for the Boolean expression, f= (1,2,3,7,8,9,10,11,14,15), using Quine-McCluskey method. Sol: Firstly these minterms are represented in the binary form as shown in the table below. The above binary representations are grouped into a number of sections in terms of the number of 1's as shown in the table below. Binary representation of minterms Minterms U V W X 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 7 0 1 1 1 8 1 0 0 0
9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 14 1 1 1 0 15 1 1 1 1 Group of minterms for different number of 1's No of 1's Minterms U V W X 1 1 0 0 0 1 1 2 0 0 1 0 1 8 1 0 0 0 2 3 0 0 1 1 2 9 1 0 0 1 2 10 1 0 1 0 3 7 0 1 1 1 3 11 1 0 1 1 3 14 1 1 1 0 4 15 1 1 1 1 Any two numbers in these groups which differ from each other by only one variable can be chosen and combined, to get 2-cell combination, as shown in the table below. 2-Cell combinations: Combinations U V W X (1,3) 0 0-1 (1,9) - 0 0 1 (2,3) 0 0 1 - (2,10) - 0 1 0 (8,9) 1 0 0 - (8,10) 1 0-0 (3,7) 0-1 1 (3,11) - 0 1 1 (9,11) 1 0-1 (10,11) 1 0 1 - (10,14) 1-1 0 (7,15) - 1 1 1 (11,15) 1-1 1 (14,15) 1 1 1 - From the 2-cell combinations, one variable and dash in the same position can be combined to form 4-cell combinations as shown in the figure below. 4-Cell combinations: Combinations U V W X (1,3,9,11) - 0-1
(2,3,10,11) - 0 1 - (8,9,10,11) 1 0 - - (3,7,11,15) - - 1 1 (10,11,14,15) 1-1 - The cells (1,3) and (9,11) form the same 4-cell combination as the cells (1,9) and (3,11). The order in which the cells are placed in a combination does not have any effect. Thus the (1,3,9,11) combination could be written as (1,9,3,11). From above 4-cell combination table, the prime implicants table can be plotted as shown in table below. Prime Implicants 1 2 3 7 8 9 10 11 14 15 (1,3,9,11) X - X - - X - X - - (2,3,10,11) - X X - - - X X - - (8,9,10,11) - - - - X X X X - - (3,7,11,15) - - - - - - X X X X - X X - X X - - - X - The columns having only one cross mark correspond to essential prime implicants. A yellow cross is used against every essential prime implicant. The prime implicants sum gives the function in its minimal SOP form Y = V'X + V'W + UV' + WX + UW Design of Adders Need of Adder circuits: Adders are important in computers and other types of digital systems in which numerical data are processed. Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give out sum and carry as output. Basically we have two types of adders 1.Half adder 2. Full adder circuit Design of Half Adder: A logic circuits for the addition of two one-bit numbers is referred to as an Half Adder. Basic rule for binary addition: The half-adder accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit.
The circuit diagram and truth table of Half adder is as shown in figure. Design of Full Adder Circuit: The full-adder accepts two input bits and an input carry and generates a sum output and an output carry.
Half adder has only two inputs and there is no provision to add carry coming from the lower order bits when multibit addition is performed. For this purpose a third input is added to this circuit and it is used to add 3 bits at a time is called Full Adder circuit. The K-map of the Full adder circuit as shown in the figure. In this K-map variable x represents Cin and yz represents variables A,B. Design of Half Subtractor: The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol and truth table are shown below.
Truth Table: X Y D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 From the above table we can draw the Kmap as shown below for "difference" and "borrow". The boolean expression for the difference and Borrow can be written. From the equation we can draw the half-subtracter as shown in the figure below. Design of Full Subtractor: A full subtracter is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth table are shown below. Symbol: Truth Table:
X Y Bin D Bout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 From above table we can draw the Kmap as shown below for "difference" and "borrow". The boolean expression for difference and borrow can be written. D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin = (X'Y' + XY)Bin + (X'Y + XY')Bin' = (X Y)'Bin + (X Y)Bin' = X Y Bin Bout = X'.Y + X'.Bin + Y.Bin From the equation we can draw the half-subtracter as shown in figure below. From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-subtracter circuit is more or less same as a full-adder with slight modification. Parallel Binary Adders: The carry output of each adder is connected to the carry input of the next higher-order adder.
Ripple Carry Adders: If the input adder is implemented using the carry ripple down the line of cascaded adders from the LSB position to MSB position. This decreases the operating speed of the adder. The time required for addition operation to be completed is limited by the amount of time required to complete the ripple carry operation. Look-Ahead Carry Adders: Carry generation occurs when an output carry is produced (generated) internally by the full-adder. A carry is generated only when both input bits are 1s. The generated carry, C g, is expressed as the AND function of the two input bits, A and B. Carry propagation occurs when the input carry is rippled to become the output carry. An input carry may be propagated by the full-adder when either or both of the input bits are 1s. The propagated carry, C p, is expressed as the OR function of the two input bits. The carry look ahead generation process is used for increasing the speed of operation. This technique anticipates the carry bits for each stage before the actual summing operation. Design of Comparators: Comparators can compare either a variable number X (xn xn-1... x3 x2 x1) with a predefined constant C (cn cn-1... c3 c2 c1) or two variable numbers X and Y. In the first case the implementation reduces to a series of cascaded AND and OR logic gates. If the comparator answers the question 'X>C?' then its hardware implementation is designed according to the following rules: The number X has two types of binary figures: bits corresponding to '1' in the predefined constant and bits corresponding to '0' in the predefined constant. The bits of the number X corresponding to '1' are supplied to AND gates
The bits corresponding to '0' are supplied to OR logic gates Block Diagram of 1-bit Comparator: The comparison process of two positive numbers X and Y is performed in a bit-by-bit manner 1.If the most significant bits are Xn='1' and Yn='0' then number X is larger than Y. 2.If Xn='0' and Yn='1' then number X is smaller than Y. starting with the most significant bit: 3.If Xn=Yn then no decision can be taken about X and Y based only on these two bits. 4.To compare the magnitude of two binary quantities to determine the relationship of those quantities. o The simplest form a comparator ckt determines whether two numbers are equal. IC Comparators:
To determine an inequality of binary numbers A and B, you first examine the highest-order bit in each number: If A 3 =1 and B 3 =0 number A is greater than number B If A 3 =0 and B 3 =1 number A is less than number B If A 3 =B 3 you must examine the next lower bit position for an equality 4-bit Comparator Logic Circuit: MSI: 7485 4-bit Magnitude Comparator: CODE CONVERTERS: There is a wide variety binary codes used in digital system. The codes are 1.Binary coded Decimal(BCD) 2.Excess-3 Code 3.Gray 4.Octal 5.Hexadecimal
So the code converters are essential in digital for various code conversion, Encoding, and Decoding purposes. Types of Code converters: 1.BCD-to-Binary Converter 2.Binary-to-BCD Converter 3.Binary to- Gray Converter 4.Gray to- Binary Converter Gray code: It is a minimum change code where only one bit in the code group changes while going from one step to the next. Binary numbers have more than 1 bits changing when increasing or decreasing continuously e.g. 0011 to 0100 (3 to 4): 3 bits change. In digital electronic circuits, sometimes it is desired to have only 1 bit changed In this case, Gray Code can be used In Gray Code, the adjacent numbers have only 1 bit different It is also called as unit distance code. In this code no weight can be attached with each bit position therefore it is unsuitable for arithmetic operations. Gray codes are useful in input and output devices and in analog and digital converters. Gray to Binary conversion: MSB of the gray code is same as binary number. So write the MSB as it is. Add the MSB of the output with bit immediately on right in input and record the sum. If a carry is generated it is ignored. Continue adding the bits in the output to immediate input bit in right till the LSB is reached. The binary equivalent has same number of bits as the gray code. This can be achieved by using X-OR gate. Example Convert 1011 to binary
Binary to Gray conversion MSB of the binary is same as MSB of gray code. Add the MSB of binary with immediate bit to right in binary and that is the next gray bit. If a carry is generated it is ignored. Repeat the procedure till the LSB is reached. Example: Convert 1011 to gray code
Excess-3 (XS3) code: 1. Non weighted BCD code 2. Add three to each nibble of BCD code to get the XS3 code. 3. This code helps in performing subtraction operations in the earlier computers. 4. The table below shows the BCD and XS-3 codes for decimal digits 0 to 9 Decimal to XS-3 conversion Decimal BCD Excess-3 0 0000 0011 1 0001 0100 2 0010 0101 3 0011 0110 4 0100 0111 5 0101 1000 6 0110 1001 7 0111 1010 8 1000 1011 9 1001 1100 (Ex).Convert 436 into XS-3 code BCD equivalent of 436 is 0100 0011 0110 Add 3 (i.e) 0011 to each group of 4 bits 0100 0011 0110 0011 0011 0011 ---------------------- 0111 0110 1001 ---------------------- 7 6 9 - Xs-3 in decimal ENCODERS: An encoder converts an active input signal in to a coded output signal.there are n input lines, only one of which is active. Internal logic within the encoder converts this active input to a coded binary output with m bits. An encoder is a combinational circuit that performs the inverse operation of a decoder. If a device output code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2 n -to-n, priority encoders. The simplest encoder is a 2 n -to-n binary encoder, where it has only one of 2 n inputs = 1 and the output is the n-bit binary number corresponding to the active input. It can be built from OR gates
Decimal-to-Binary Encoder: Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4-to-10 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of a Decimal-to-binary encoder In this circuit digital input A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH input. Truth Table: I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are: Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7 Based on the above equations, we can draw the circuit as shown below Priority Encoder: If more then two inputs are active simultaneously, the output is unpredictable or rather it is not what we expect it to be.this problem is resolved if priority is established so that only one input is encoded, no matter how many inputs are active at a given point of time. The priority encoder includes a priority function. The operation of the priority encoder is such that if two or more inputs are active at the same time, the input having the highest priority will take precedence. Example: 4to3 Priority Encoder: The truth table of a 4-input priority encoder is as shown below. The input D3 has the highest priority, D2 has next highest priority, D0 has the lowest priority. This means output Y2 and Y1 are 0 only when none of the inputs D1, D2, D3 are high and only D0 is high. A 4 to 3 encoder consists of four inputs and three outputs, truth table and symbols of which is shown below. Truth Table: D3 D2 D1 D0 Y2 Y1 Y0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 x 0 1 0 0 1 x x 0 1 1
1 X x x 1 0 0 Now that we have the truth table, we can draw the Kmaps as shown below: K-Maps for 4 to 3 Priority Encoder: From the Kmap we can draw the circuit as shown below. For Y2, we connect directly to D3 The same logic can be implemented for higher order encoders also. Octal- to-binary Encoder: The octal code is often used at the inputs of digital circuits that require manual entering long binary words. Priority encoder 74148 IC has been designed to achieve this operation. This circuit also has active low inputs and active low outputs. The enable input and carry outputs,which are also active low,are used to cascade circuits to handle more inputs. 74148 8-to-3 Priority Encoder: Block diagram of 74148 Octal-to-Binary Priority Encoder:
Pins 0-7:Octal inputs (Active Low) ;A0,A1, A2 Binary outputs (active low) EI- Enable input (Active Low) ; GS, E0- Carry outputs (active low) Applications of Encoder: A Hexadecimal to binary encoder which is also a very useful circuit because of wide spread use of hexadecimal code in computers, microprocessors, can be designed using this facility. The priority encoder can conveniently be used for handling priority interrupts in computers,microprocessors etc., Decoders: A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.binary Decoder has n inputs and 2 n outputs also called as n-to-2 n decoder. Inputs have all the 2 n combinations and the corresponding output will be activated for each input combinations. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Figure below shows the pseudo block of a decoder. A binary decoder has n inputs and 2 n outputs. Only one output is active at any one time, corresponding to the input value. Figure below shows a representation of Binary n-to-2 n decoder
Decoders usually have an enable line, If enable=0, decoder is off. It means all output lines are zero If enable=1, decoder is on and depending on input, the corresponding output line is 1, all other lines are 0. 3-to-8 Decoder: The logic diagram of 3-to-8 decoder circuit and logic function is as shown in figure. The inputs and outputs of the 3-to-8 decoder circuit as shown in the figure. The BCD-to-Decimal Decoder: The BCD-to-decimal converts each BCD code into one of ten possible decimal digit indications. So it is Called 4-line-to-10-line decoder or 1-of-10 decoder
2-to-4 Decoder with Output Enable: The function table and logic circuit as shown in figure. The output equations are Implement Logic Function with Decoder: Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2 n decoder to generate the minterms, and an OR gate to form the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can be implemented with an n-to- 2 n decoder with m OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few minterms. Example.1. Full adder using decoder: S(x, y, z) = (1,2,4,7) C(x, y, z) = (3,5,6,7)
Truth Table: X Y Z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 From the truth table we know the values for which the sum (s) is active and also the carry (c) is active. Thus we have the equation as shown above and a circuit can be drawn as shown below from the equation derived. Use a 3-to-8 decoder to implement: f = x y z + xy z + xyz (m1 + m5 + m7) The BCD-to-7-Segment Decoder: The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive 7-segment display devices to produce a decimal readout.
The BCD-to-7-Segment Decoder (The Application): Seven segment display is the most popular display device used in digital system. For displaying data using this device,the data have to be converted from BCD-to-7 Segment code. A number of MSI IC s are available to perform BCD to 7-segment decoders(7446, 74246, 7447, 74247) The decoder /driver circuit has 4 input lines for BCD data and 7 output lines to drive a 7-segment display. If the outputs are Active low,then the 7-segment LED must be the common anode type. If the outputs are Active high,then the 7-segment LED must be the common cathode type.
Example:Use a 3-to-8 decoder to implement: f = x y z + xy z + xyz (m1 + m5 + m7) Construct 4-to-16 Decoder using 3-to-8 decoders Use 2 3-to-8 decoders Inputs: D, C, B, A Outputs: Y0 Y15 When D = 0, top decoder is enabled When D = 1,bottom decoderis enabled En is enable
Application Example: 1.Implement the functions (1) f 1 (x 2,x 1,x 0 ) = Σm(0,1,3,4,5,6),(2) f 2 (x 2,x 1,x 0 ) = Σm(1,2,3,4,6) using using 3-to 8 Decoders. Sol: Σm(0,5,7), Σm(2,7) 2.Implement the function s using 3-t0-8 decoder f 1 (x 2,x 1,x 0 ) = Σm(0,2,6,7) and f 2 (x 2,x 1,x 0 ) = Σm(3,5,6,7) and design (a) Using output and-gates. (b) Using output nand-gates. Multiplexers (Data Selectors): A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A number of select inputs determine which data source is connected to the output.
A MUX is a device that allows digital information from several sources to be routed onto a single line for data transmission over that line to a common destination. The basic MUX has several data-input lines and a single output line. It also has data-select inputs, which permit digital data on any one of the inputs to be switched to the output line. The block diagram of MUX with n data sources of b bits wide and s bits wide select line is shown in below figure. MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output as shown in the figure below. At any given point of time only one input gets selected and is connected to output, based on the select input signal. The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the inputs, which is connected to the output. As you can see at any given point of time only one input gets transferred to output. 2x1 MUX: A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux is given in the table below.
Design of a 2:1 Mux: To derive the gate level implementation of 2:1 mux we need to have truth table as s hown in figure. And once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is equal to '1'.Combining the two 1' as shown in figure, we can drive the output y as shown below Truth Table: K map: Y = A.S + B.S B A S Y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Circuit:
Design of 4:1 Multiplexers (Data Selectors) : The logic circuit diagram of 4:1 multiplexer Truth table:
The output function of the 4:1 multiplexer Y = S 1. S 0. I 0 + S 1. S 0. I 1 + S 1. S 0. I 2 + S 1. S 0. I 3 MSI MUX: 74150: 16-to-1:74153: Dual 4-to-1: 74157: Quad 2-to-1: 74151: 8-to-1 Design 16-to-1 MUX using 74151: Sol: Use two 74151 D = 0 enables top MUX D = 1 enables bottom MUX W = Y = (Y1+Y2) = (W1 +W2 ) = W1W2
Larger Multiplexers: Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown below. 8-to-1 multiplexer from Smaller MUX: 16-to-1 multiplexer from 4:1 mux:
Quadruple 2-to-1 MUX: It is 2-to-1 MUX with 4 bits for each input There is 1 output of 4 bits There is 1 select signal When 1 input is selected, the whole group of 4 bits goes to the output Quad 2-to-1 MUX: Implementing Functions Multiplexers: Any n-variable logic function can be implemented using a smaller 2 n-1 -to-1 multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable functions) as follows. Express function in canonical sum-of-minterms form. Choose n-1 variables as inputs to mux select lines. Construct the truth table for the function, but grouping inputs by selection line values (i.e select lines as most significant inputs). Determine multiplexer input line i values by comparing the remaining input variable and the function F for the corresponding selection lines value i.
We have four possible mux input line i values: Connect to 0 if the function is 0 for both values of remaining variable. Connect to 1 if the function is 1 for both values of remaining variable. Connect to remaining variable if function is equal to the remaining variable. Connect to the inverted remaining variable if the function is equal to the remaining variable inverted Case 1: Number of inputs is equal to number of select lines Design procedure Identify the decimal number corresponding to each minterm in the expression Connect logic 1 level to input lines corresponding to these numbers Connect logic 0 level to the others Connect inputs to selected lines Case 2: Number of inputs is higher than number of select lines Procedure 2.1: Reduce the number of inputs to the number of select lines by inspection K-map Procedure 2.2: Use multiplexer tree when number of inputs exceeds the largest number of inputs on available ICs Can be done by one of these two techniques connect the MSB input to the enable/strobe input connect the MSB input to another multiplexer Truth table of a 3 variable logic circuit Case2.1: Reducing Inputs: 3-variable Function using 4-to-1 mux: Implement the function F(X,Y,Z) = S(0,1,3,6) using a single 4-to-1 mux and an inverter. We choose the two most significant inputs X, Y as mux select lines.
1-Realize the function f(x,y,z) = Σm(0,2,3,5) using a 4-to-1-line multiplexer Reducing Inputs with K-map: Example: f(x,y,z) = Σm(0,2,3,5)
Reducing 4-input to 3-input Example:Implement the function f(w,x,y,z) = Σm(0,1,5,6,7,9,12,15) using multiplexer 3-variable Function Using 8-to-1 mux: Implement the function F(X,Y,Z) = S(1,3,5,6) using an 8-to-1 mux. Connect the input variables X, Y, Z to mux select lines. Mux data input lines 1, 3, 5, 6 that correspond to the function minterms are connected to 1. The remaining mux data input lines 0, 2, 4, 7 are connected to 0.
3-variable Function Using 4-to-1 mux: Implement the function F(X,Y,Z) = S(0,1,3,6) using a single 4-to-1 mux and an inverter. We choose the two most significant inputs X, Y as mux select lines. Truth Table: Select i X Y Z F Mux Input i 0 0 0 0 1 1 0 0 0 1 1 1 1 0 1 0 0 Z 1 0 1 1 1 Z 2 1 0 0 0 0 2 1 0 1 0 0 3 1 1 0 1 Z' 3 1 1 1 0 Z' We determine multiplexer input line i values by comparing the remaining Z and the function F for the corresponding selection lines value i input variable when XY=00 the function F is 1 (for both Z=0, Z=1) thus mux input0 = 1 when XY=01 the function F is Z thus mux input1 = Z when XY=10 the function F is 0 (for both Z=0, Z=1) thus mux input2 = 0 when XY=11 the function F is Z' thus mux input3 = Z'
Example for logic function implementation using MUX DE-MULTIPLEXER: They are digital switches which connect data from one input source to one of n outputs.usually implemented by using n-to-2 n binary decoders where the decoder enable line is used for data input of the de-multiplexer.the figure below shows a de-multiplexer block diagram which has got s-bits-wide select input, one b-bitswide data input and n b-bits-wide outputs.
The operation of a de-multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the outputs, which is connected to the input. As you can see at any given point of time only one output gets connected to input. It Performs the reverse operation of a multiplexer Input lines are: - 1 data line - n select lines - maybe 1 enable Output lines are- 2 n output lines Block diagram of 2-to-4 Decoder with Input and Output Lines: A DEMUX basically reverses the MUX function.
It takes digital information from one line and distributes it to a given number of output lines. It also known as data distributor. The figure shows the logic circuit diagram of 1:4 De-multiplexer. The timing diagram shows the signal whether they high or Low S0,S1-select lines,d0, D1, D3,D4-data output lines De multiplexer Applications: A multiplexer/demultiplexer arrangement for information transmission