EE40 Midterm Review Prof. Nathan Cheung 10/29/2009 Slide 1
I feel I know the topics but I cannot solve the problems Now what? Slide 2
R L C Properties Slide 3
Ideal Voltage Source *Current depends d on circuit it connection, the given voltage drop is fixed i Ideal Current Source *Voltage depends on circuit connection, the given current is fixed i absorb power supply power absorb power 0 v 0 v supply power Slide 4
Recognize Voltage and Current Dividing Configurations R eq = R v R i i = ( ) Req i v s 1 1 R = Ri i i eq R = ( R eq i ) i s Memorize Voltage and Current Dividing Formulas Slide 5
Some connectivity is not amenable to simple inspection with simple voltage divider or current divider methods *Use Nodal or Mesh Analysis Slide 6
Nodal Analysis Define a GROUND Node (one less current variable) Apply A l KCL at extraordinary nodes Use supernode relationship for floating voltage sources Slide 7
Nodal Analysis: Supernodes To deal with floating voltage source (neither side is connected to the reference node) we use supernodes: Two equations: KCL for supernode Auxiliary equation for voltages (KVL) Slide 8
Tips for Nodal and Mesh Analyses Find one formulation which works for you and stick with same formulation and KCL/KVL sign convention throughout. Example KCL: KVL: Algebraic sum of currents leaving node = 0 Currents entering are included with a minus sign. Algebraic sum of voltage drops around loop = 0 Voltage rises are included with a minus sign. Slide 9
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Op Amp Model i 1 v + i 2 v - R i + + v o V cc ~10 V slope = A >>1 v p v n _ R o i o v o A(v 1 v 2 ) ~1 mv -V cc Virtual short condition v+ = v i+=0 i =0 Not true if v o > + V rail or V V rail Slide 12
Op Amp Operation w/o Negative Feedback (Digital Operations) 1. Simple comparator with 1 Volt threshold: V is set to 0 Volts (logic 0 ) V + is set to 2 Volts (logic 1 ) A = 100 V IN + V 0 1V + 2. Simple inverter with 1 Volt threshold: V is set to 0 Volts (logic 0 ) V + is set to 2 Volts (logic 1 ) 2 A = 100 1 + V 0 0 1V + 2 1 0 V 0 If V IN > 101V 1.01 V, V 0 = 2V = Logic 1 1 2 V IN If V IN < 0.99 V, V 0 = 0V = Logic 0 V 0 If VIN < 0.99 V, V 0 = 2V = Logic 1 1 2 0 g If V IN > 1.01 V, V 0 = 0V = Logic 0 V IN Slide 13 V IN
Digital-to-Analog Conversion (analog operation) Weighted-adder D/A converter 8V + - S4 S3 S2 S1 10K 20K 40K 5K 80K + + V 0 4-Bit D/A S1 closed if LSB =1 S2 " if next bit = 1 (Transistors are used S3 " if " " = 1 as electronic switches) S4 " if MSB = 1 Slide 14 Binary number Analog output (volts) 0.5 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1.5 0 1 0 0 2 0 1 0 1 2.5 0 1 1 0 3 0 1 1 1 3.5 1 0 0 0 4 1 0 0 1 4.5 1 0 1 0 5 1 0 1 1 5.5 1 1 0 0 6 1 1 0 1 6.5 1 1 1 0 7 1 1 1 1 7.5 MSB LSB
First-Order Circuit Step Response 1. Identify the variable of interest For RL circuits, it is usually the inductor current i L L( (t) For RC circuits, it is usually the capacitor voltage v c (t) 2. Determine the initial value (at t = t 0+ )ofthe variable Assuming that the circuit reached steady state before t 0, use the fact that an inductor behaves like a short circuit in steady state or that a capacitor behaves like an open circuit it in steady state t Slide 15
Procedure (cont d) 3. Calculate the final value of the variable (its value as t ) ) Again, make use of the fact that an inductor behaves like a short circuit in steady state (t ) or that a capacitor behaves like an open circuit in steady state (t ) 4. Calculate the time constant for the circuit τ = L/R for an RL circuit, where R is the Thévenin equivalent resistance seen by the inductor τ = RC for an RC circuit where R is the Thévenin equivalent resistance seen by the capacitor Slide 16
Example : v(t) across a capacitor * v is continuous v(t) v(t) t o t t o t Note: i(t) d/di dv/dt is not continuous Slide 17
First Order Circuit Complete Solution Voltages and currents in a 1st order circuit satisfy a differential equation of the form dx () t xt () + τ = f() t dt f(t) is called the forcing function. The complete solution is the SUM of a particular solution and a complementary solution xt () = x() t + x() t p c Slide 18
Particular Solutions of some simple force function f(t) x p (t) 0 0 constant sin(t) t tsin(t) exp(-t)sin(t) constant Asin(t)+Bcos(t) A+Bt Atsin(t) +Btcos(t)+Csin(t)+Dcos(t) Aexp(-t)sin(t) + Bexp(-t)cos(t) Slide 19
Complementary Solution xc(t) Complementary solution is a solution of the homogeneous equation (i.e. f(t)=0 ). dx () t xt () + τ c = 0 c dt xt c () Homogeneous equation t / τ Solution to the homogeneous = Ke equation. To determine K, match xt () = x() t + x() t p c with ihthe initial ii condition dii value x(t) () Slide 20
Second Order Circuits The voltage and current in a second order circuit is the solution to a differential equation of the following form: 2 d x () t dx () t 2 α ω 2 0 dt + 2 + xt ( ) = f ( t) dt xt () = x () t + x () t p c α = R/2L ω 2 o = 1/(LC) X p (t) is any particular solution and X c (t) is the complementary solution (solution of the homogeneous equation chosen so that the total solution matches the initial conditions). Slide 21
The Particular Solution A particular solution x p (t) can usually be chosen as a weighted sum of f(t) and its first and second derivatives. If f(t) () is constant, then x p p( (t) can be chosen to be constant. Its value is determined by the equation. If f(t) is sinusoidal, then x p (t) can be chosen to be sinusoidal with the same frequency. The magnitude and phase are determined by the equation. Slide 22
The Complementary Solution To find the general form of the solution of the homogeneous equation we may start with trying the following form: st x () t = Ke c s must satisfy an algebraic equation determined d by the coefficients of the differential equation: 2 st st dke dke 2 α ω0 st + 2 + Ke = 0 2 dt dt ske + 2 α ske + ω Ke = 0 2 st st 2 st 0 s + 2α s+ ω = 0 2 2 0 Slide 23
RLC Complex Impedances Slide 24
Series and Parallel Resonance Slide 25
Maximum Average Power Transfer Z s + v s ( t ) Z L ( - t) v L source load * Z L = Z s Conjugate of Z s gives max. power transfer Slide 26
H(ω) in Poles and Zeros Format db db Log ω H( ω) = constant ω Zero +20dB/dec Log ω 1 1 + j ω / ω pole ( + ω ω )... 1 j / zero db +20dB/dec Log ω ω=1 Slide 27 dbpole Log ω -20dB/dec
Bode Phase Plot Phase For Single Pole or Single Zero, 45 o per decade Slide 28
Bode Plots: Straight Lines Approximation In addition, we need to check H(ω) as ω -> 0 and H(ω) ( ) as ω ->. Slide 29
Bode Plot: Quick Summary In addition, we need to check H(ω) as ω -> 0 and H(ω) ( ) as ω - >. Slide 30
Bode Plot: Exact plot of Quadratic Pole Second Order LowPass Filter V C 1 HLP ( ω ) = = V M LP ( ω) = S 2 ( 1 ω LC ) 1 + jωrc { [ 2 ( ) ] ( ) } 2 2 1 ω / ω + ω / ω 1/ 2 1 LC 0 Q 2 1 ω L ω o = Q = ω o RC = o R 0 Slide 31
Common Filter Transfer Function vs. Freq H ( f ) H( f) Low Pass High Pass Frequency H ( f ) H ( f ) Frequency Band dpass Band dreject Frequency Frequency Slide 32
Cascaded Active Filters Slide 33
Number Base Number base representation with number base B Example d 31 d 30... d 1 d 0 is a 32 digit number value = d 31 B 31 + d 30 B 30 +... + d 1 B 1 + d 0 B 0 Example : Binary (B=2): 0,1 (In binary digits called bits ) 11010 = 1 2 4 + 1 2 3 + 0 2 2 + 1 2 1 + 0 2 0 = 16 + 8 + 2 = 26 Slide 34
A A = A A A A = 0 A 1 = A A0 A 0 = 0 A B = B A Boolean Algebra Relations A (B C) = (A B) C A+A = A A+A A = 1 A+1 = 1 A+0 = A A+B = B+A A (B+C) = A B +A C A B = A + B A B = A + B Slide 35 A+(B+C) = (A+B)+C De Morgan s laws
Exercise Verification by Truth Table F = ABC + AB + ABC + ABC Slide 36
Boolean Expression to Logic Gates Given a Boolean expression, that can be many different ways to implement with equivalents Example: A B= AB + AB = (A + B)(A + B) = AB + A + B A B A B AB How about these? A B AB Slide 37
Notations of Hambley Textbook Sum of Products (SOP) Row # A B C D 0 0 0 0 1 = (,,, ) 1 0 0 1 0 2 0 1 0 1 D Σ m(0,2,6,7) Product of Sums (POS) D = Π M(1,3,4,5) 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 1 7 1 1 1 1 Slide 38
SOP or POS? The Boolean Expression will appear shorter If the Truth table has less 1 s, SOP If the Truth Table has less 0 s s, POS After Minimization, both methods should give same results, unless there are don t care rows in the Truth Table. Slide 39
Karnaugh Maps 3-variable Karnaugh Map 4-variable Karnaugh Map * Arrows show example locations of logic PRODUCTS Slide 40
3-Variable SOP Example Slide 41
Timing Diagram Example: Ripple Counter Slide 42